arch/mips: introduce mips32r3 and mips64r3
PATCH 1/3 arch/mips: introduce mips32r3 and mips64r3
From: Thomas De Schampheleire <[email protected]>
It's unclear why Buildroot only defined MIPS 32/64 releases 1, 2, 5 and 6 while 3 exists as well.
Interesting fact:
"Release 4 was skipped because the number four is perceived as unlucky in many Asian cultures."
https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS64
--- arch/Config.in.mips | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-)
arch/Config.in.mips +18 -2
@@ -5,6 +5,9 @@ config BR2_MIPS_CPU_MIPS32 config BR2_MIPS_CPU_MIPS32R2 bool select BR2_MIPS_NAN_LEGACY +config BR2_MIPS_CPU_MIPS32R3 + bool + select BR2_MIPS_NAN_LEGACY config BR2_MIPS_CPU_MIPS32R5 bool select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
@@ -18,6 +21,9 @@ config BR2_MIPS_CPU_MIPS64 config BR2_MIPS_CPU_MIPS64R2 bool select BR2_MIPS_NAN_LEGACY +config BR2_MIPS_CPU_MIPS64R3 + bool + select BR2_MIPS_NAN_LEGACY config BR2_MIPS_CPU_MIPS64R5 bool select BR2_ARCH_NEEDS_GCC_AT_LEAST_5
@@ -34,8 +40,8 @@ choice help Specific CPU variant to use - 64bit cabable: 64, 64r2, 64r5, 64r6 - non-64bit capable: 32, 32r2, 32r5, 32r6 + 64bit capable: 64, 64r2, 64r3, 64r5, 64r6 + non-64bit capable: 32, 32r2, 32r3, 32r5, 32r6 config BR2_mips_32 bool "Generic MIPS32"
@@ -45,6 +51,10 @@ config BR2_mips_32r2 bool "Generic MIPS32R2" depends on !BR2_ARCH_IS_64 select BR2_MIPS_CPU_MIPS32R2 +config BR2_mips_32r3 + bool "Generic MIPS32R3" + depends on !BR2_ARCH_IS_64 + select BR2_MIPS_CPU_MIPS32R3 config BR2_mips_32r5 bool "Generic MIPS32R5" depends on !BR2_ARCH_IS_64
@@ -95,6 +105,10 @@ config BR2_mips_64r2 bool "Generic MIPS64R2" depends on BR2_ARCH_IS_64 select BR2_MIPS_CPU_MIPS64R2 +config BR2_mips_64r3 + bool "Generic MIPS64R3" + depends on BR2_ARCH_IS_64 + select BR2_MIPS_CPU_MIPS64R3 config BR2_mips_64r5 bool "Generic MIPS64R5" depends on BR2_ARCH_IS_64
@@ -213,6 +227,7 @@ config BR2_ENDIAN config BR2_GCC_TARGET_ARCH default "mips32" if BR2_mips_32 default "mips32r2" if BR2_mips_32r2 + default "mips32r3" if BR2_mips_32r3 default "mips32r5" if BR2_mips_32r5 default "mips32r6" if BR2_mips_32r6 default "interaptiv" if BR2_mips_interaptiv
@@ -222,6 +237,7 @@ config BR2_GCC_TARGET_ARCH default "mips32r2" if BR2_mips_xburst default "mips64" if BR2_mips_64 default "mips64r2" if BR2_mips_64r2 + default "mips64r3" if BR2_mips_64r3 default "mips64r5" if BR2_mips_64r5 default "mips64r6" if BR2_mips_64r6 default "i6400" if BR2_mips_i6400
Signature · 1 line
2.19.2
PATCH 2/3 arch/mips: add (Marvell) Octeon II processor
From: Thomas De Schampheleire <[email protected]>
The compiler recognizes a specific 'march' value for Octeon II processors, so create a 'Target Architecture Variant' entry for it in the target menu.
--- arch/Config.in.mips | 8 ++++++++ 1 file changed, 8 insertions(+)
arch/Config.in.mips +8 -0
@@ -122,6 +122,13 @@ config BR2_mips_i6400 depends on BR2_ARCH_IS_64 select BR2_MIPS_CPU_MIPS64R6 select BR2_ARCH_NEEDS_GCC_AT_LEAST_6 +config BR2_mips_octeon2 + bool "Octeon II" + depends on BR2_ARCH_IS_64 + select BR2_MIPS_CPU_MIPS64R2 + help + Marvell (formerly Cavium Networks) Octeon II CN60XX + processors. config BR2_mips_p6600 bool "P6600" depends on BR2_ARCH_IS_64
@@ -241,6 +248,7 @@ config BR2_GCC_TARGET_ARCH default "mips64r5" if BR2_mips_64r5 default "mips64r6" if BR2_mips_64r6 default "i6400" if BR2_mips_i6400 + default "octeon2" if BR2_mips_octeon2 default "p6600" if BR2_mips_p6600 config BR2_MIPS_OABI32
Signature · 1 line
2.19.2
PATCH 3/3 arch/mips: add (Marvell) Octeon III processor
In reply to Thomas De SchampheleireFrom: Thomas De Schampheleire <[email protected]>
The compiler recognizes a specific 'march' value for Octeon III processors, so create a 'Target Architecture Variant' entry for it in the target menu.
Note: support for '-march=octeon3' was added in gcc 5.x. However, the official compiler provided by Marvell (Cavium Networks) uses gcc 4.7.x (and supports -march=octeon3 via their own modifications). For this reason, no line 'select BR2_ARCH_NEEDS_GCC_AT_LEAST_5' is added.
--- arch/Config.in.mips | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/Config.in.mips +9 -0
@@ -129,6 +129,13 @@ config BR2_mips_octeon2 help Marvell (formerly Cavium Networks) Octeon II CN60XX processors. +config BR2_mips_octeon3 + bool "Octeon III" + depends on BR2_ARCH_IS_64 + select BR2_MIPS_CPU_MIPS64R3 + help + Marvell (formerly Cavium Networks) Octeon III CN7XXX + processors. config BR2_mips_p6600 bool "P6600" depends on BR2_ARCH_IS_64
@@ -156,6 +163,7 @@ endchoice config BR2_MIPS_SOFT_FLOAT bool "Use soft-float" default y + depends on !BR2_mips_octeon3 # hard-float only select BR2_SOFT_FLOAT help If your target CPU does not have a Floating Point Unit (FPU)
@@ -249,6 +257,7 @@ config BR2_GCC_TARGET_ARCH default "mips64r6" if BR2_mips_64r6 default "i6400" if BR2_mips_i6400 default "octeon2" if BR2_mips_octeon2 + default "octeon3" if BR2_mips_octeon3 default "p6600" if BR2_mips_p6600 config BR2_MIPS_OABI32
Signature · 1 line
2.19.2
PATCH 3/3 arch/mips: add (Marvell) Octeon III processor
Hello Thomas,
arch/Config.in.mips endchoice · line 165
Quoted 4 lines · On Wed, 30 Jan 2019 21:12:24 +0100 Thomas De Schampheleire…
arch/Config.in.mips +0
-0@@ -156,6 +163,7 @@ endchoice config BR2_MIPS_SOFT_FLOAT bool "Use soft-float" default y
Not related directly to your patch, but MIPS related anyway: does it make sense to default to soft-float ?
Wouldn't it better to have, like on ARM, an indication of which MIPS cores support hardware floating point, and for those, default to using hardware floating point ?
Thanks,
Thoams
Signature · 3 lines
Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com
PATCH 3/3 arch/mips: add (Marvell) Octeon III processor
El mi?., 30 ene. 2019 a las 21:29, Thomas Petazzoni (<[email protected]>) escribi?:
Quoted 14 lines
Hello Thomas,
arch/Config.in.mips endchoice · line 165
Quoted 4 lines · On Wed, 30 Jan 2019 21:12:24 +0100 Thomas De Schampheleire…
arch/Config.in.mips +0
-0@@ -156,6 +163,7 @@ endchoice config BR2_MIPS_SOFT_FLOAT bool "Use soft-float" default yNot related directly to your patch, but MIPS related anyway: does it make sense to default to soft-float ?
Quoted 3 lines
Wouldn't it better to have, like on ARM, an indication of which MIPS cores support hardware floating point, and for those, default to using hardware floating point ?
I don't know the reason why it was done this way. Perhaps historically most MIPS had no floating-point unit?
Or maybe because originally there were only 'generic' variants described, like 'mips32r2' for which it is not defined if there is a floating-point unit in the actual SoC implementation.
In any case, the strategy you describe sounds more 'neutral'. But it requires investigating whether or not the existing processors definitely/maybe/never have an FPU.
/Thomas
PATCH 3/3 arch/mips: add (Marvell) Octeon III processor
In reply to Thomas De SchampheleireQuoted 9 lines · Thomas De Schampheleire
From: Thomas De Schampheleire <[email protected]>
The compiler recognizes a specific 'march' value for Octeon III processors, so create a 'Target Architecture Variant' entry for it in the target menu.
Note: support for '-march=octeon3' was added in gcc 5.x. However, the official compiler provided by Marvell (Cavium Networks) uses gcc 4.7.x (and supports -march=octeon3 via their own modifications). For this reason, no line 'select
BR2_ARCH_NEEDS_GCC_AT_LEAST_5' is added.
Actually, I wonder if we should not just remove the GCC_AT_LEAST dependencies
in the custom external toolchain. It's kind of a "you know what you're doing" situation.
Perhaps it would make more sense to extend check_unusable_toolchain with a
configure-style compile-and-link test of a simple main(){} program to check if all the arch et al options that we pass in the wrapper are supported, and error out at that time.
Regards,
Arnout
PATCH 1/3 arch/mips: introduce mips32r3 and mips64r3
In reply to Thomas De SchampheleireQuoted 10 lines · On Wed, 30 Jan 2019 21:12:22 +0100 Thomas De Schampheleire…
From: Thomas De Schampheleire <[email protected]>
It's unclear why Buildroot only defined MIPS 32/64 releases 1, 2, 5 and 6 while 3 exists as well.
Interesting fact:
"Release 4 was skipped because the number four is perceived as unlucky in many Asian cultures."
https://en.wikipedia.org/wiki/MIPS_architecture#MIPS32/MIPS64
Quoted 4 lines
Signed-off-by Thomas De Schampheleire <[email protected]>--- arch/Config.in.mips | 20 ++++++++++++++++++-- 1 file changed, 18 insertions(+), 2 deletions(-)
Patch series applied. Thanks!
Thomas
Signature · 3 lines
Thomas Petazzoni, CTO, Bootlin Embedded Linux and Kernel engineering https://bootlin.com