Skip to contentSkip to conversation

dts: Revert at91 switch to new PMC clock bindings

PATCH In review Ladislav Michl 3 participants 6 messages Feb 4, 2019 – Feb 17, 2019

Subsystems (6)
Device tree bindings Arm (32-bit) Arm sub-architectures Common clk +2 more subsystems
lore
Share & tools
lore

Ladislav Michl

author
#0 lore raw

PATCH 1/1 dts: Revert at91 switch to new PMC clock bindings

Recent DTS update brought in switch to the new PMC clock bindings, however we do not support that yet. Revert this change until PMC clock bindings support is implemented.

Fixes 33fdc89d4cbd ("dts: update to v5.0-rc1")
Signed-off-by Ladislav Michl <[email protected]>

---
Disclaimer: Runtime tested only on at91sam9g20.

 dts/src/arm/at91sam9260.dtsi       | 308 ++++++++++++++++++++++++---
 dts/src/arm/at91sam9261.dtsi       | 287 +++++++++++++++++++++++--
 dts/src/arm/at91sam9263.dtsi       | 315 +++++++++++++++++++++++++---
 dts/src/arm/at91sam9g15.dtsi       |   4 -
 dts/src/arm/at91sam9g20.dtsi       |  23 +-
 dts/src/arm/at91sam9g25.dtsi       |   4 -
 dts/src/arm/at91sam9g25ek.dts      |   4 +-
 dts/src/arm/at91sam9g35.dtsi       |   4 -
 dts/src/arm/at91sam9rl.dtsi        | 239 +++++++++++++++++++--
 dts/src/arm/at91sam9x25.dtsi       |   4 -
 dts/src/arm/at91sam9x35.dtsi       |   4 -
 dts/src/arm/at91sam9x5.dtsi        | 326 ++++++++++++++++++++++++++---
 dts/src/arm/at91sam9x5_can.dtsi    |  18 +-
 dts/src/arm/at91sam9x5_isi.dtsi    |  11 +-
 dts/src/arm/at91sam9x5_lcd.dtsi    |  19 +-
 dts/src/arm/at91sam9x5_macb0.dtsi  |  11 +-
 dts/src/arm/at91sam9x5_macb1.dtsi  |  11 +-
 dts/src/arm/at91sam9x5_usart3.dtsi |  11 +-
 18 files changed, 1434 insertions(+), 169 deletions(-)
dts/src/arm/at91sam9260.dtsi +278 -30
index 7cd9c3bc4..9118e29b6 100644
@@ -113,28 +113,276 @@
 				compatible = "atmel,at91sam9260-pmc", "syscon";
 				reg = <0xfffffc00 0x100>;
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
-				#clock-cells = <2>;
-				clocks = <&slow_xtal>, <&main_xtal>;
-				clock-names = "slow_xtal", "main_xtal";
+				interrupt-controller;
+				#address-cells = <1>;
+				#size-cells = <0>;
+				#interrupt-cells = <1>;
+
+				main_osc: main_osc {
+					compatible = "atmel,at91rm9200-clk-main-osc";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_MOSCS>;
+					clocks = <&main_xtal>;
+				};
+
+				main: mainck {
+					compatible = "atmel,at91rm9200-clk-main";
+					#clock-cells = <0>;
+					clocks = <&main_osc>;
+				};
+
+				slow_rc_osc: slow_rc_osc {
+					compatible = "fixed-clock";
+					#clock-cells = <0>;
+					clock-frequency = <32768>;
+					clock-accuracy = <50000000>;
+				};
+
+				clk32k: slck {
+					compatible = "atmel,at91sam9260-clk-slow";
+					#clock-cells = <0>;
+					clocks = <&slow_rc_osc>, <&slow_xtal>;
+				};
+
+				plla: pllack {
+					compatible = "atmel,at91rm9200-clk-pll";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_LOCKA>;
+					clocks = <&main>;
+					reg = <0>;
+					atmel,clk-input-range = <1000000 32000000>;
+					#atmel,pll-clk-output-range-cells = <4>;
+					atmel,pll-clk-output-ranges = <80000000 160000000 0 1>,
+								<150000000 240000000 2 1>;
+				};
+
+				pllb: pllbck {
+					compatible = "atmel,at91rm9200-clk-pll";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_LOCKB>;
+					clocks = <&main>;
+					reg = <1>;
+					atmel,clk-input-range = <1000000 5000000>;
+					#atmel,pll-clk-output-range-cells = <4>;
+					atmel,pll-clk-output-ranges = <70000000 130000000 1 1>;
+				};
+
+				mck: masterck {
+					compatible = "atmel,at91rm9200-clk-master";
+					#clock-cells = <0>;
+					interrupts-extended = <&pmc AT91_PMC_MCKRDY>;
+					clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+					atmel,clk-output-range = <0 105000000>;
+					atmel,clk-divisors = <1 2 4 0>;
+				};
+
+				usb: usbck {
+					compatible = "atmel,at91rm9200-clk-usb";
+					#clock-cells = <0>;
+					atmel,clk-divisors = <1 2 4 0>;
+					clocks = <&pllb>;
+				};
+
+				prog: progck {
+					compatible = "atmel,at91rm9200-clk-programmable";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					interrupt-parent = <&pmc>;
+					clocks = <&clk32k>, <&main>, <&plla>, <&pllb>;
+
+					prog0: prog0 {
+						#clock-cells = <0>;
+						reg = <0>;
+						interrupts = <AT91_PMC_PCKRDY(0)>;
+					};
+
+					prog1: prog1 {
+						#clock-cells = <0>;
+						reg = <1>;
+						interrupts = <AT91_PMC_PCKRDY(1)>;
+					};
+				};
+
+				systemck {
+					compatible = "atmel,at91rm9200-clk-system";
+					#address-cells = <1>;
+					#size-cells = <0>;
+
+					uhpck: uhpck {
+						#clock-cells = <0>;
+						reg = <6>;
+						clocks = <&usb>;
+					};
+
+					udpck: udpck {
+						#clock-cells = <0>;
+						reg = <7>;
+						clocks = <&usb>;
+					};
+
+					pck0: pck0 {
+						#clock-cells = <0>;
+						reg = <8>;
+						clocks = <&prog0>;
+					};
+
+					pck1: pck1 {
+						#clock-cells = <0>;
+						reg = <9>;
+						clocks = <&prog1>;
+					};
+				};
+
+				periphck {
+					compatible = "atmel,at91rm9200-clk-peripheral";
+					#address-cells = <1>;
+					#size-cells = <0>;
+					clocks = <&mck>;
+
+					pioA_clk: pioA_clk {
+						#clock-cells = <0>;
+						reg = <2>;
+					};
+
+					pioB_clk: pioB_clk {
+						#clock-cells = <0>;
+						reg = <3>;
+					};
+
+					pioC_clk: pioC_clk {
+						#clock-cells = <0>;
+						reg = <4>;
+					};
+
+					adc_clk: adc_clk {
+						#clock-cells = <0>;
+						reg = <5>;
+					};
+
+					usart0_clk: usart0_clk {
+						#clock-cells = <0>;
+						reg = <6>;
+					};
+
+					usart1_clk: usart1_clk {
+						#clock-cells = <0>;
+						reg = <7>;
+					};
+
+					usart2_clk: usart2_clk {
+						#clock-cells = <0>;
+						reg = <8>;
+					};
+
+					mci0_clk: mci0_clk {
+						#clock-cells = <0>;
+						reg = <9>;
+					};
+
+					udc_clk: udc_clk {
+						#clock-cells = <0>;
+						reg = <10>;
+					};
+
+					twi0_clk: twi0_clk {
+						reg = <11>;
+						#clock-cells = <0>;
+					};
+
+					spi0_clk: spi0_clk {
+						#clock-cells = <0>;
+						reg = <12>;
+					};
+
+					spi1_clk: spi1_clk {
+						#clock-cells = <0>;
+						reg = <13>;
+					};
+
+					ssc0_clk: ssc0_clk {
+						#clock-cells = <0>;
+						reg = <14>;
+					};
+
+					tc0_clk: tc0_clk {
+						#clock-cells = <0>;
+						reg = <17>;
+					};
+
+					tc1_clk: tc1_clk {
+						#clock-cells = <0>;
+						reg = <18>;
+					};
+
+					tc2_clk: tc2_clk {
+						#clock-cells = <0>;
+						reg = <19>;
+					};
+
+					ohci_clk: ohci_clk {
+						#clock-cells = <0>;
+						reg = <20>;
+					};
+
+					macb0_clk: macb0_clk {
+						#clock-cells = <0>;
+						reg = <21>;
+					};
+
+					isi_clk: isi_clk {
+						#clock-cells = <0>;
+						reg = <22>;
+					};
+
+					usart3_clk: usart3_clk {
+						#clock-cells = <0>;
+						reg = <23>;
+					};
+
+					uart0_clk: uart0_clk {
+						#clock-cells = <0>;
+						reg = <24>;
+					};
+
+					uart1_clk: uart1_clk {
+						#clock-cells = <0>;
+						reg = <25>;
+					};
+
+					tc3_clk: tc3_clk {
+						#clock-cells = <0>;
+						reg = <26>;
+					};
+
+					tc4_clk: tc4_clk {
+						#clock-cells = <0>;
+						reg = <27>;
+					};
+
+					tc5_clk: tc5_clk {
+						#clock-cells = <0>;
+						reg = <28>;
+					};
+				};
 			};
 
 			rstc@fffffd00 {
 				compatible = "atmel,at91sam9260-rstc";
 				reg = <0xfffffd00 0x10>;
-				clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
+				clocks = <&clk32k>;
 			};
 
 			shdwc@fffffd10 {
 				compatible = "atmel,at91sam9260-shdwc";
 				reg = <0xfffffd10 0x10>;
-				clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
+				clocks = <&clk32k>;
 			};
 
 			pit: timer@fffffd30 {
 				compatible = "atmel,at91sam9260-pit";
 				reg = <0xfffffd30 0xf>;
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
-				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+				clocks = <&mck>;
 			};
 
 			tcb0: timer@fffa0000 {

@@ -145,7 +393,7 @@
 				interrupts = <17 IRQ_TYPE_LEVEL_HIGH 0
 					      18 IRQ_TYPE_LEVEL_HIGH 0
 					      19 IRQ_TYPE_LEVEL_HIGH 0>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 17>, <&pmc PMC_TYPE_PERIPHERAL 18>, <&pmc PMC_TYPE_PERIPHERAL 19>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
+				clocks = <&tc0_clk>, <&tc1_clk>, <&tc2_clk>, <&clk32k>;
 				clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
 			};
 

@@ -157,7 +405,7 @@
 				interrupts = <26 IRQ_TYPE_LEVEL_HIGH 0
 					      27 IRQ_TYPE_LEVEL_HIGH 0
 					      28 IRQ_TYPE_LEVEL_HIGH 0>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 26>, <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 28>, <&pmc PMC_TYPE_CORE PMC_SLOW>;
+				clocks = <&tc3_clk>, <&tc4_clk>, <&tc5_clk>, <&clk32k>;
 				clock-names = "t0_clk", "t1_clk", "t2_clk", "slow_clk";
 			};
 

@@ -498,7 +746,7 @@
 					gpio-controller;
 					interrupt-controller;
 					#interrupt-cells = <2>;
-					clocks = <&pmc PMC_TYPE_PERIPHERAL 2>;
+					clocks = <&pioA_clk>;
 				};
 
 				pioB: gpio@fffff600 {

@@ -509,7 +757,7 @@
 					gpio-controller;
 					interrupt-controller;
 					#interrupt-cells = <2>;
-					clocks = <&pmc PMC_TYPE_PERIPHERAL 3>;
+					clocks = <&pioB_clk>;
 				};
 
 				pioC: gpio@fffff800 {

@@ -520,7 +768,7 @@
 					gpio-controller;
 					interrupt-controller;
 					#interrupt-cells = <2>;
-					clocks = <&pmc PMC_TYPE_PERIPHERAL 4>;
+					clocks = <&pioC_clk>;
 				};
 			};
 

@@ -530,7 +778,7 @@
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_dbgu>;
-				clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+				clocks = <&mck>;
 				clock-names = "usart";
 				status = "disabled";
 			};

@@ -543,7 +791,7 @@
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart0>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 6>;
+				clocks = <&usart0_clk>;
 				clock-names = "usart";
 				status = "disabled";
 			};

@@ -556,7 +804,7 @@
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart1>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 7>;
+				clocks = <&usart1_clk>;
 				clock-names = "usart";
 				status = "disabled";
 			};

@@ -569,7 +817,7 @@
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart2>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				clocks = <&usart2_clk>;
 				clock-names = "usart";
 				status = "disabled";
 			};

@@ -582,7 +830,7 @@
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_usart3>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 23>;
+				clocks = <&usart3_clk>;
 				clock-names = "usart";
 				status = "disabled";
 			};

@@ -595,7 +843,7 @@
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_uart0>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>;
+				clocks = <&uart0_clk>;
 				clock-names = "usart";
 				status = "disabled";
 			};

@@ -608,7 +856,7 @@
 				atmel,use-dma-tx;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_uart1>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
+				clocks = <&uart1_clk>;
 				clock-names = "usart";
 				status = "disabled";
 			};

@@ -619,7 +867,7 @@
 				interrupts = <21 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb_rmii>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 21>, <&pmc PMC_TYPE_PERIPHERAL 21>;
+				clocks = <&macb0_clk>, <&macb0_clk>;
 				clock-names = "hclk", "pclk";
 				status = "disabled";
 			};

@@ -628,7 +876,7 @@
 				compatible = "atmel,at91sam9260-udc";
 				reg = <0xfffa4000 0x4000>;
 				interrupts = <10 IRQ_TYPE_LEVEL_HIGH 2>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 10>, <&pmc PMC_TYPE_SYSTEM 7>;
+				clocks = <&udc_clk>, <&udpck>;
 				clock-names = "pclk", "hclk";
 				status = "disabled";
 			};

@@ -639,7 +887,7 @@
 				interrupts = <11 IRQ_TYPE_LEVEL_HIGH 6>;
 				#address-cells = <1>;
 				#size-cells = <0>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 11>;
+				clocks = <&twi0_clk>;
 				status = "disabled";
 			};
 

@@ -650,7 +898,7 @@
 				#address-cells = <1>;
 				#size-cells = <0>;
 				pinctrl-names = "default";
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 9>;
+				clocks = <&mci0_clk>;
 				clock-names = "mci_clk";
 				status = "disabled";
 			};

@@ -661,7 +909,7 @@
 				interrupts = <14 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_ssc0_tx &pinctrl_ssc0_rx>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 14>;
+				clocks = <&ssc0_clk>;
 				clock-names = "pclk";
 				status = "disabled";
 			};

@@ -674,7 +922,7 @@
 				interrupts = <12 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi0>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 12>;
+				clocks = <&spi0_clk>;
 				clock-names = "spi_clk";
 				status = "disabled";
 			};

@@ -687,7 +935,7 @@
 				interrupts = <13 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_spi1>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 13>;
+				clocks = <&spi1_clk>;
 				clock-names = "spi_clk";
 				status = "disabled";
 			};

@@ -698,7 +946,7 @@
 				compatible = "atmel,at91sam9260-adc";
 				reg = <0xfffe0000 0x100>;
 				interrupts = <5 IRQ_TYPE_LEVEL_HIGH 0>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 5>, <&adc_op_clk>;
+				clocks = <&adc_clk>, <&adc_op_clk>;
 				clock-names = "adc_clk", "adc_op_clk";
 				atmel,adc-use-external-triggers;
 				atmel,adc-channels-used = <0xf>;

@@ -733,7 +981,7 @@
 				compatible = "atmel,at91sam9260-rtt";
 				reg = <0xfffffd20 0x10>;
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
-				clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
+				clocks = <&clk32k>;
 				status = "disabled";
 			};
 

@@ -741,7 +989,7 @@
 				compatible = "atmel,at91sam9260-wdt";
 				reg = <0xfffffd40 0x10>;
 				interrupts = <1 IRQ_TYPE_LEVEL_HIGH 7>;
-				clocks = <&pmc PMC_TYPE_CORE PMC_SLOW>;
+				clocks = <&clk32k>;
 				atmel,watchdog-type = "hardware";
 				atmel,reset-type = "all";
 				atmel,dbg-halt;

@@ -759,7 +1007,7 @@
 			compatible = "atmel,at91rm9200-ohci", "usb-ohci";
 			reg = <0x00500000 0x100000>;
 			interrupts = <20 IRQ_TYPE_LEVEL_HIGH 2>;
-			clocks = <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_PERIPHERAL 20>, <&pmc PMC_TYPE_SYSTEM 6>;
+			clocks = <&ohci_clk>, <&ohci_clk>, <&uhpck>;
 			clock-names = "ohci_clk", "hclk", "uhpck";
 			status = "disabled";
 		};

@@ -779,7 +1027,7 @@
 				  0x5 0x0 0x60000000 0x10000000
 				  0x6 0x0 0x70000000 0x10000000
 				  0x7 0x0 0x80000000 0x10000000>;
-			clocks = <&pmc PMC_TYPE_CORE PMC_MCK>;
+			clocks = <&mck>;
 			status = "disabled";
 
 			nand_controller: nand-controller {
dts/src/arm/at91sam9261.dtsi +264 -23

413 lines not on this page · raw message

dts/src/arm/at91sam9263.dtsi +285 -30

483 lines not on this page · raw message

dts/src/arm/at91sam9g15.dtsi +0 -4
index b34a6c65b..27de7dc0f 100644
@@ -24,10 +24,6 @@
 				       0x003fffff 0x003f8000 0x00000000  /* pioD */
 				      >;
 			};
-
-			pmc: pmc@fffffc00 {
-				compatible = "atmel,at91sam9g15-pmc", "atmel,at91sam9x5-pmc", "syscon";
-			};
 		};
 	};
 };
dts/src/arm/at91sam9g20.dtsi +22 -1
index e976fd6bc..90705ee60 100644
@@ -40,7 +40,28 @@
 			};
 
 			pmc: pmc@fffffc00 {
-				compatible = "atmel,at91sam9g20-pmc", "atmel,at91sam9260-pmc", "syscon";
+				plla: pllack {
+					atmel,clk-input-range = <2000000 32000000>;
+					atmel,pll-clk-output-ranges = <745000000 800000000 0 0>,
+								<695000000 750000000 1 0>,
+								<645000000 700000000 2 0>,
+								<595000000 650000000 3 0>,
+								<545000000 600000000 0 1>,
+								<495000000 550000000 1 1>,
+								<445000000 500000000 2 1>,
+								<400000000 450000000 3 1>;
+				};
+
+				pllb: pllbck {
+					compatible = "atmel,at91sam9g20-clk-pllb";
+					atmel,clk-input-range = <2000000 32000000>;
+					atmel,pll-clk-output-ranges = <30000000 100000000 0 0>;
+				};
+
+				mck: masterck {
+					atmel,clk-output-range = <0 133000000>;
+					atmel,clk-divisors = <1 2 4 6>;
+				};
 			};
 		};
 	};
dts/src/arm/at91sam9g25.dtsi +0 -4
index d8bb56253..0898213f3 100644
@@ -26,10 +26,6 @@
 				       0x003fffff 0x003f8000 0x00000000  /* pioD */
 				      >;
 			};
-
-			pmc: pmc@fffffc00 {
-				compatible = "atmel,at91sam9g25-pmc", "atmel,at91sam9x5-pmc", "syscon";
-			};
 		};
 	};
 };
dts/src/arm/at91sam9g25ek.dts +2 -2
index ac730812a..31fecc2cd 100644
@@ -32,9 +32,9 @@
 					pinctrl-0 = <&pinctrl_pck0_as_isi_mck &pinctrl_sensor_power &pinctrl_sensor_reset>;
 					resetb-gpios = <&pioA 7 GPIO_ACTIVE_LOW>;
 					pwdn-gpios = <&pioA 13 GPIO_ACTIVE_HIGH>;
-					clocks = <&pmc PMC_TYPE_SYSTEM 8>;
+					clocks = <&pck0>;
 					clock-names = "xvclk";
-					assigned-clocks = <&pmc PMC_TYPE_SYSTEM 8>;
+					assigned-clocks = <&pck0>;
 					assigned-clock-rates = <25000000>;
 					status = "okay";
dts/src/arm/at91sam9g35.dtsi +0 -4
index 333e158fe..ff4115886 100644
@@ -25,10 +25,6 @@
 				       0x003fffff 0x003f8000 0x00000000  /* pioD */
 				      >;
 			};
-
-			pmc: pmc@fffffc00 {
-				compatible = "atmel,at91sam9g35-pmc", "atmel,at91sam9x5-pmc", "syscon";
-			};
 		};
 	};
 };
dts/src/arm/at91sam9rl.dtsi +216 -23

365 lines not on this page · raw message

dts/src/arm/at91sam9x25.dtsi +0 -4
index a99703a26..3c5fa3388 100644
@@ -27,10 +27,6 @@
 				       0x003fffff 0x003f8000 0x00000000  /* pioD */
 				      >;
 			};
-
-			pmc: pmc@fffffc00 {
-				compatible = "atmel,at91sam9x25-pmc", "atmel,at91sam9x5-pmc", "syscon";
-			};
 		};
 	};
 };
dts/src/arm/at91sam9x35.dtsi +0 -4
index bca274d33..d9054e816 100644
@@ -26,10 +26,6 @@
 				       0x003fffff 0x003f8000 0x00000000  /* pioD */
 				      >;
 			};
-
-			pmc: pmc@fffffc00 {
-				compatible = "atmel,at91sam9x35-pmc", "atmel,at91sam9x5-pmc", "syscon";
-			};
 		};
 	};
 };
dts/src/arm/at91sam9x5.dtsi +293 -33

512 lines not on this page · raw message

dts/src/arm/at91sam9x5_can.dtsi +16 -2
index 125f9e3b4..8eb2f9c1b 100644
@@ -13,13 +13,27 @@
 / {
 	ahb {
 		apb {
+			pmc: pmc@fffffc00 {
+				periphck {
+					can0_clk: can0_clk {
+						#clock-cells = <0>;
+						reg = <29>;
+					};
+
+					can1_clk: can1_clk {
+						#clock-cells = <0>;
+						reg = <30>;
+					};
+				};
+			};
+
 			can0: can@f8000000 {
 				compatible = "atmel,at91sam9x5-can";
 				reg = <0xf8000000 0x300>;
 				interrupts = <29 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_can0_rx_tx>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 29>;
+				clocks = <&can0_clk>;
 				clock-names = "can_clk";
 				status = "disabled";
 			};

@@ -30,7 +44,7 @@
 				interrupts = <30 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_can1_rx_tx>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 30>;
+				clocks = <&can1_clk>;
 				clock-names = "can_clk";
 				status = "disabled";
 			};
dts/src/arm/at91sam9x5_isi.dtsi +10 -1
index c3e45b57b..8fc45ca4d 100644
@@ -44,13 +44,22 @@
 				};
 			};
 
+			pmc: pmc@fffffc00 {
+				periphck {
+					isi_clk: isi_clk {
+						#clock-cells = <0>;
+						reg = <25>;
+					};
+				};
+			};
+
 			isi: isi@f8048000 {
 				compatible = "atmel,at91sam9g45-isi";
 				reg = <0xf8048000 0x4000>;
 				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 5>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_isi_data_0_7>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>;
+				clocks = <&isi_clk>;
 				clock-names = "isi_clk";
 				status = "disabled";
 				port {
dts/src/arm/at91sam9x5_lcd.dtsi +18 -1
index 12595fb11..1629db9dd 100644
@@ -17,7 +17,7 @@
 				compatible = "atmel,at91sam9x5-hlcdc";
 				reg = <0xf8038000 0x4000>;
 				interrupts = <25 IRQ_TYPE_LEVEL_HIGH 0>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 25>, <&pmc PMC_TYPE_SYSTEM 3>, <&clk32k>;
+				clocks = <&lcdc_clk>, <&lcdck>, <&clk32k>;
 				clock-names = "periph_clk","sys_clk", "slow_clk";
 				status = "disabled";
 

@@ -143,6 +143,23 @@
 					};
 				};
 			};
+
+			pmc: pmc@fffffc00 {
+				periphck {
+					lcdc_clk: lcdc_clk {
+						#clock-cells = <0>;
+						reg = <25>;
+					};
+				};
+
+				systemck {
+					lcdck: lcdck {
+						#clock-cells = <0>;
+						reg = <3>;
+						clocks = <&mck>;
+					};
+				};
+			};
 		};
 	};
 };
dts/src/arm/at91sam9x5_macb0.dtsi +10 -1
index 57c2e5a4f..73d7e3096 100644
@@ -43,13 +43,22 @@
 				};
 			};
 
+			pmc: pmc@fffffc00 {
+				periphck {
+					macb0_clk: macb0_clk {
+						#clock-cells = <0>;
+						reg = <24>;
+					};
+				};
+			};
+
 			macb0: ethernet@f802c000 {
 				compatible = "cdns,at91sam9260-macb", "cdns,macb";
 				reg = <0xf802c000 0x100>;
 				interrupts = <24 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb0_rmii>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 24>, <&pmc PMC_TYPE_PERIPHERAL 24>;
+				clocks = <&macb0_clk>, <&macb0_clk>;
 				clock-names = "hclk", "pclk";
 				status = "disabled";
 			};
dts/src/arm/at91sam9x5_macb1.dtsi +10 -1
index 59b8da87d..d81980c40 100644
@@ -31,13 +31,22 @@
 				};
 			};
 
+			pmc: pmc@fffffc00 {
+				periphck {
+					macb1_clk: macb1_clk {
+						#clock-cells = <0>;
+						reg = <27>;
+					};
+				};
+			};
+
 			macb1: ethernet@f8030000 {
 				compatible = "cdns,at91sam9260-macb", "cdns,macb";
 				reg = <0xf8030000 0x100>;
 				interrupts = <27 IRQ_TYPE_LEVEL_HIGH 3>;
 				pinctrl-names = "default";
 				pinctrl-0 = <&pinctrl_macb1_rmii>;
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 27>, <&pmc PMC_TYPE_PERIPHERAL 27>;
+				clocks = <&macb1_clk>, <&macb1_clk>;
 				clock-names = "hclk", "pclk";
 				status = "disabled";
 			};
dts/src/arm/at91sam9x5_usart3.dtsi +10 -1
index 9102dfbed..a32d12b40 100644
@@ -42,6 +42,15 @@
 				};
 			};
 
+			pmc: pmc@fffffc00 {
+				periphck {
+					usart3_clk: usart3_clk {
+						#clock-cells = <0>;
+						reg = <8>;
+					};
+				};
+			};
+
 			usart3: serial@f8028000 {
 				compatible = "atmel,at91sam9260-usart";
 				reg = <0xf8028000 0x200>;

@@ -51,7 +60,7 @@
 				dmas = <&dma1 1 AT91_DMA_CFG_PER_ID(14)>,
 				       <&dma1 1 (AT91_DMA_CFG_PER_ID(15) | AT91_DMA_CFG_FIFOCFG_ASAP)>;
 				dma-names = "tx", "rx";
-				clocks = <&pmc PMC_TYPE_PERIPHERAL 8>;
+				clocks = <&usart3_clk>;
 				clock-names = "usart";
 				status = "disabled";
 			};
Signature · 7 lines
2.20.1


_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
#1 lore raw

Hi Ladis,

Quoted 20 lines · Ladislav Michl

Recent DTS update brought in switch to the new PMC clock bindings, however we do not support that yet. Revert this change until PMC clock bindings support is implemented.

Fixes 33fdc89d4cbd ("dts: update to v5.0-rc1")
Signed-off-by Ladislav Michl <[email protected]>

---
Disclaimer: Runtime tested only on at91sam9g20.

 dts/src/arm/at91sam9260.dtsi       | 308 ++++++++++++++++++++++++---
 dts/src/arm/at91sam9261.dtsi       | 287 +++++++++++++++++++++++--
 dts/src/arm/at91sam9263.dtsi       | 315 +++++++++++++++++++++++++---
 dts/src/arm/at91sam9g15.dtsi       |   4 -
 dts/src/arm/at91sam9g20.dtsi       |  23 +-
 dts/src/arm/at91sam9g25.dtsi       |   4 -
 dts/src/arm/at91sam9g25ek.dts      |   4 +-
 dts/src/arm/at91sam9g35.dtsi       |   4 -
 dts/src/arm/at91sam9rl.dtsi        | 239 +++++++++++++++++++--
 dts/src/arm/at91sam9x25.dtsi       |   4 -
 dts/src/arm/at91sam9x35.dtsi       |   4 -
Quoted 8 lines
 dts/src/arm/at91sam9x5.dtsi        | 326 ++++++++++++++++++++++++++---
 dts/src/arm/at91sam9x5_can.dtsi    |  18 +-
 dts/src/arm/at91sam9x5_isi.dtsi    |  11 +-
 dts/src/arm/at91sam9x5_lcd.dtsi    |  19 +-
 dts/src/arm/at91sam9x5_macb0.dtsi  |  11 +-
 dts/src/arm/at91sam9x5_macb1.dtsi  |  11 +-
 dts/src/arm/at91sam9x5_usart3.dtsi |  11 +-
 18 files changed, 1434 insertions(+), 169 deletions(-)

dts/ contains a 1:1 copy from the upstream devicetree-rebasing repository. I can't apply any patches to this directory.

You would have to merge the changes to the changes to the corresponding files in arch/arm/dts. I'm not sure how feasible this is in this case since not only the clock nodes are changed, but also the references to the clocks.

For sure it should be enough to fix the trees you actually can test and care about.

Sascha

Signature · 9 lines
Pengutronix e.K.                           |                             |
Industrial Linux Solutions                 | http://www.pengutronix.de/  |
Peiner Str. 6-8, 31137 Hildesheim, Germany | Phone: +49-5121-206917-0    |
Amtsgericht Hildesheim, HRA 2686           | Fax:   +49-5121-206917-5555 |

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox
author
#2 lore raw
Quoted 35 lines · Sascha Hauer

Hi Ladis,

Quoted 20 lines · Ladislav Michl

Recent DTS update brought in switch to the new PMC clock bindings, however we do not support that yet. Revert this change until PMC clock bindings support is implemented.

Fixes 33fdc89d4cbd ("dts: update to v5.0-rc1")
Signed-off-by Ladislav Michl <[email protected]>

---
Disclaimer: Runtime tested only on at91sam9g20.

 dts/src/arm/at91sam9260.dtsi       | 308 ++++++++++++++++++++++++---
 dts/src/arm/at91sam9261.dtsi       | 287 +++++++++++++++++++++++--
 dts/src/arm/at91sam9263.dtsi       | 315 +++++++++++++++++++++++++---
 dts/src/arm/at91sam9g15.dtsi       |   4 -
 dts/src/arm/at91sam9g20.dtsi       |  23 +-
 dts/src/arm/at91sam9g25.dtsi       |   4 -
 dts/src/arm/at91sam9g25ek.dts      |   4 +-
 dts/src/arm/at91sam9g35.dtsi       |   4 -
 dts/src/arm/at91sam9rl.dtsi        | 239 +++++++++++++++++++--
 dts/src/arm/at91sam9x25.dtsi       |   4 -
 dts/src/arm/at91sam9x35.dtsi       |   4 -
Quoted 8 lines
 dts/src/arm/at91sam9x5.dtsi        | 326 ++++++++++++++++++++++++++---
 dts/src/arm/at91sam9x5_can.dtsi    |  18 +-
 dts/src/arm/at91sam9x5_isi.dtsi    |  11 +-
 dts/src/arm/at91sam9x5_lcd.dtsi    |  19 +-
 dts/src/arm/at91sam9x5_macb0.dtsi  |  11 +-
 dts/src/arm/at91sam9x5_macb1.dtsi  |  11 +-
 dts/src/arm/at91sam9x5_usart3.dtsi |  11 +-
 18 files changed, 1434 insertions(+), 169 deletions(-)

dts/ contains a 1:1 copy from the upstream devicetree-rebasing repository. I can't apply any patches to this directory.

Quoted 7 lines

You would have to merge the changes to the changes to the corresponding files in arch/arm/dts. I'm not sure how feasible this is in this case since not only the clock nodes are changed, but also the references to the clocks.

For sure it should be enough to fix the trees you actually can test and care about.

My board is not upstreamed as it does not make sense to do it so. It will never hit the market. Also upstream barebox does not use DT on any at91sam9g20 SoC, so it is safe. However there seem to be devices using AT91SAM9X5, SAMA5D3 and SAM9263 which depends on DT clocks and those are now broken. That said, I can live with one more offtree patch until new PMC clock binding is implemented (reverting change in arch/arm/dts is a bit painfull).

On the other hand, was the DT update to v5.0-rc1 and later to v5.0-rc2 motivated by any need or it is just an update to be in sync? If that is the latter I'd just revert it for barebox-2019.02.0 :)

Best regards,
ladis

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox

#3 lore raw
In reply to Sascha Hauer

Hi Sasha

Quoted 8 lines

dts/ contains a 1:1 copy from the upstream devicetree-rebasing repository. I can't apply any patches to this directory.

You would have to merge the changes to the changes to the corresponding files in arch/arm/dts. I'm not sure how feasible this is in this case since not only the clock nodes are changed, but also the references to the clocks.

The breakage was anticipated for my part, no suprise. I just do not have time to look into it at the moment.

The objective for my part is to have all at91 boards moved over to DT, so we will have to face this.

Or in other words patching all DT files in arch/arm/dts is not IMO a feasible long term solution.

I got a new at91sam9gxx board from Microchip two weeks ago, and that is my next DT target.
Then I hope we can maybe mass convert the rest of the at91 baords with some limited testing.

But this clock issue will need to be fixed first.

Sam

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox

#4 lore raw
In reply to Ladislav Michl

Hi Ladislav

Quoted 3 lines

Recent DTS update brought in switch to the new PMC clock bindings, however we do not support that yet. Revert this change until PMC clock bindings support is implemented.

I have now ported the clk code from the kernel so barebox have support for PMC bindings.
Can you give it a try and see if this works for you.

So far I have only tested this on at91sam9263ek - a DT enabled board. It builds for non-DT boards.

Patch needs a bit love before it is ready to submit. Could I get early feedback that would be great.

Sam

From 2cfaa800d9c4e845838a477f4cc11d4fdaf10952 Mon Sep 17 00:00:00 2001
From: Sam Ravnborg <[email protected]>
Date: Sat, 16 Feb 2019 21:14:11 +0100
Subject: [PATCH v1 1/1] clk: at91: update to new bindings

Based on kernel 5.0-rc6 update at91 clk support
to match the new PMC bindings.

This add new drivers:
at91sam9260, at91sam9rl, at91sam9x5, sama5d2 and sama5d4

They were copied from the kernel and saw minimal modifications required to build under barebox.

For the remaining files the updates in the kernel from last kernel copy was identified and similar changes were made in the files in barebox.

The kernel has a dt-compat file for all the backward compatibility code.
As barebox has only a few DT enabled at91 targets this was not ported over.

clk-programmable saw some extra changes - it had never been bulit. It is used only by at91sama5d2 - and barebox has no baord support for this cpu at the moment.

To match the kernel the CONFIG symbols used to select individual files were updated and there are now specific CONFIG symbols for SAMA5D2, SAM5D3 and SAMA5D4

In the kernel CLK_OF_DECLARE_DRIVER() can be used for a two step init. In barebox this is a simple one step init.
It was added to have less differences between the kernel and the barebox versions of the drivers.

Signed-off-by Sam Ravnborg <[email protected]>
---
 arch/arm/mach-at91/Kconfig          |  28 +-
 drivers/clk/at91/Makefile           |   5 +
 drivers/clk/at91/at91sam9260.c      | 497 ++++++++++++++++++++++++++++++++++++
 drivers/clk/at91/at91sam9rl.c       | 177 +++++++++++++
 drivers/clk/at91/at91sam9x5.c       | 315 +++++++++++++++++++++++
 drivers/clk/at91/clk-generated.c    | 185 +++-----------
 drivers/clk/at91/clk-h32mx.c        |  21 +-
 drivers/clk/at91/clk-main.c         | 112 +-------
 drivers/clk/at91/clk-master.c       |  94 +------
 drivers/clk/at91/clk-peripheral.c   |  82 +-----
 drivers/clk/at91/clk-pll.c          | 174 +------------
 drivers/clk/at91/clk-plldiv.c       |  27 +-
 drivers/clk/at91/clk-programmable.c |  83 +-----
 drivers/clk/at91/clk-slow.c         |  33 +--
 drivers/clk/at91/clk-smd.c          |  33 +--
 drivers/clk/at91/clk-system.c       |  42 +--
 drivers/clk/at91/clk-usb.c          |  94 +------
 drivers/clk/at91/clk-utmi.c         | 104 +++++---
 drivers/clk/at91/pmc.c              | 248 ++++++++++++++++++
 drivers/clk/at91/pmc.h              | 169 ++++++++++++
 drivers/clk/at91/sama5d2.c          | 342 +++++++++++++++++++++++++
 drivers/clk/at91/sama5d4.c          | 270 ++++++++++++++++++++
 include/dt-bindings/clock/at91.h    |  38 +++
 include/linux/clk.h                 |   7 +
 include/soc/at91/atmel-sfr.h        |  34 +++
 25 files changed, 2252 insertions(+), 962 deletions(-)
 create mode 100644 drivers/clk/at91/at91sam9260.c
 create mode 100644 drivers/clk/at91/at91sam9rl.c
 create mode 100644 drivers/clk/at91/at91sam9x5.c
 create mode 100644 drivers/clk/at91/sama5d2.c
 create mode 100644 drivers/clk/at91/sama5d4.c
 create mode 100644 include/dt-bindings/clock/at91.h
 create mode 100644 include/soc/at91/atmel-sfr.h
arch/arm/mach-at91/Kconfig +21 -7
index b101e61d2..164aedd80 100644
@@ -53,12 +53,28 @@ config SOC_AT91SAM9
 	select AT91SAM9_SMC
 	select CLOCKSOURCE_ATMEL_PIT
 	select PINCTRL
+	select HAVE_AT91_SMD
+	select HAVE_AT91_USB_CLK
+	select HAVE_AT91_UTMI
+
+config SOC_SAMA5D3
+	bool
+	select CPU_V7
+	select AT91SAM9_SMC
+	select CLOCKSOURCE_ATMEL_PIT
+	select HAVE_AT91_SMD
+	select HAVE_AT91_USB_CLK
+	select HAVE_AT91_UTMI
 
-config SOC_SAMA5
+config SOC_SAMA5D4
 	bool
 	select CPU_V7
 	select AT91SAM9_SMC
 	select CLOCKSOURCE_ATMEL_PIT
+	select HAVE_AT91_H32MX
+	select HAVE_AT91_SMD
+	select HAVE_AT91_USB_CLK
+	select HAVE_AT91_UTMI
 
 config ARCH_TEXT_BASE
 	hex

@@ -82,8 +98,9 @@ comment "Atmel AT91 System-on-Chip"
 config SOC_AT91RM9200
 	bool
 	select CPU_ARM920T
-	select HAVE_AT91_DBGU0
 	select HAS_AT91_ETHER
+	select HAVE_AT91_DBGU0
+	select HAVE_AT91_USB_CLK
 
 config SOC_AT91SAM9260
 	bool

@@ -122,9 +139,6 @@ config SOC_AT91SAM9X5
 	select SOC_AT91SAM9
 	select HAVE_AT91_DBGU0
 	select HAS_MACB
-	select HAVE_AT91_SMD
-	select HAVE_AT91_USB_CLK
-	select HAVE_AT91_UTMI
 	select COMMON_CLK_OF_PROVIDER
 	help
 	  Select this if you are using one of Atmel's AT91SAM9x5 family SoC.

@@ -188,14 +202,14 @@ config ARCH_AT91SAM9N12
 
 config ARCH_SAMA5D3
 	bool "SAMA5D3x"
-	select SOC_SAMA5
+	select SOC_SAMA5D3
 	select HAVE_AT91_DBGU1
 	select HAS_MACB
 	select HAVE_MACH_ARM_HEAD
 
 config ARCH_SAMA5D4
 	bool "SAMA5D4"
-	select SOC_SAMA5
+	select SOC_SAMA5D4
 	select HAVE_AT91_DBGU2
 	select HAS_MACB
 	select HAVE_MACH_ARM_HEAD
drivers/clk/at91/Makefile +5 -0
index 13e67bd35..ec41c15fa 100644
@@ -11,3 +11,8 @@ obj-$(CONFIG_HAVE_AT91_USB_CLK)		+= clk-usb.o
 obj-$(CONFIG_HAVE_AT91_SMD)		+= clk-smd.o
 obj-$(CONFIG_HAVE_AT91_H32MX)		+= clk-h32mx.o
 obj-$(CONFIG_HAVE_AT91_GENERATED_CLK)	+= clk-generated.o
+obj-$(CONFIG_SOC_AT91SAM9) 		+= at91sam9260.o
+obj-$(CONFIG_SOC_AT91SAM9) 		+= at91sam9rl.o
+obj-$(CONFIG_SOC_AT91SAM9) 		+= at91sam9x5.o
+obj-$(CONFIG_SOC_SAMA5D2) 		+= sama5d2.o
+obj-$(CONFIG_SOC_SAMA5D4) 		+= sama5d4.o
drivers/clk/at91/at91sam9260.c new file +497 -0

497 lines not on this page · raw message

drivers/clk/at91/at91sam9rl.c new file +177 -0

177 lines not on this page · raw message

drivers/clk/at91/at91sam9x5.c new file +315 -0

315 lines not on this page · raw message

drivers/clk/at91/clk-generated.c +32 -153

305 lines not on this page · raw message

drivers/clk/at91/clk-h32mx.c +7 -14
index e0daa4a31..14d1dd849 100644
@@ -15,7 +15,6 @@
 #include <linux/clk-provider.h>
 #include <linux/clkdev.h>
 #include <linux/clk/at91_pmc.h>
-#include <linux/of.h>
 #include <linux/regmap.h>
 #include <linux/mfd/syscon.h>
 

@@ -86,25 +85,21 @@ static const struct clk_ops h32mx_ops = {
 	.set_rate = clk_sama5d4_h32mx_set_rate,
 };
 
-static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
+struct clk *
+at91_clk_register_h32mx(struct regmap *regmap, const char *name,
+			const char *parent_name)
 {
 	struct clk_sama5d4_h32mx *h32mxclk;
 	struct clk_init_data init;
-	const char *parent_name;
-	struct regmap *regmap;
 	int ret;
 
-	regmap = syscon_node_to_regmap(of_get_parent(np));
-	if (IS_ERR(regmap))
-		return;
-
 	h32mxclk = kzalloc(sizeof(*h32mxclk), GFP_KERNEL);
 	if (!h32mxclk)
-		return;
+		return ERR_PTR(-ENOMEM);
 
 	parent_name = of_clk_get_parent_name(np, 0);
 
-	init.name = np->name;
+	init.name = name;
 	init.ops = &h32mx_ops;
 	init.parent_names = parent_name ? &parent_name : NULL;
 	init.num_parents = parent_name ? 1 : 0;

@@ -116,10 +111,8 @@ static void __init of_sama5d4_clk_h32mx_setup(struct device_node *np)
 	ret = clk_hw_register(NULL, &h32mxclk->hw);
 	if (ret) {
 		kfree(h32mxclk);
-		return;
+		return ERR_PTR(ret);
 	}
 
-	of_clk_add_hw_provider(np, of_clk_hw_simple_get, &h32mxclk->hw);
+	return &h32mxclk->hw;
 }
-CLK_OF_DECLARE(of_sama5d4_clk_h32mx_setup, "atmel,sama5d4-clk-h32mx",
-	       of_sama5d4_clk_h32mx_setup);
drivers/clk/at91/clk-main.c +5 -107

165 lines not on this page · raw message

drivers/clk/at91/clk-master.c +3 -91

122 lines not on this page · raw message

drivers/clk/at91/clk-peripheral.c +2 -80

109 lines not on this page · raw message

drivers/clk/at91/clk-pll.c +5 -169

208 lines not on this page · raw message

drivers/clk/at91/clk-plldiv.c +1 -26
index 917108e84..98d79ef59 100644
@@ -78,7 +78,7 @@ static const struct clk_ops plldiv_ops = {
 	.set_rate = clk_plldiv_set_rate,
 };
 
-static struct clk *
+struct clk *
 at91_clk_register_plldiv(struct regmap *regmap, const char *name,
 			 const char *parent_name)
 {

@@ -108,28 +108,3 @@ at91_clk_register_plldiv(struct regmap *regmap, const char *name,
 
 	return &plldiv->clk;
 }
-
-static int
-of_at91sam9x5_clk_plldiv_setup(struct device_node *np)
-{
-	struct clk *clk;
-	const char *parent_name;
-	const char *name = np->name;
-	struct regmap *regmap;
-
-	parent_name = of_clk_get_parent_name(np, 0);
-
-	of_property_read_string(np, "clock-output-names", &name);
-
-	regmap = syscon_node_to_regmap(of_get_parent(np));
-	if (IS_ERR(regmap))
-		return PTR_ERR(regmap);
-
-	clk = at91_clk_register_plldiv(regmap, name, parent_name);
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
-
-	return of_clk_add_provider(np, of_clk_src_simple_get, clk);
-}
-CLK_OF_DECLARE(at91sam9x5_clk_plldiv, "atmel,at91sam9x5-clk-plldiv",
-	       of_at91sam9x5_clk_plldiv_setup);
drivers/clk/at91/clk-programmable.c +4 -79

118 lines not on this page · raw message

drivers/clk/at91/clk-slow.c +1 -32
index d4981e7b4..d19f7e15a 100644
@@ -12,7 +12,6 @@
 
 #include <common.h>
 #include <clock.h>
-#include <of.h>
 #include <io.h>
 #include <linux/list.h>
 #include <linux/clk.h>

@@ -44,7 +43,7 @@ static const struct clk_ops sam9260_slow_ops = {
 	.get_parent = clk_sam9260_slow_get_parent,
 };
 
-static struct clk * __init
+struct clk * __init
 at91_clk_register_sam9260_slow(struct regmap *regmap,
 			       const char *name,
 			       const char **parent_names,

@@ -76,33 +75,3 @@ at91_clk_register_sam9260_slow(struct regmap *regmap,
 
 	return &slowck->clk;
 }
-
-static int of_at91sam9260_clk_slow_setup(struct device_node *np)
-{
-	struct clk *clk;
-	const char *parent_names[2];
-	unsigned int num_parents;
-	const char *name = np->name;
-	struct regmap *regmap;
-
-	num_parents = of_clk_get_parent_count(np);
-	if (num_parents != 2)
-		return -EINVAL;
-
-	of_clk_parent_fill(np, parent_names, num_parents);
-	regmap = syscon_node_to_regmap(of_get_parent(np));
-	if (IS_ERR(regmap))
-		return PTR_ERR(regmap);
-
-	of_property_read_string(np, "clock-output-names", &name);
-
-	clk = at91_clk_register_sam9260_slow(regmap, name, parent_names,
-					     num_parents);
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
-
-	return of_clk_add_provider(np, of_clk_src_simple_get, clk);
-}
-
-CLK_OF_DECLARE(at91sam9260_clk_slow, "atmel,at91sam9260-clk-slow",
-	       of_at91sam9260_clk_slow_setup);
drivers/clk/at91/clk-smd.c +1 -32
index 65c53efbb..e81f0d4d4 100644
@@ -10,7 +10,6 @@
 
 #include <common.h>
 #include <clock.h>
-#include <of.h>
 #include <io.h>
 #include <linux/list.h>
 #include <linux/clk.h>

@@ -115,7 +114,7 @@ static const struct clk_ops at91sam9x5_smd_ops = {
 	.set_rate = at91sam9x5_clk_smd_set_rate,
 };
 
-static struct clk *
+struct clk *
 at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
 			    const char **parent_names, u8 num_parents)
 {

@@ -140,33 +139,3 @@ at91sam9x5_clk_register_smd(struct regmap *regmap, const char *name,
 
 	return &smd->clk;
 }
-
-static int of_at91sam9x5_clk_smd_setup(struct device_node *np)
-{
-	struct clk *clk;
-	unsigned int num_parents;
-	const char *parent_names[SMD_SOURCE_MAX];
-	const char *name = np->name;
-	struct regmap *regmap;
-
-	num_parents = of_clk_get_parent_count(np);
-	if (num_parents == 0 || num_parents > SMD_SOURCE_MAX)
-		return -EINVAL;
-
-	of_clk_parent_fill(np, parent_names, num_parents);
-
-	of_property_read_string(np, "clock-output-names", &name);
-
-	regmap = syscon_node_to_regmap(of_get_parent(np));
-	if (IS_ERR(regmap))
-		return PTR_ERR(regmap);
-
-	clk = at91sam9x5_clk_register_smd(regmap, name, parent_names,
-					  num_parents);
-	if (IS_ERR(clk))
-		return PTR_ERR(clk);
-
-	return of_clk_add_provider(np, of_clk_src_simple_get, clk);
-}
-CLK_OF_DECLARE(at91sam9x5_clk_smd, "atmel,at91sam9x5-clk-smd",
-	       of_at91sam9x5_clk_smd_setup);
drivers/clk/at91/clk-system.c +1 -41

57 lines not on this page · raw message

drivers/clk/at91/clk-usb.c +3 -91

121 lines not on this page · raw message

drivers/clk/at91/clk-utmi.c +64 -40

163 lines not on this page · raw message

drivers/clk/at91/pmc.c +248 -0

259 lines not on this page · raw message

drivers/clk/at91/pmc.h +169 -0

131 lines not on this page · raw message

drivers/clk/at91/sama5d2.c new file +342 -0

342 lines not on this page · raw message

drivers/clk/at91/sama5d4.c new file +270 -0

270 lines not on this page · raw message

include/dt-bindings/clock/at91.h new file +38 -0
new file mode 100644
index 000000000..ed30da28d

Lines of this file are not shown. View the raw message.

include/linux/clk.h +7 -0
index 978a0a8a9..20498574f 100644

Lines of this file are not shown. View the raw message.

include/soc/at91/atmel-sfr.h new file +34 -0
new file mode 100644
index 000000000..482337af0

Lines of this file are not shown. View the raw message.

The rest of this diff is not shown. View the raw message.

Signature · 7 lines
2.12.0


_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox

Part of the diff is not shown here. View the raw message.

#5 lore raw
Quoted 10 lines · Sam Ravnborg

Hi Ladislav

Quoted 3 lines

Recent DTS update brought in switch to the new PMC clock bindings, however we do not support that yet. Revert this change until PMC clock bindings support is implemented.

I have now ported the clk code from the kernel so barebox have support for PMC bindings.
Can you give it a try and see if this works for you.

Quoted 5 lines

So far I have only tested this on at91sam9263ek - a DT enabled board. It builds for non-DT boards.

Patch needs a bit love before it is ready to submit. Could I get early feedback that would be great.

Updated patchset sent please try this is possible.

Thanks,
Sam

_______________________________________________
barebox mailing list
[email protected]
http://lists.infradead.org/mailman/listinfo/barebox