make mt7623 clock of hdmi stable
Subsystems (4)
v4 cover make mt7623 clock of hdmi stable
From: Wangyan Wang <wangyan.wang-NuS5LvNUpcJWk0Htik3J/[email protected]>
V4 adopt maintainer's suggestion.
Here is the change list between V3 & V4
1. add Reviewed-by:CK Hu <ck.hu-NuS5LvNUpcJWk0Htik3J/[email protected]> in commit message.
2. describe the reason why mt7623 clock of hdmi is more stable than before.
the tvdpll should be stable in hdmi normal setting to guarantee clock of hdmi stable, but the tvdpll may be changed in original code ,the patch is to deal with the problem, you can find more descriptions in patch "drm/mediatek:using different flags of clk ...".
chunhui dai (8):
drm/mediatek: recalculate hdmi phy clock of MT2701 by querying
hardware
drm/mediatek: move the setting of fixed divider drm/mediatek: using different flags of clk for HDMI phy drm/mediatek: fix the rate and divder of hdmi phy for MT2701
clk: mediatek: add MUX_GATE_FLAGS_2
clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel drm/mediatek: using new factor for tvdpll in MT2701 drm/mediatek: fix the rate of parent for hdmi phy in MT2701
drivers/clk/mediatek/clk-mt2701.c | 4 +- drivers/clk/mediatek/clk-mtk.c | 2 +- drivers/clk/mediatek/clk-mtk.h | 20 ++++++--- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 ++-- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 34 ++++------------ drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 7 +--- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 56 +++++++++++++++++++++++--- drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 23 +++++++++++ 8 files changed, 102 insertions(+), 52 deletions(-)
Signature · 1 line
2.14.1
A message that is not in the archive (sent off-list or not yet received): 20190219093115.16449-1-wangyan.wang-NuS5LvNUpcJWk0Htik3J/[email protected]
PATCH v4 1/8 drm/mediatek: recalculate hdmi phy clock of MT2701 by querying hardware
From: chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/[email protected]>
Recalculate the rate of this clock, by querying hardware.
--- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 7 ++---- drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 3 +-- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 35 ++++++++++++++++++++++++++ drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 8 ++++++ 4 files changed, 46 insertions(+), 7 deletions(-)
drivers/gpu/drm/mediatek/mtk_hdmi_phy.c +2 -5
@@ -29,12 +29,9 @@ long mtk_hdmi_pll_round_rate(struct clk_hw *hw, unsigned long rate,return rate; } -unsigned long mtk_hdmi_pll_recalc_rate (struct clk_hw *hw, -unsigned long parent_rate) +u32 mtk_hdmi_phy_read (struct mtk_hdmi_phy *hdmi_phy,u32 offset) { -struct mtk_hdmi_phy *hdmi_phy =to_mtk_hdmi_phy (hw); - -return hdmi_phy->pll_rate; +return readl (hdmi_phy->regs + offset); } void mtk_hdmi_phy_clear_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
drivers/gpu/drm/mediatek/mtk_hdmi_phy.h +1 -2
@@ -41,6 +41,7 @@ struct mtk_hdmi_phy {unsigned int ibias_up; }; +u32 mtk_hdmi_phy_read (struct mtk_hdmi_phy *hdmi_phy,u32 offset);void mtk_hdmi_phy_clear_bits (struct mtk_hdmi_phy *hdmi_phy,u32 offset,u32 bits); void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,
@@ -50,8 +51,6 @@ void mtk_hdmi_phy_mask(struct mtk_hdmi_phy *hdmi_phy, u32 offset,struct mtk_hdmi_phy *to_mtk_hdmi_phy (struct clk_hw *hw);long mtk_hdmi_pll_round_rate (struct clk_hw *hw,unsigned long rate,unsigned long *parent_rate); -unsigned long mtk_hdmi_pll_recalc_rate (struct clk_hw *hw, -unsigned long parent_rate);extern struct platform_driver mtk_hdmi_phy_driver;extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c +35 -0
@@ -153,6 +153,41 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, RG_HDMITX_DRV_IBIAS_MASK);return 0 ; } +static unsigned long mtk_hdmi_pll_recalc_rate (struct clk_hw *hw, +unsigned long parent_rate) +{ +struct mtk_hdmi_phy *hdmi_phy =to_mtk_hdmi_phy (hw); +unsigned long out_rate, val; + + val = (mtk_hdmi_phy_read (hdmi_phy,HDMI_CON6 ) + &RG_HTPLL_PREDIV_MASK ) >>RG_HTPLL_PREDIV ; +switch (val) { +case 0x00 : + out_rate = parent_rate; +break ; +case 0x01 : + out_rate = parent_rate /2 ; +break ; +default : + out_rate = parent_rate /4 ; +break ; + } + + val = (mtk_hdmi_phy_read (hdmi_phy,HDMI_CON6 ) + &RG_HTPLL_FBKDIV_MASK ) >>RG_HTPLL_FBKDIV ; + out_rate *= (val +1 ) *2 ; + val = (mtk_hdmi_phy_read (hdmi_phy,HDMI_CON2 ) + &RG_HDMITX_TX_POSDIV_MASK ); + + out_rate >>= (val >>RG_HDMITX_TX_POSDIV ); + +if (mtk_hdmi_phy_read (hdmi_phy,HDMI_CON2 ) &RG_HDMITX_EN_TX_POSDIV ) + out_rate = out_rate /5 ; + + hdmi_phy->pll_rate = out_rate; + +return hdmi_phy->pll_rate; +}static const struct clk_ops mtk_hdmi_phy_pll_ops = { .prepare = mtk_hdmi_pll_prepare,
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c +8 -0
@@ -285,6 +285,14 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,return 0 ; } +static unsigned long mtk_hdmi_pll_recalc_rate (struct clk_hw *hw, +unsigned long parent_rate) +{ +struct mtk_hdmi_phy *hdmi_phy =to_mtk_hdmi_phy (hw); + +return hdmi_phy->pll_rate; +} +static const struct clk_ops mtk_hdmi_phy_pll_ops = { .prepare = mtk_hdmi_pll_prepare, .unprepare = mtk_hdmi_pll_unprepare,
Signature · 1 line
2.14.1
PATCH v4 2/8 drm/mediatek: move the setting of fixed divider
In reply to a message not in the archiveFrom: chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/[email protected]>
move the setting of fixed divider from enable/disable to the function of setting rate.
the patch is for hdmi pll divider, the divder should be configured before clock calculation to ensure the clock is right.
--- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 5 +---- 1 file changed, 1 insertion(+), 4 deletions(-)
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c +1 -4
@@ -79,7 +79,6 @@ static int mtk_hdmi_pll_prepare(struct clk_hw *hw)mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_SLDO_MASK );usleep_range (80 ,100 );mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON2 ,RG_HDMITX_MBIAS_LPF_EN ); -mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON2 ,RG_HDMITX_EN_TX_POSDIV );mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_SER_MASK );mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_PRED_MASK );mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_DRV_MASK );
@@ -94,7 +93,6 @@ static void mtk_hdmi_pll_unprepare(struct clk_hw *hw)mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_DRV_MASK );mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_PRED_MASK );mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_SER_MASK ); -mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON2 ,RG_HDMITX_EN_TX_POSDIV );mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON2 ,RG_HDMITX_MBIAS_LPF_EN );usleep_range (80 ,100 );mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_SLDO_MASK );
@@ -123,6 +121,7 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON6 ,RG_HTPLL_PREDIV_MASK );mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON6 ,RG_HTPLL_POSDIV_MASK ); +mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON2 ,RG_HDMITX_EN_TX_POSDIV );mtk_hdmi_phy_mask (hdmi_phy,HDMI_CON6 , (0x1 <<RG_HTPLL_IC ),RG_HTPLL_IC_MASK ); mtk_hdmi_phy_mask(hdmi_phy, HDMI_CON6, (0x1 << RG_HTPLL_IR),
@@ -209,7 +208,6 @@ static void mtk_hdmi_phy_enable_tmds(struct mtk_hdmi_phy *hdmi_phy)mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_SLDO_MASK );usleep_range (80 ,100 );mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON2 ,RG_HDMITX_MBIAS_LPF_EN ); -mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON2 ,RG_HDMITX_EN_TX_POSDIV );mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_SER_MASK );mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_PRED_MASK );mtk_hdmi_phy_set_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_DRV_MASK );
@@ -221,7 +219,6 @@ static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_DRV_MASK );mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_PRED_MASK );mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_SER_MASK ); -mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON2 ,RG_HDMITX_EN_TX_POSDIV );mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON2 ,RG_HDMITX_MBIAS_LPF_EN );usleep_range (80 ,100 );mtk_hdmi_phy_clear_bits (hdmi_phy,HDMI_CON0 ,RG_HDMITX_EN_SLDO_MASK );
Signature · 1 line
2.14.1
PATCH v4 3/8 drm/mediatek: using different flags of clk for HDMI phy
In reply to a message not in the archiveFrom: chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/[email protected]>
The parent rate of hdmi phy had set by DPI driver.
We should not set or change the parent rate of MT2701 hdmi phy, as a result we should remove the flags of "CLK_SET_RATE_PARENT" from the clock of MT2701 hdmi phy.
--- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 13 +++++-------- drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 1 + drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 1 + drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 1 + 4 files changed, 8 insertions(+), 8 deletions(-)
drivers/gpu/drm/mediatek/mtk_hdmi_phy.c +5 -8
@@ -107,13 +107,11 @@ mtk_hdmi_phy_dev_get_ops(const struct mtk_hdmi_phy *hdmi_phy)return NULL ; } -static void mtk_hdmi_phy_clk_get_ops (struct mtk_hdmi_phy *hdmi_phy, -const struct clk_ops **ops) +static void mtk_hdmi_phy_clk_get_data (struct mtk_hdmi_phy *hdmi_phy, +struct clk_init_data *clk_init) { -if (hdmi_phy && hdmi_phy->conf && hdmi_phy->conf->hdmi_phy_clk_ops) - *ops = hdmi_phy->conf->hdmi_phy_clk_ops; -else -dev_err (hdmi_phy->dev,"Failed to get clk ops of phy\n" ); + clk_init->flags = hdmi_phy->conf->flags; + clk_init->ops = hdmi_phy->conf->hdmi_phy_clk_ops; }static int mtk_hdmi_phy_probe (struct platform_device *pdev)
@@ -126,7 +124,6 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev)struct clk_init_data clk_init = { .num_parents =1 , .parent_names = (const char *const *)&ref_clk_name, - .flags =CLK_SET_RATE_PARENT |CLK_SET_RATE_GATE , };struct phy *phy;
@@ -164,7 +161,7 @@ static int mtk_hdmi_phy_probe(struct platform_device *pdev) hdmi_phy->dev = dev; hdmi_phy->conf = (struct mtk_hdmi_phy_conf *)of_device_get_match_data (dev); -mtk_hdmi_phy_clk_get_ops (hdmi_phy, &clk_init.ops); +mtk_hdmi_phy_clk_get_data (hdmi_phy, &clk_init); hdmi_phy->pll_hw.init = &clk_init; hdmi_phy->pll =devm_clk_register (dev, &hdmi_phy->pll_hw);if (IS_ERR (hdmi_phy->pll)) {
drivers/gpu/drm/mediatek/mtk_hdmi_phy.h +1 -0
@@ -21,6 +21,7 @@ struct mtk_hdmi_phy;struct mtk_hdmi_phy_conf {bool tz_disabled; +unsigned long flags;const struct clk_ops *hdmi_phy_clk_ops;void (*hdmi_phy_enable_tmds)(struct mtk_hdmi_phy *hdmi_phy);void (*hdmi_phy_disable_tmds)(struct mtk_hdmi_phy *hdmi_phy);
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c +1 -0
@@ -234,6 +234,7 @@ static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy)struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf = { .tz_disabled = true, + .flags =CLK_SET_RATE_NO_REPARENT |CLK_SET_RATE_GATE , .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops, .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c +1 -0
@@ -317,6 +317,7 @@ static void mtk_hdmi_phy_disable_tmds(struct mtk_hdmi_phy *hdmi_phy) }struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf = { + .flags =CLK_SET_RATE_PARENT |CLK_SET_RATE_GATE , .hdmi_phy_clk_ops = &mtk_hdmi_phy_pll_ops, .hdmi_phy_enable_tmds = mtk_hdmi_phy_enable_tmds, .hdmi_phy_disable_tmds = mtk_hdmi_phy_disable_tmds,
Signature · 1 line
2.14.1
PATCH v4 4/8 drm/mediatek: fix the rate and divder of hdmi phy for MT2701
In reply to a message not in the archiveFrom: chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/[email protected]>
Due to a clerical error,there is one zero less for 12800000. Fix it for 128000000.
Fixes 0fc721b2968e ("drm/mediatek: add hdmi driver for MT2701 and MT7623")
--- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c +2 -2
@@ -114,8 +114,8 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,if (rate <=64000000 ) pos_div =3 ; -else if (rate <=12800000 ) - pos_div =1 ; +else if (rate <=128000000 ) + pos_div =2 ;else pos_div =1 ;
Signature · 1 line
2.14.1
PATCH v4 5/8 clk: mediatek: add MUX_GATE_FLAGS_2
In reply to a message not in the archiveFrom: chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/[email protected]>
Add MUX_GATE_FLAGS_2 for the clock which needs to set two falgs. Such as some mux need to set the flags of "CLK_MUX_ROUND_CLOSEST".
--- drivers/clk/mediatek/clk-mtk.c | 2 +- drivers/clk/mediatek/clk-mtk.h | 20 ++++++++++++++------ 2 files changed, 15 insertions(+), 7 deletions(-)
drivers/clk/mediatek/clk-mtk.c +1 -1
@@ -167,7 +167,7 @@ struct clk *mtk_clk_register_composite(const struct mtk_composite *mc, mux->mask =BIT (mc->mux_width) -1 ; mux->shift = mc->mux_shift; mux->lock = lock; - + mux->flags = mc->mux_flags; mux_hw = &mux->hw; mux_ops = &clk_mux_ops;
drivers/clk/mediatek/clk-mtk.h +14 -6
@@ -81,15 +81,13 @@ struct mtk_composite {signed char divider_shift;signed char divider_width; +unsigned char mux_flags; +signed char num_parents; }; -/* -* In case the rate change propagation to parent clocks is undesirable, -* this macro allows to specify the clock flags manually. -*/ -#define MUX_GATE_FLAGS (_id, _name, _parents, _reg, _shift, _width, \ - _gate, _flags) { \ +#define MUX_GATE_FLAGS_2 (_id, _name, _parents, _reg, _shift, \ + _width, _gate, _flags, _muxflags) { \ .id = _id, \ .name = _name, \ .mux_reg = _reg, \
@@ -101,8 +99,18 @@ struct mtk_composite { .parent_names = _parents, \ .num_parents = ARRAY_SIZE(_parents), \ .flags = _flags, \ + .mux_flags = _muxflags, \ } +/* +* In case the rate change propagation to parent clocks is undesirable, +* this macro allows to specify the clock flags manually. +*/ +#define MUX_GATE_FLAGS (_id, _name, _parents, _reg, _shift, _width, \ + _gate, _flags) \ + MUX_GATE_FLAGS_2(_id, _name, _parents, _reg, \ + _shift, _width, _gate, _flags, 0) +/* * Unless necessary, all MUX_GATE clocks propagate rate changes to their * parent clock by default.
Signature · 1 line
2.14.1
PATCH v4 6/8 clk: mediatek: using CLK_MUX_ROUND_CLOSEST for the clock of dpi1_sel
In reply to a message not in the archiveFrom: chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/[email protected]>
The MUX clock of dpi1_sel should select the closet clock for itself. We could add this flag to enable this function of MUX in CCF.
--- drivers/clk/mediatek/clk-mt2701.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/clk/mediatek/clk-mt2701.c +2 -2
@@ -535,8 +535,8 @@ static const struct mtk_composite top_muxes[] = { 0x0080, 8, 2, 15),MUX_GATE (CLK_TOP_DPI0_SEL ,"dpi0_sel" , dpi0_parents,0x0080 ,16 ,3 ,23 ), -MUX_GATE (CLK_TOP_DPI1_SEL ,"dpi1_sel" , dpi1_parents, -0x0080 ,24 ,2 ,31 ), +MUX_GATE_FLAGS_2 (CLK_TOP_DPI1_SEL ,"dpi1_sel" , dpi1_parents, +0x0080 ,24 ,2 ,31 ,0 ,CLK_MUX_ROUND_CLOSEST ),MUX_GATE (CLK_TOP_TVE_SEL ,"tve_sel" , tve_parents, 0x0090, 0, 3, 7),
Signature · 1 line
2.14.1
PATCH v4 7/8 drm/mediatek: using new factor for tvdpll in MT2701
In reply to a message not in the archiveFrom: chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/[email protected]>
The factor depends on the divider of DPI in MT2701, therefore, we should fix this factor to the right and new one.
--- drivers/gpu/drm/mediatek/mtk_dpi.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)
drivers/gpu/drm/mediatek/mtk_dpi.c +3 -5
@@ -662,13 +662,11 @@ static unsigned int mt8173_calculate_factor(int clock)static unsigned int mt2701_calculate_factor (int clock) {if (clock <=64000 ) -return 16 ; -else if (clock <=128000 ) -return 8 ; -else if (clock <=256000 )return 4 ; -else +else if (clock <=128000 )return 2 ; +else +return 1 ; }static const struct mtk_dpi_conf mt8173_conf = {
Signature · 1 line
2.14.1
PATCH v4 8/8 drm/mediatek: fix the rate of parent for hdmi phy in MT2701
In reply to a message not in the archiveFrom: chunhui dai <chunhui.dai-NuS5LvNUpcJWk0Htik3J/[email protected]>
We should not change the rate of parent for hdmi phy when doing round_rate for this clock. The parent clock of hdmi phy must be the same as it. We change it when doing set_rate only.
--- drivers/gpu/drm/mediatek/mtk_hdmi_phy.c | 14 -------------- drivers/gpu/drm/mediatek/mtk_hdmi_phy.h | 3 --- drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c | 11 +++++++++++ drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c | 14 ++++++++++++++ 4 files changed, 25 insertions(+), 17 deletions(-)
drivers/gpu/drm/mediatek/mtk_hdmi_phy.c +0 -14
@@ -15,20 +15,6 @@ static const struct phy_ops mtk_hdmi_phy_dev_ops = { .owner = THIS_MODULE, }; -long mtk_hdmi_pll_round_rate (struct clk_hw *hw,unsigned long rate, -unsigned long *parent_rate) -{ -struct mtk_hdmi_phy *hdmi_phy =to_mtk_hdmi_phy (hw); - - hdmi_phy->pll_rate = rate; -if (rate <=74250000 ) - *parent_rate = rate; -else - *parent_rate = rate /2 ; - -return rate; -} -u32 mtk_hdmi_phy_read (struct mtk_hdmi_phy *hdmi_phy,u32 offset) {return readl (hdmi_phy->regs + offset);
drivers/gpu/drm/mediatek/mtk_hdmi_phy.h +0 -3
@@ -50,9 +50,6 @@ void mtk_hdmi_phy_set_bits(struct mtk_hdmi_phy *hdmi_phy, u32 offset,void mtk_hdmi_phy_mask (struct mtk_hdmi_phy *hdmi_phy,u32 offset,u32 val,u32 mask);struct mtk_hdmi_phy *to_mtk_hdmi_phy (struct clk_hw *hw); -long mtk_hdmi_pll_round_rate (struct clk_hw *hw,unsigned long rate, -unsigned long *parent_rate); -extern struct platform_driver mtk_hdmi_phy_driver;extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_8173_conf;extern struct mtk_hdmi_phy_conf mtk_hdmi_phy_2701_conf;
drivers/gpu/drm/mediatek/mtk_mt2701_hdmi_phy.c +11 -0
@@ -152,6 +152,17 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate, RG_HDMITX_DRV_IBIAS_MASK);return 0 ; } + +static long mtk_hdmi_pll_round_rate (struct clk_hw *hw,unsigned long rate, +unsigned long *parent_rate) +{ +struct mtk_hdmi_phy *hdmi_phy =to_mtk_hdmi_phy (hw); + + hdmi_phy->pll_rate = rate; + +return rate; +} +static unsigned long mtk_hdmi_pll_recalc_rate (struct clk_hw *hw,unsigned long parent_rate) {
drivers/gpu/drm/mediatek/mtk_mt8173_hdmi_phy.c +14 -0
@@ -285,6 +285,20 @@ static int mtk_hdmi_pll_set_rate(struct clk_hw *hw, unsigned long rate,return 0 ; } +static long mtk_hdmi_pll_round_rate (struct clk_hw *hw,unsigned long rate, +unsigned long *parent_rate) +{ +struct mtk_hdmi_phy *hdmi_phy =to_mtk_hdmi_phy (hw); + + hdmi_phy->pll_rate = rate; +if (rate <=74250000 ) + *parent_rate = rate; +else + *parent_rate = rate /2 ; + +return rate; +} +static unsigned long mtk_hdmi_pll_recalc_rate (struct clk_hw *hw,unsigned long parent_rate) {
Signature · 1 line
2.14.1