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mtd: spi-nor: cadence-quadspi: add reset control

PATCH In review Dinh Nguyen 2 participants 3 messages Apr 9, 2019 – May 7, 2019

Subsystems (2)
Memory technology devices (MTD) SPI NOR
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Dinh Nguyen

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#0 lore raw

PATCH v2 1/1 mtd: spi-nor: cadence-quadspi: add reset control

Get the reset control for the QSPI controller and bring it out of reset.

Suggested-by Tien-Fong Chee <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>

---
v2: use devm_reset_control_get_optional_exclusive
print an error message
return -EPROBE_DEFER

---
 drivers/mtd/spi-nor/cadence-quadspi.c | 14 ++++++++++++++
 1 file changed, 14 insertions(+)
drivers/mtd/spi-nor/cadence-quadspi.c +14 -0
index 792628750eec..c548567adcf0 100644
@@ -34,6 +34,7 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/sched.h>
 #include <linux/spi/spi.h>
 #include <linux/timer.h>

@@ -1336,6 +1337,7 @@ static int cqspi_probe(struct platform_device *pdev)
 	struct cqspi_st *cqspi;
 	struct resource *res;
 	struct resource *res_ahb;
+	struct reset_control *rstc;
 	const struct cqspi_driver_platdata *ddata;
 	int ret;
 	int irq;

@@ -1362,6 +1364,18 @@ static int cqspi_probe(struct platform_device *pdev)
 		return PTR_ERR(cqspi->clk);
 	}
 
+	/* Obtain QSPI reset control */
+	rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
+	if (IS_ERR(rstc)) {
+		dev_err(dev, "Cannot get QSPI reset.\n");
+		if (PTR_ERR(rstc) == -EPROBE_DEFER)
+			return -EPROBE_DEFER;
+	} else {
+		reset_control_assert(rstc);
+		udelay(1);
+		reset_control_deassert(rstc);
+	}
+
 	/* Obtain and remap controller address. */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	cqspi->iobase = devm_ioremap_resource(dev, res);
Signature · 1 line
2.20.0
#1 lore raw

Hi, Dinh,

Quoted 1 line · Dinh Nguyen

Get the reset control for the QSPI controller and bring it out of reset.

Is there a public datasheet where I can check this?

Quoted 9 lines
Suggested-by Tien-Fong Chee <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>

---
v2: use devm_reset_control_get_optional_exclusive
print an error message
return -EPROBE_DEFER

---
 drivers/mtd/spi-nor/cadence-quadspi.c | 14 ++++++++++++++

would you update the bindings as well?

Quoted 23 lines
 1 file changed, 14 insertions(+)
drivers/mtd/spi-nor/cadence-quadspi.c +2 -0
index 792628750eec..c548567adcf0 100644
@@ -34,6 +34,7 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/sched.h>
 #include <linux/spi/spi.h>
 #include <linux/timer.h>

@@ -1336,6 +1337,7 @@ static int cqspi_probe(struct platform_device *pdev)
 	struct cqspi_st *cqspi;
 	struct resource *res;
 	struct resource *res_ahb;
+	struct reset_control *rstc;
 	const struct cqspi_driver_platdata *ddata;
 	int ret;
 	int irq;

drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1367

Quoted 4 lines
drivers/mtd/spi-nor/cadence-quadspi.c +1 -0
@@ -1362,6 +1364,18 @@ static int cqspi_probe(struct platform_device *pdev)
 		return PTR_ERR(cqspi->clk);
 	}
 
+	/* Obtain QSPI reset control */

OSPI version of the IP has been added recently. Is this available just for QSPI?

drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1372

Quoted 5 lines
drivers/mtd/spi-nor/cadence-quadspi.c +5 -0
+	rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
+	if (IS_ERR(rstc)) {
+		dev_err(dev, "Cannot get QSPI reset.\n");
+		if (PTR_ERR(rstc) == -EPROBE_DEFER)
+			return -EPROBE_DEFER;

why ignoring all the other possible errors? Maybe return PTR_ERR(rstc); ?

drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1374

Quoted 2 lines
drivers/mtd/spi-nor/cadence-quadspi.c +2 -0
+	} else {
+		reset_control_assert(rstc);

Shouldn't the clock be enabled before asserting reset?

Does it matter if reset_control_assert() is returning any error?

drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1375

Quoted 1 line
drivers/mtd/spi-nor/cadence-quadspi.c +1 -0
+		udelay(1);

Is there a range or 1 us is the maximum time that we should wait?

drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1376

Quoted 1 line
drivers/mtd/spi-nor/cadence-quadspi.c +1 -0
+		reset_control_deassert(rstc);

Should we check if reset_control_deassert() is returning any error?

Cheers,
ta

Quoted 6 lines
drivers/mtd/spi-nor/cadence-quadspi.c +2 -0
+	}
+
 	/* Obtain and remap controller address. */
 	res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
 	cqspi->iobase = devm_ioremap_resource(dev, res);
author
#2 lore raw
Quoted 6 lines · On 4/17/19 3:48 AM, [email protected] wrote:

Hi, Dinh,

Quoted 1 line · Dinh Nguyen

Get the reset control for the QSPI controller and bring it out of reset.

Is there a public datasheet where I can check this?

You can look at the reset manager bits here:

https://www.intel.com/content/www/us/en/programmable/hps/arria-10/hps.html#reg_soc_top/sfo1429890575955.html

Otherwise, the QSPI block is just the standard IP from Cadence.

Quoted 11 lines
Quoted 9 lines
Suggested-by Tien-Fong Chee <[email protected]>
Signed-off-by Dinh Nguyen <[email protected]>

---
v2: use devm_reset_control_get_optional_exclusive
print an error message
return -EPROBE_DEFER

---
 drivers/mtd/spi-nor/cadence-quadspi.c | 14 ++++++++++++++

would you update the bindings as well?

Yes, I will do that.

Quoted 31 lines
Quoted 24 lines
 1 file changed, 14 insertions(+)
drivers/mtd/spi-nor/cadence-quadspi.c +2 -0
index 792628750eec..c548567adcf0 100644
@@ -34,6 +34,7 @@
 #include <linux/of.h>
 #include <linux/platform_device.h>
 #include <linux/pm_runtime.h>
+#include <linux/reset.h>
 #include <linux/sched.h>
 #include <linux/spi/spi.h>
 #include <linux/timer.h>

@@ -1336,6 +1337,7 @@ static int cqspi_probe(struct platform_device *pdev)
 	struct cqspi_st *cqspi;
 	struct resource *res;
 	struct resource *res_ahb;
+	struct reset_control *rstc;
 	const struct cqspi_driver_platdata *ddata;
 	int ret;
 	int irq;

drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1367

Quoted 4 lines
drivers/mtd/spi-nor/cadence-quadspi.c +1 -0
@@ -1362,6 +1364,18 @@ static int cqspi_probe(struct platform_device *pdev)
 		return PTR_ERR(cqspi->clk);
 	}
 
+	/* Obtain QSPI reset control */

OSPI version of the IP has been added recently. Is this available just for QSPI?

Quoted 7 lines

drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1372

Quoted 5 lines
drivers/mtd/spi-nor/cadence-quadspi.c +5 -0
+	rstc = devm_reset_control_get_optional_exclusive(dev, NULL);
+	if (IS_ERR(rstc)) {
+		dev_err(dev, "Cannot get QSPI reset.\n");
+		if (PTR_ERR(rstc) == -EPROBE_DEFER)
+			return -EPROBE_DEFER;

why ignoring all the other possible errors? Maybe return PTR_ERR(rstc); ?

Ok..

Quoted 6 lines

drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1374

Quoted 3 lines
drivers/mtd/spi-nor/cadence-quadspi.c +2 -0
+	} else {
+		reset_control_assert(rstc);

Shouldn't the clock be enabled before asserting reset?

Yes, it should. Thanks for catching that!

Quoted 7 lines

Does it matter if reset_control_assert() is returning any error?

drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1375

Quoted 1 line
drivers/mtd/spi-nor/cadence-quadspi.c +1 -0
+		udelay(1);

Is there a range or 1 us is the maximum time that we should wait?

drivers/mtd/spi-nor/cadence-quadspi.c static int cqspi_probe(struct platform_device *pdev) · line 1376

Quoted 1 line
drivers/mtd/spi-nor/cadence-quadspi.c +1 -0
+		reset_control_deassert(rstc);

I'll add a 1-2 us range.

Quoted 3 lines

Should we check if reset_control_deassert() is returning any error?

I don't think there is a need for error checking here. We've already made sure that the reset property is there.

Thanks for the review...

Dinh