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x86: Wait for self IPI

PATCH In review [email protected] 2 participants 3 messages Apr 15, 2019 – Apr 16, 2019 KVM

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#0 lore raw

PATCH 1/1 x86: Wait for self IPI

From: Nadav Amit <[email protected]>

There is no architectural requirement that self-IPI would be received on the next instruction after it is generated. Make the test more robust by not requiring it, and instead wait for some time or until it is received.

Signed-off-by Nadav Amit <[email protected]>
---
 x86/apic.c | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)
x86/apic.c +6 -1
index 0849f87..de5990c 100644
@@ -255,13 +255,18 @@ static void self_ipi_isr(isr_regs_t *regs)
 
 static void test_self_ipi(void)
 {
+    u64 start = rdtsc();
     int vec = 0xf1;
 
     handle_irq(vec, self_ipi_isr);
     irq_enable();
     apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | vec,
                    0);
-    asm volatile ("nop");
+
+    do {
+        pause();
+    } while (rdtsc() - start < 1000000000 && ipi_count == 0);
+
     report("self ipi", ipi_count == 1);
 }
Signature · 1 line
2.17.1
author
#1 lore raw
Quoted 40 lines · On Apr 15, 2019, at 4:03 PM, [email protected] wrote:

From: Nadav Amit <[email protected]>

There is no architectural requirement that self-IPI would be received on the next instruction after it is generated. Make the test more robust by not requiring it, and instead wait for some time or until it is received.

Signed-off-by Nadav Amit <[email protected]>

---
x86/apic.c | 7 ++++++-

1 file changed, 6 insertions(+), 1 deletion(-)
x86/apic.c +6 -1
index 0849f87..de5990c 100644
@@ -255,13 +255,18 @@ static void self_ipi_isr(isr_regs_t *regs)
 
 static void test_self_ipi(void)
 {
+    u64 start = rdtsc();
    int vec = 0xf1;
 
    handle_irq(vec, self_ipi_isr);
    irq_enable();
    apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | vec,
                   0);
-    asm volatile ("nop");
+
+    do {
+        pause();
+    } while (rdtsc() - start < 1000000000 && ipi_count == 0);
+
    report("self ipi", ipi_count == 1);
 }
Signature · 1 line
2.17.1

This is of course a KVM-unit-tests patch.

maintainer
#2 lore raw
Quoted 38 lines · Nadav Amit
Quoted 38 lines · On Apr 15, 2019, at 4:03 PM, [email protected] wrote:

From: Nadav Amit <[email protected]>

There is no architectural requirement that self-IPI would be received on the next instruction after it is generated. Make the test more robust by not requiring it, and instead wait for some time or until it is received.

Signed-off-by Nadav Amit <[email protected]>

---
x86/apic.c | 7 ++++++-

1 file changed, 6 insertions(+), 1 deletion(-)
x86/apic.c +6 -1
index 0849f87..de5990c 100644
@@ -255,13 +255,18 @@ static void self_ipi_isr(isr_regs_t *regs)
 
 static void test_self_ipi(void)
 {
+    u64 start = rdtsc();
    int vec = 0xf1;
 
    handle_irq(vec, self_ipi_isr);
    irq_enable();
    apic_icr_write(APIC_DEST_SELF | APIC_DEST_PHYSICAL | APIC_DM_FIXED | vec,
                   0);
-    asm volatile ("nop");
+
+    do {
+        pause();
+    } while (rdtsc() - start < 1000000000 && ipi_count == 0);
+
    report("self ipi", ipi_count == 1);
 }
Quoted 5 lines
Quoted 2 lines
Signature · 1 line
2.17.1

This is of course a KVM-unit-tests patch.

which I've queued, thanks.

Paolo