arm64: dts: rockchip: Add missing PCIe pwr amd rst configuration

PATCH Superseded Anand Moon 2 participants 4 messages May 30, 2019 – May 31, 2019

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Anand Moon

author

2019-05-30 12:58 UTC #0 lore raw

PATCH 1/1 arm64: dts: rockchip: Add missing PCIe pwr amd rst configuration

This patch add missing PCIe gpio and pinctrl for power (#PCIE_PWR) also add PCIe gpio and pinctrl for reset (#PCIE_PERST_L).

Signed-off-by Anand Moon <[email protected]>

---
Tested on Rock960 Model A

---
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +14 -2

index c7d48d41e184..f5bef6b0fe89 100644
@@ -55,9 +55,10 @@
 
 	vcc3v3_pcie: vcc3v3-pcie-regulator {
 		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		pinctrl-names = "default";
-		pinctrl-0 = <&pcie_drv>;
+		pinctrl-0 = <&pcie_drv &pcie_pwr>;
 		regulator-boot-on;
 		regulator-name = "vcc3v3_pcie";
 		regulator-min-microvolt = <3300000>;

@@ -381,9 +382,10 @@
 };
 
 &pcie0 {
+	ep-gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
 	num-lanes = <4>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_clkreqn_cpm>;
+	pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
 };

@@ -408,6 +410,16 @@
 		};
 	};
 
+	pcie {
+		pcie_pwr: pcie-pwr {
+			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_perst_l:pcie-perst-l {
+			rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+	};
+
 	sdmmc {
 		sdmmc_bus1: sdmmc-bus1 {
 			rockchip,pins =

Signature · 1 line

2.21.0

Manivannan Sadhasivam

2019-05-31 04:02 UTC #1 lore raw

Hi,

Quoted 40 lines · Anand Moon

This patch add missing PCIe gpio and pinctrl for power (#PCIE_PWR) also add PCIe gpio and pinctrl for reset (#PCIE_PERST_L).

Signed-off-by Anand Moon <[email protected]>

---
Tested on Rock960 Model A

---
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +4 -2

index c7d48d41e184..f5bef6b0fe89 100644
@@ -55,9 +55,10 @@
 
 	vcc3v3_pcie: vcc3v3-pcie-regulator {
 		compatible = "regulator-fixed";
+		gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
 		enable-active-high;
 		pinctrl-names = "default";
-		pinctrl-0 = <&pcie_drv>;
+		pinctrl-0 = <&pcie_drv &pcie_pwr>;
 		regulator-boot-on;
 		regulator-name = "vcc3v3_pcie";
 		regulator-min-microvolt = <3300000>;

@@ -381,9 +382,10 @@
 };
 
 &pcie0 {
+	ep-gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
 	num-lanes = <4>;
 	pinctrl-names = "default";
-	pinctrl-0 = <&pcie_clkreqn_cpm>;
+	pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>;
 	vpcie3v3-supply = <&vcc3v3_pcie>;
 	status = "okay";
 };

@@ -408,6 +410,16 @@
 		};

arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi line 420

Quoted 10 lines

arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +8 -0

 	};
 
+	pcie {
+		pcie_pwr: pcie-pwr {
+			rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+		};
+
+		pcie_perst_l:pcie-perst-l {
+			rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+		};

Which schematics did you refer? According to Rock960 v2.1 schematics [1], below is the pin mapping for PCI-E PWR and PERST:

PCIE_PERST - GPIO2_A2
PCIE_PWR - GPIO2_A5

Above mapping holds true for Rock960 version 1.1, 1.2 and 1.3. Also, rk3399-rock960.dtsi is common for both Rock960 and Ficus boards, so the board specific parts should go to rk3399-rock960.dts and rk3399-ficus.dts.

Thanks,
Mani

[1] https://dl.vamrs.com/products/rock960/docs/hw/rock960_sch_v12_20180314.pdf

Quoted 8 lines

arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +2 -0
+	};
+
 	sdmmc {
 		sdmmc_bus1: sdmmc-bus1 {
 			rockchip,pins =
Signature · 1 line
2.21.0

Anand Moon

author

2019-05-31 04:57 UTC #2 lore raw

Hi Manivannan,

Quoted 58 lines · Manivannan Sadhasivam

Hi,

Quoted 40 lines · Anand Moon

This patch add missing PCIe gpio and pinctrl for power (#PCIE_PWR) also add PCIe gpio and pinctrl for reset (#PCIE_PERST_L).

Signed-off-by Anand Moon <[email protected]>

---
Tested on Rock960 Model A

---
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +4 -2

index c7d48d41e184..f5bef6b0fe89 100644
@@ -55,9 +55,10 @@
 
      vcc3v3_pcie: vcc3v3-pcie-regulator {
              compatible = "regulator-fixed";
+             gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
              enable-active-high;
              pinctrl-names = "default";
-             pinctrl-0 = <&pcie_drv>;
+             pinctrl-0 = <&pcie_drv &pcie_pwr>;
              regulator-boot-on;
              regulator-name = "vcc3v3_pcie";
              regulator-min-microvolt = <3300000>;

@@ -381,9 +382,10 @@
 };
 
 &pcie0 {
+     ep-gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
      num-lanes = <4>;
      pinctrl-names = "default";
-     pinctrl-0 = <&pcie_clkreqn_cpm>;
+     pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>;
      vpcie3v3-supply = <&vcc3v3_pcie>;
      status = "okay";
 };

@@ -408,6 +410,16 @@
              };

arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi line 420

Quoted 10 lines

arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +8 -0

      };
 
+     pcie {
+             pcie_pwr: pcie-pwr {
+                     rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+             };
+
+             pcie_perst_l:pcie-perst-l {
+                     rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+             };

Which schematics did you refer? According to Rock960 v2.1 schematics [1], below is the pin mapping for PCI-E PWR and PERST:

Quoted 3 lines

PCIE_PERST - GPIO2_A2
PCIE_PWR - GPIO2_A5

Opps, I have referred the wrong schematics *RK3399_Rock960_V1.0.pdf* may be old version.
Thanks for pointing out the correct schematics.

Quoted 6 lines

Above mapping holds true for Rock960 version 1.1, 1.2 and 1.3. Also, rk3399-rock960.dtsi is common for both Rock960 and Ficus boards, so the board specific parts should go to rk3399-rock960.dts and rk3399-ficus.dts.
Thanks,
Mani

I have ROCK960-V 1.2 (Model A) for testing so. I will be sending patch v2 the relevant
node update in rk3399-rock960.dts and rk3399-ficus.dts if below common for both the boards.

PCIE_PERST - GPIO2_A2
PCIE_PWR - GPIO2_A5

Quoted 2 lines

[1] https://dl.vamrs.com/products/rock960/docs/hw/rock960_sch_v12_20180314.pdf

Best Regards
-Anand

Manivannan Sadhasivam

2019-05-31 06:08 UTC #3 lore raw

Quoted 74 lines · Anand Moon

Hi Manivannan,
Quoted 58 lines · Manivannan Sadhasivam
Hi,
Quoted 40 lines · Anand Moon
This patch add missing PCIe gpio and pinctrl for power (#PCIE_PWR) also add PCIe gpio and pinctrl for reset (#PCIE_PERST_L).
Signed-off-by Anand Moon <[email protected]>
---
Tested on Rock960 Model A
---
 arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi | 16 ++++++++++++++--
 1 file changed, 14 insertions(+), 2 deletions(-)
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +4 -2
index c7d48d41e184..f5bef6b0fe89 100644
@@ -55,9 +55,10 @@
 
      vcc3v3_pcie: vcc3v3-pcie-regulator {
              compatible = "regulator-fixed";
+             gpio = <&gpio2 RK_PA2 GPIO_ACTIVE_HIGH>;
              enable-active-high;
              pinctrl-names = "default";
-             pinctrl-0 = <&pcie_drv>;
+             pinctrl-0 = <&pcie_drv &pcie_pwr>;
              regulator-boot-on;
              regulator-name = "vcc3v3_pcie";
              regulator-min-microvolt = <3300000>;
@@ -381,9 +382,10 @@
 };
 
 &pcie0 {
+     ep-gpio = <&gpio2 RK_PD4 GPIO_ACTIVE_HIGH>;
      num-lanes = <4>;
      pinctrl-names = "default";
-     pinctrl-0 = <&pcie_clkreqn_cpm>;
+     pinctrl-0 = <&pcie_clkreqn_cpm &pcie_perst_l>;
      vpcie3v3-supply = <&vcc3v3_pcie>;
      status = "okay";
 };
@@ -408,6 +410,16 @@
              };
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi line 420
Quoted 10 lines
arch/arm64/boot/dts/rockchip/rk3399-rock960.dtsi +8 -0
      };
 
+     pcie {
+             pcie_pwr: pcie-pwr {
+                     rockchip,pins = <2 RK_PA2 RK_FUNC_GPIO &pcfg_pull_none>;
+             };
+
+             pcie_perst_l:pcie-perst-l {
+                     rockchip,pins = <2 RK_PD4 RK_FUNC_GPIO &pcfg_pull_none>;
+             };
Which schematics did you refer? According to Rock960 v2.1 schematics [1], below is the pin mapping for PCI-E PWR and PERST:
Quoted 3 lines
PCIE_PERST - GPIO2_A2
PCIE_PWR - GPIO2_A5
Opps, I have referred the wrong schematics *RK3399_Rock960_V1.0.pdf* may be old version.
Thanks for pointing out the correct schematics.
Quoted 4 lines
Above mapping holds true for Rock960 version 1.1, 1.2 and 1.3. Also, rk3399-rock960.dtsi is common for both Rock960 and Ficus boards, so the board specific parts should go to rk3399-rock960.dts and rk3399-ficus.dts.

Quoted 7 lines

Quoted 2 lines
Thanks,
Mani
I have ROCK960-V 1.2 (Model A) for testing so. I will be sending patch v2 the relevant
node update in rk3399-rock960.dts and rk3399-ficus.dts if below common for both the boards.

Both boards are different in terms of pin mapping!

-Mani

Quoted 9 lines

PCIE_PERST - GPIO2_A2
PCIE_PWR - GPIO2_A5
Quoted 2 lines
[1] https://dl.vamrs.com/products/rock960/docs/hw/rock960_sch_v12_20180314.pdf
Best Regards
-Anand