mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning
PATCH v2 1/3 mmc: sdhci: sdhci-pci-o2micro: Correctly set bus width when tuning
The O2Micro controller only supports tuning at 4-bits. So the host driver needs to change the bus width while tuning and then set it back when done.
There was a bug in the original implementation in that mmc->ios.bus_width also wasn't updated. Thus setting the incorrect blocksize in sdhci_send_tuning which results in a tuning failure.
---
drivers/mmc/host/sdhci-pci-o2micro.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
drivers/mmc/host/sdhci-pci-o2micro.c +4 -1
@@ -115,6 +115,7 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)*/ if (mmc->ios.bus_width ==MMC_BUS_WIDTH_8 ) { current_bus_width = mmc->ios.bus_width; + mmc->ios.bus_width =MMC_BUS_WIDTH_4 ;sdhci_set_bus_width (host,MMC_BUS_WIDTH_4 ); }
@@ -126,8 +127,10 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)sdhci_end_tuning (host); -if (current_bus_width ==MMC_BUS_WIDTH_8 ) +if (current_bus_width ==MMC_BUS_WIDTH_8 ) { + mmc->ios.bus_width =MMC_BUS_WIDTH_8 ;sdhci_set_bus_width (host, current_bus_width); + } host->flags &= ~SDHCI_HS400_TUNING ;return 0 ;
Signature · 1 line
2.22.0.410.gd8fdbe21b5-goog
PATCH v2 2/3 mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width
The O2 controller supports 8-bit EMMC access.
JESD84-B51 section A.6.3.a defines the bus testing procedure that mmc_select_bus_width() implements. This is used to determine the actual bus width of the eMMC.
---
I tested this on an AMD chromebook.
$ cat /sys/kernel/debug/mmc1/ios clock: 200000000 Hz actual clock: 200000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 9 (mmc HS200) signal voltage: 1 (1.80 V) driver type: 0 (driver type B)
Before this patch only 4 bit was negotiated.
drivers/mmc/host/sdhci-pci-o2micro.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)
drivers/mmc/host/sdhci-pci-o2micro.c +11 -1
@@ -395,11 +395,21 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) {struct sdhci_pci_chip *chip;struct sdhci_host *host; -u32 reg; +u32 reg, caps;int ret; chip = slot->chip; host = slot->host; + + caps =sdhci_readl (host,SDHCI_CAPABILITIES ); + +/* +* mmc_select_bus_width() will test the bus to determine the actual bus +* width. +*/ +if (caps &SDHCI_CAN_DO_8BIT ) + host->mmc->caps |=MMC_CAP_8_BIT_DATA ; +switch (chip->pdev->device) {case PCI_DEVICE_ID_O2_SDS0 :case PCI_DEVICE_ID_O2_SEABIRD0 :
Signature · 1 line
2.22.0.410.gd8fdbe21b5-goog
Re: [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width
Quoted 7 lines · Raul E Rangel
The O2 controller supports 8-bit EMMC access.
JESD84-B51 section A.6.3.a defines the bus testing procedure that
mmc_select_bus_width()implements. This is used to determine the actual bus width of the eMMC.Signed-off-by Raul E Rangel <[email protected]>
Quoted 48 lines
---
I tested this on an AMD chromebook.$ cat /sys/kernel/debug/mmc1/ios clock: 200000000 Hz actual clock: 200000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 9 (mmc HS200) signal voltage: 1 (1.80 V) driver type: 0 (driver type B)Before this patch only 4 bit was negotiated.
drivers/mmc/host/sdhci-pci-o2micro.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)drivers/mmc/host/sdhci-pci-o2micro.c +11
-1@@ -395,11 +395,21 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) {struct sdhci_pci_chip *chip;struct sdhci_host *host; -u32 reg; +u32 reg, caps;int ret; chip = slot->chip; host = slot->host; + + caps =sdhci_readl (host,SDHCI_CAPABILITIES ); + +/* +* mmc_select_bus_width() will test the bus to determine the actual bus +* width. +*/ +if (caps &SDHCI_CAN_DO_8BIT ) + host->mmc->caps |=MMC_CAP_8_BIT_DATA ; +switch (chip->pdev->device) {case PCI_DEVICE_ID_O2_SDS0 :case PCI_DEVICE_ID_O2_SEABIRD0 :
Re: [PATCH v2 2/3] mmc: sdhci: sdhci-pci-o2micro: Check if controller supports 8-bit width
In reply to Raul E RangelQuoted 8 lines · Raul E Rangel
The O2 controller supports 8-bit EMMC access.
JESD84-B51 section A.6.3.a defines the bus testing procedure that
mmc_select_bus_width()implements. This is used to determine the actual bus width of the eMMC.Signed-off-by Raul E Rangel <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
Quoted 50 lines
---
I tested this on an AMD chromebook.$ cat /sys/kernel/debug/mmc1/ios clock: 200000000 Hz actual clock: 200000000 Hz vdd: 21 (3.3 ~ 3.4 V) bus mode: 2 (push-pull) chip select: 0 (don't care) power mode: 2 (on) bus width: 3 (8 bits) timing spec: 9 (mmc HS200) signal voltage: 1 (1.80 V) driver type: 0 (driver type B)Before this patch only 4 bit was negotiated.
drivers/mmc/host/sdhci-pci-o2micro.c | 12 +++++++++++- 1 file changed, 11 insertions(+), 1 deletion(-)drivers/mmc/host/sdhci-pci-o2micro.c +11
-2@@ -395,11 +395,21 @@ int sdhci_pci_o2_probe_slot(struct sdhci_pci_slot *slot) {struct sdhci_pci_chip *chip;struct sdhci_host *host; -u32 reg; +u32 reg, caps;int ret; chip = slot->chip; host = slot->host; + + caps =sdhci_readl (host,SDHCI_CAPABILITIES ); + +/* +* mmc_select_bus_width() will test the bus to determine the actual bus +* width. +*/ +if (caps &SDHCI_CAN_DO_8BIT ) + host->mmc->caps |=MMC_CAP_8_BIT_DATA ; +switch (chip->pdev->device) {case PCI_DEVICE_ID_O2_SDS0 :case PCI_DEVICE_ID_O2_SEABIRD0 : --2.22.0.410.gd8fdbe21b5-goog
PATCH v2 3/3 mmc: sdhci: Fix indenting on SDHCI_CTRL_8BITBUS
In reply to Raul E RangelRemove whitespace in front of SDHCI_CTRL_8BITBUS. The value is not part of SDHCI_CTRL_DMA_MASK.
---
drivers/mmc/host/sdhci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/mmc/host/sdhci.h +1 -1
@@ -89,7 +89,7 @@#define SDHCI_CTRL_ADMA32 0x10#define SDHCI_CTRL_ADMA64 0x18#define SDHCI_CTRL_ADMA3 0x18 -#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_8BITBUS 0x20#define SDHCI_CTRL_CDTEST_INS 0x40#define SDHCI_CTRL_CDTEST_EN 0x80
Signature · 1 line
2.22.0.410.gd8fdbe21b5-goog
Re: [PATCH v2 3/3] mmc: sdhci: Fix indenting on SDHCI_CTRL_8BITBUS
Quoted 6 lines · Raul E Rangel
Remove whitespace in front of
SDHCI_CTRL_8BITBUS. The value is not part ofSDHCI_CTRL_DMA_MASK.Signed-off-by Raul E Rangel <[email protected]>Acked-by Adrian Hunter <[email protected]>
Applied for next, thanks!
Kind regards
Uffe
Quoted 21 lines
---
drivers/mmc/host/sdhci.h | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)drivers/mmc/host/sdhci.h +1
-2@@ -89,7 +89,7 @@#define SDHCI_CTRL_ADMA32 0x10#define SDHCI_CTRL_ADMA64 0x18#define SDHCI_CTRL_ADMA3 0x18 -#define SDHCI_CTRL_8BITBUS 0x20 +#define SDHCI_CTRL_8BITBUS 0x20#define SDHCI_CTRL_CDTEST_INS 0x40#define SDHCI_CTRL_CDTEST_EN 0x80 --2.22.0.410.gd8fdbe21b5-goog
Quoted 11 lines · Raul E Rangel
The O2Micro controller only supports tuning at 4-bits. So the host driver needs to change the bus width while tuning and then set it back when done.
There was a bug in the original implementation in that
mmc->ios.bus_widthalso wasn't updated. Thus setting the incorrect blocksize insdhci_send_tuningwhich results in a tuning failure.Signed-off-by Raul E Rangel <[email protected]>Fixes 0086fc217d5d7 ("mmc: sdhci: Add support for O2 hardware tuning")Acked-by Adrian Hunter <[email protected]>
Applied for fixes and by adding a stable tag, thanks!
Kind regards
Uffe
Quoted 32 lines
---
drivers/mmc/host/sdhci-pci-o2micro.c | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)drivers/mmc/host/sdhci-pci-o2micro.c +4
-2@@ -115,6 +115,7 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)*/ if (mmc->ios.bus_width ==MMC_BUS_WIDTH_8 ) { current_bus_width = mmc->ios.bus_width; + mmc->ios.bus_width =MMC_BUS_WIDTH_4 ;sdhci_set_bus_width (host,MMC_BUS_WIDTH_4 ); }@@ -126,8 +127,10 @@ static int sdhci_o2_execute_tuning(struct mmc_host *mmc, u32 opcode)sdhci_end_tuning (host); -if (current_bus_width ==MMC_BUS_WIDTH_8 ) +if (current_bus_width ==MMC_BUS_WIDTH_8 ) { + mmc->ios.bus_width =MMC_BUS_WIDTH_8 ;sdhci_set_bus_width (host, current_bus_width); + } host->flags &= ~SDHCI_HS400_TUNING ;return 0 ; --2.22.0.410.gd8fdbe21b5-goog