ram: rk3399: Code cleanup

Fix checkpatch warninigs on sdram_rk3399.c like
- Avoid CamelCase
- Unnecessary parentheses
- Alignment should match open parenthesis
- multiple blank lines
- misspelled
- spaces preferred around that '>>'

Signed-off-by Jagan Teki <[email protected]>

---
  drivers/ram/rockchip/sdram_rk3399.c | 48 ++++++++++++++---------------
  1 file changed, 24 insertions(+), 24 deletions(-)

drivers/ram/rockchip/sdram_rk3399.c +24 -23

index 52518656c4..541e4a4b1e 100644
@@ -47,7 +47,7 @@ struct dram_info {
  #define PRESET_GPIO0_HOLD(n)	((0x1 << (7 + 16)) | ((n) << 7))
  #define PRESET_GPIO1_HOLD(n)	((0x1 << (8 + 16)) | ((n) << 8))
 
-#define PHY_DRV_ODT_Hi_Z	0x0
+#define PHY_DRV_ODT_HI_Z	0x0
  #define PHY_DRV_ODT_240		0x1
  #define PHY_DRV_ODT_120		0x8
  #define PHY_DRV_ODT_80		0x9

@@ -150,7 +150,7 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
  			((16 - row) << 24));
  	/* PI_41 PI_CS_MAP:RW:24:4 */
  	clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
-	if ((sdram_ch->rank == 1) && (sdram_params->base.dramtype == DDR3))
+	if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3)
  		writel(0x2EC7FFFF, &denali_pi[34]);
  }
 

@@ -166,10 +166,10 @@ static void set_ds_odt(const struct chan_info *chan,
  	u32 reg_value;
 
  	if (sdram_params->base.dramtype == LPDDR4) {
-		tsel_rd_select_p = PHY_DRV_ODT_Hi_Z;
+		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
  		tsel_wr_select_p = PHY_DRV_ODT_40;
  		ca_tsel_wr_select_p = PHY_DRV_ODT_40;
-		tsel_idle_select_p = PHY_DRV_ODT_Hi_Z;
+		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 
  		tsel_rd_select_n = PHY_DRV_ODT_240;
  		tsel_wr_select_n = PHY_DRV_ODT_40;

@@ -181,10 +181,10 @@ static void set_ds_odt(const struct chan_info *chan,
  		ca_tsel_wr_select_p = PHY_DRV_ODT_48;
  		tsel_idle_select_p = PHY_DRV_ODT_240;
 
-		tsel_rd_select_n = PHY_DRV_ODT_Hi_Z;
+		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
  		tsel_wr_select_n = PHY_DRV_ODT_34_3;
  		ca_tsel_wr_select_n = PHY_DRV_ODT_48;
-		tsel_idle_select_n = PHY_DRV_ODT_Hi_Z;
+		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
  	} else {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
  		tsel_wr_select_p = PHY_DRV_ODT_34_3;

@@ -294,7 +294,7 @@ static void set_ds_odt(const struct chan_info *chan,
  }
 
  static int phy_io_config(const struct chan_info *chan,
-			  const struct rk3399_sdram_params *sdram_params)
+			 const struct rk3399_sdram_params *sdram_params)
  {
  	u32 *denali_phy = chan->publ->denali_phy;
  	u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;

@@ -423,7 +423,6 @@ static int phy_io_config(const struct chan_info *chan,
  	/* PHY_939 PHY_PAD_CS_DRIVE */
  	clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 
-
  	/* speed setting */
  	if (sdram_params->base.ddr_freq < 400)
  		speed = 0x0;

@@ -492,7 +491,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
  	setbits_le32(&denali_pi[0], START);
  	setbits_le32(&denali_ctl[0], START);
 
-	/* Wating for phy DLL lock */
+	/* Waiting for phy DLL lock */
  	while (1) {
  		tmp = readl(&denali_phy[920]);
  		tmp1 = readl(&denali_phy[921]);

@@ -547,12 +546,12 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
  	/* PHY_DLL_RST_EN */
  	clrsetbits_le32(&denali_phy[957], 0x3 << 24, 0x2 << 24);
 
-	/* Wating for PHY and DRAM init complete */
+	/* Waiting for PHY and DRAM init complete */
  	tmp = get_timer(0);
  	do {
  		if (get_timer(tmp) > timeout_ms) {
  			pr_err("DRAM (%s): phy failed to lock within  %ld ms\n",
-			      __func__, timeout_ms);
+			       __func__, timeout_ms);
  			return -ETIME;
  		}
  	} while (!(readl(&denali_ctl[203]) & (1 << 3)));

@@ -569,7 +568,7 @@ static void select_per_cs_training_index(const struct chan_info *chan,
  	u32 *denali_phy = chan->publ->denali_phy;
 
  	/* PHY_84 PHY_PER_CS_TRAINING_EN_0 1bit offset_16 */
-	if ((readl(&denali_phy[84])>>16) & 1) {
+	if ((readl(&denali_phy[84]) >> 16) & 1) {
  		/*
  		 * PHY_8/136/264/392
  		 * phy_per_cs_training_index_X 1bit offset_24

@@ -646,7 +645,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
  			if ((((tmp >> 11) & 0x1) == 0x1) &&
  			    (((tmp >> 13) & 0x1) == 0x1) &&
  			    (((tmp >> 5) & 0x1) == 0x0) &&
-			    (obs_err == 0))
+			    obs_err == 0)
  				break;
  			else if ((((tmp >> 5) & 0x1) == 0x1) ||
  				 (obs_err == 1))

@@ -700,7 +699,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
  			if ((((tmp >> 10) & 0x1) == 0x1) &&
  			    (((tmp >> 13) & 0x1) == 0x1) &&
  			    (((tmp >> 4) & 0x1) == 0x0) &&
-			    (obs_err == 0))
+			    obs_err == 0)
  				break;
  			else if ((((tmp >> 4) & 0x1) == 0x1) ||
  				 (obs_err == 1))

@@ -759,7 +758,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
  			if ((((tmp >> 9) & 0x1) == 0x1) &&
  			    (((tmp >> 13) & 0x1) == 0x1) &&
  			    (((tmp >> 3) & 0x1) == 0x0) &&
-			    (obs_err == 0))
+			    obs_err == 0)
  				break;
  			else if ((((tmp >> 3) & 0x1) == 0x1) ||
  				 (obs_err == 1))

@@ -955,8 +954,10 @@ static void dram_all_config(struct dram_info *dram,
  		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
  		sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
  		sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
-		sys_reg |= (info->cs0_row - 13) << SYS_REG_CS0_ROW_SHIFT(channel);
-		sys_reg |= (info->cs1_row - 13) << SYS_REG_CS1_ROW_SHIFT(channel);
+		sys_reg |= (info->cs0_row - 13) <<
+			    SYS_REG_CS0_ROW_SHIFT(channel);
+		sys_reg |= (info->cs1_row - 13) <<
+			    SYS_REG_CS1_ROW_SHIFT(channel);
  		sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
  		sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
 

@@ -991,7 +992,7 @@ static void dram_all_config(struct dram_info *dram,
  }
 
  static int switch_to_phy_index1(struct dram_info *dram,
-				 const struct rk3399_sdram_params *sdram_params)
+				const struct rk3399_sdram_params *sdram_params)
  {
  	u32 channel;
  	u32 *denali_phy;

@@ -1026,7 +1027,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
  		denali_phy = dram->chan[channel].publ->denali_phy;
  		clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
  		ret = data_training(&dram->chan[channel], channel,
-				  sdram_params, PI_FULL_TRAINING);
+				    sdram_params, PI_FULL_TRAINING);
  		if (ret) {
  			debug("index1 training failed\n");
  			return ret;

@@ -1116,8 +1117,8 @@ static int conv_of_platdata(struct udevice *dev)
  	int ret;
 
  	ret = regmap_init_mem_platdata(dev, dtplat->reg,
-			ARRAY_SIZE(dtplat->reg) / 2,
-			&plat->map);
+				       ARRAY_SIZE(dtplat->reg) / 2,
+				       &plat->map);
  	if (ret)
  		return ret;
 

@@ -1199,8 +1200,8 @@ static int rk3399_dmc_probe(struct udevice *dev)
  	priv->pmugrf = syscon_get_first_range(ROCKCHIP_SYSCON_PMUGRF);
  	debug("%s: pmugrf=%p\n", __func__, priv->pmugrf);
  	priv->info.base = CONFIG_SYS_SDRAM_BASE;
-	priv->info.size = rockchip_sdram_size(
-			(phys_addr_t)&priv->pmugrf->os_reg2);
+	priv->info.size =
+		rockchip_sdram_size((phys_addr_t)&priv->pmugrf->os_reg2);
  #endif
  	return 0;
  }

- Add proper spaces in data training, rk3399_dmc_init, pctl_cfg
- Order include files
- Move macro after include files

Signed-off-by Jagan Teki <[email protected]>

---
  drivers/ram/rockchip/sdram_rk3399.c | 60 +++++++++++++++++++++--------
  1 file changed, 43 insertions(+), 17 deletions(-)

drivers/ram/rockchip/sdram_rk3399.c +42 -16

index 541e4a4b1e..733864f5d2 100644
@@ -14,14 +14,27 @@
  #include <syscon.h>
  #include <asm/io.h>
  #include <asm/arch-rockchip/clock.h>
-#include <asm/arch-rockchip/sdram_common.h>
-#include <asm/arch-rockchip/sdram_rk3399.h>
  #include <asm/arch-rockchip/cru_rk3399.h>
  #include <asm/arch-rockchip/grf_rk3399.h>
  #include <asm/arch-rockchip/hardware.h>
+#include <asm/arch-rockchip/sdram_common.h>
+#include <asm/arch-rockchip/sdram_rk3399.h>
  #include <linux/err.h>
  #include <time.h>
 
+#define PRESET_SGRF_HOLD(n)	((0x1 << (6 + 16)) | ((n) << 6))
+#define PRESET_GPIO0_HOLD(n)	((0x1 << (7 + 16)) | ((n) << 7))
+#define PRESET_GPIO1_HOLD(n)	((0x1 << (8 + 16)) | ((n) << 8))
+
+#define PHY_DRV_ODT_HI_Z	0x0
+#define PHY_DRV_ODT_240		0x1
+#define PHY_DRV_ODT_120		0x8
+#define PHY_DRV_ODT_80		0x9
+#define PHY_DRV_ODT_60		0xc
+#define PHY_DRV_ODT_48		0xd
+#define PHY_DRV_ODT_40		0xe
+#define PHY_DRV_ODT_34_3	0xf
+
  struct chan_info {
  	struct rk3399_ddr_pctl_regs *pctl;
  	struct rk3399_ddr_pi_regs *pi;

@@ -43,19 +56,6 @@ struct dram_info {
  	struct rk3399_pmugrf_regs *pmugrf;
  };
 
-#define PRESET_SGRF_HOLD(n)	((0x1 << (6 + 16)) | ((n) << 6))
-#define PRESET_GPIO0_HOLD(n)	((0x1 << (7 + 16)) | ((n) << 7))
-#define PRESET_GPIO1_HOLD(n)	((0x1 << (8 + 16)) | ((n) << 8))
-
-#define PHY_DRV_ODT_HI_Z	0x0
-#define PHY_DRV_ODT_240		0x1
-#define PHY_DRV_ODT_120		0x8
-#define PHY_DRV_ODT_80		0x9
-#define PHY_DRV_ODT_60		0xc
-#define PHY_DRV_ODT_48		0xd
-#define PHY_DRV_ODT_40		0xe
-#define PHY_DRV_ODT_34_3	0xf
-
  #if defined(CONFIG_TPL_BUILD) || \
  	(!defined(CONFIG_TPL) && defined(CONFIG_SPL_BUILD))
 

@@ -473,8 +473,10 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
  	copy_to_reg(&denali_ctl[1], &params_ctl[1],
  		    sizeof(struct rk3399_ddr_pctl_regs) - 4);
  	writel(params_ctl[0], &denali_ctl[0]);
+
  	copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
  		    sizeof(struct rk3399_ddr_pi_regs));
+
  	/* rank count need to set for init */
  	set_memory_map(chan, channel, sdram_params);
 

@@ -620,8 +622,10 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);
+
  		/* PI_100 PI_CALVL_EN:RW:8:2 */
  		clrsetbits_le32(&denali_pi[100], 0x3 << 8, 0x2 << 8);
+
  		/* PI_92 PI_CALVL_REQ:WR:16:1,PI_CALVL_CS:RW:24:2 */
  		clrsetbits_le32(&denali_pi[92],
  				(0x1 << 16) | (0x3 << 24),

@@ -651,9 +655,11 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
  				 (obs_err == 1))
  				return -EIO;
  		}
+
  		/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  		writel(0x00003f7c, (&denali_pi[175]));
  	}
+
  	clrbits_le32(&denali_pi[100], 0x3 << 8);
 
  	return 0;

@@ -670,8 +676,10 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);
+
  		/* PI_60 PI_WRLVL_EN:RW:8:2 */
  		clrsetbits_le32(&denali_pi[60], 0x3 << 8, 0x2 << 8);
+
  		/* PI_59 PI_WRLVL_REQ:WR:8:1,PI_WRLVL_CS:RW:16:2 */
  		clrsetbits_le32(&denali_pi[59],
  				(0x1 << 8) | (0x3 << 16),

@@ -705,6 +713,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
  				 (obs_err == 1))
  				return -EIO;
  		}
+
  		/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  		writel(0x00003f7c, (&denali_pi[175]));
  	}

@@ -726,8 +735,10 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);
+
  		/* PI_80 PI_RDLVL_GATE_EN:RW:24:2 */
  		clrsetbits_le32(&denali_pi[80], 0x3 << 24, 0x2 << 24);
+
  		/*
  		 * PI_74 PI_RDLVL_GATE_REQ:WR:16:1
  		 * PI_RDLVL_CS:RW:24:2

@@ -764,9 +775,11 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
  				 (obs_err == 1))
  				return -EIO;
  		}
+
  		/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  		writel(0x00003f7c, (&denali_pi[175]));
  	}
+
  	clrbits_le32(&denali_pi[80], 0x3 << 24);
 
  	return 0;

@@ -781,8 +794,10 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);
+
  		/* PI_80 PI_RDLVL_EN:RW:16:2 */
  		clrsetbits_le32(&denali_pi[80], 0x3 << 16, 0x2 << 16);
+
  		/* PI_74 PI_RDLVL_REQ:WR:8:1,PI_RDLVL_CS:RW:24:2 */
  		clrsetbits_le32(&denali_pi[74],
  				(0x1 << 8) | (0x3 << 24),

@@ -805,9 +820,11 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
  			else if (((tmp >> 2) & 0x1) == 0x1)
  				return -EIO;
  		}
+
  		/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  		writel(0x00003f7c, (&denali_pi[175]));
  	}
+
  	clrbits_le32(&denali_pi[80], 0x3 << 16);
 
  	return 0;

@@ -822,13 +839,16 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);
+
  		/*
  		 * disable PI_WDQLVL_VREF_EN before wdq leveling?
  		 * PI_181 PI_WDQLVL_VREF_EN:RW:8:1
  		 */
  		clrbits_le32(&denali_pi[181], 0x1 << 8);
+
  		/* PI_124 PI_WDQLVL_EN:RW:16:2 */
  		clrsetbits_le32(&denali_pi[124], 0x3 << 16, 0x2 << 16);
+
  		/* PI_121 PI_WDQLVL_REQ:WR:8:1,PI_WDQLVL_CS:RW:16:2 */
  		clrsetbits_le32(&denali_pi[121],
  				(0x1 << 8) | (0x3 << 16),

@@ -845,9 +865,11 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
  			else if (((tmp >> 6) & 0x1) == 0x1)
  				return -EIO;
  		}
+
  		/* clear interrupt,PI_175 PI_INT_ACK:WR:0:17 */
  		writel(0x00003f7c, (&denali_pi[175]));
  	}
+
  	clrbits_le32(&denali_pi[124], 0x3 << 16);
 
  	return 0;

@@ -938,6 +960,7 @@ static void dram_all_config(struct dram_info *dram,
  	sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
  	sys_reg |= (sdram_params->base.num_channels - 1)
  		    << SYS_REG_NUM_CH_SHIFT;
+
  	for (channel = 0, idx = 0;
  	     (idx < sdram_params->base.num_channels) && (channel < 2);
  	     channel++) {

@@ -1164,6 +1187,7 @@ static int rk3399_dmc_init(struct udevice *dev)
  	      priv->chan[1].publ, priv->chan[1].msch);
  	debug("cru %p, cic %p, grf %p, sgrf %p, pmucru %p\n", priv->cru,
  	      priv->cic, priv->pmugrf, priv->pmusgrf, priv->pmucru);
+
  #if CONFIG_IS_ENABLED(OF_PLATDATA)
  	ret = clk_get_by_index_platdata(dev, 0, dtplat->clocks, &priv->ddr_clk);
  #else

@@ -1173,14 +1197,16 @@ static int rk3399_dmc_init(struct udevice *dev)
  		printf("%s clk get failed %d\n", __func__, ret);
  		return ret;
  	}
+
  	ret = clk_set_rate(&priv->ddr_clk, params->base.ddr_freq * MHz);
  	if (ret < 0) {
  		printf("%s clk set failed %d\n", __func__, ret);
  		return ret;
  	}
+
  	ret = sdram_init(priv, params);
  	if (ret < 0) {
-		printf("%s DRAM init failed%d\n", __func__, ret);
+		printf("%s DRAM init failed %d\n", __func__, ret);
  		return ret;
  	}
 

Rename variable name of struct rk3399_sdram_params from sdram_params with params for more code readability.

No functionality change.

Signed-off-by Jagan Teki <[email protected]>

---
  drivers/ram/rockchip/sdram_rk3399.c | 160 ++++++++++++++--------------
  1 file changed, 78 insertions(+), 82 deletions(-)

drivers/ram/rockchip/sdram_rk3399.c +74 -80

index 733864f5d2..c918c2e588 100644
@@ -111,10 +111,9 @@ static void phy_dll_bypass_set(struct rk3399_ddr_publ_regs *ddr_publ_regs,
  }
 
  static void set_memory_map(const struct chan_info *chan, u32 channel,
-			   const struct rk3399_sdram_params *sdram_params)
+			   const struct rk3399_sdram_params *params)
  {
-	const struct rk3399_sdram_channel *sdram_ch =
-		&sdram_params->ch[channel];
+	const struct rk3399_sdram_channel *sdram_ch = &params->ch[channel];
  	u32 *denali_ctl = chan->pctl->denali_ctl;
  	u32 *denali_pi = chan->pi->denali_pi;
  	u32 cs_map;

@@ -150,12 +149,12 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
  			((16 - row) << 24));
  	/* PI_41 PI_CS_MAP:RW:24:4 */
  	clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
-	if (sdram_ch->rank == 1 && sdram_params->base.dramtype == DDR3)
+	if (sdram_ch->rank == 1 && params->base.dramtype == DDR3)
  		writel(0x2EC7FFFF, &denali_pi[34]);
  }
 
  static void set_ds_odt(const struct chan_info *chan,
-		       const struct rk3399_sdram_params *sdram_params)
+		       const struct rk3399_sdram_params *params)
  {
  	u32 *denali_phy = chan->publ->denali_phy;
 

@@ -165,7 +164,7 @@ static void set_ds_odt(const struct chan_info *chan,
  	u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
  	u32 reg_value;
 
-	if (sdram_params->base.dramtype == LPDDR4) {
+	if (params->base.dramtype == LPDDR4) {
  		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
  		tsel_wr_select_p = PHY_DRV_ODT_40;
  		ca_tsel_wr_select_p = PHY_DRV_ODT_40;

@@ -175,7 +174,7 @@ static void set_ds_odt(const struct chan_info *chan,
  		tsel_wr_select_n = PHY_DRV_ODT_40;
  		ca_tsel_wr_select_n = PHY_DRV_ODT_40;
  		tsel_idle_select_n = PHY_DRV_ODT_240;
-	} else if (sdram_params->base.dramtype == LPDDR3) {
+	} else if (params->base.dramtype == LPDDR3) {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
  		tsel_wr_select_p = PHY_DRV_ODT_34_3;
  		ca_tsel_wr_select_p = PHY_DRV_ODT_48;

@@ -197,7 +196,7 @@ static void set_ds_odt(const struct chan_info *chan,
  		tsel_idle_select_n = PHY_DRV_ODT_240;
  	}
 
-	if (sdram_params->base.odt == 1)
+	if (params->base.odt == 1)
  		tsel_rd_en = 1;
  	else
  		tsel_rd_en = 0;

@@ -294,7 +293,7 @@ static void set_ds_odt(const struct chan_info *chan,
  }
 
  static int phy_io_config(const struct chan_info *chan,
-			 const struct rk3399_sdram_params *sdram_params)
+			 const struct rk3399_sdram_params *params)
  {
  	u32 *denali_phy = chan->publ->denali_phy;
  	u32 vref_mode_dq, vref_value_dq, vref_mode_ac, vref_value_ac;

@@ -304,14 +303,14 @@ static int phy_io_config(const struct chan_info *chan,
  	u32 speed;
 
  	/* vref setting */
-	if (sdram_params->base.dramtype == LPDDR4) {
+	if (params->base.dramtype == LPDDR4) {
  		/* LPDDR4 */
  		vref_mode_dq = 0x6;
  		vref_value_dq = 0x1f;
  		vref_mode_ac = 0x6;
  		vref_value_ac = 0x1f;
-	} else if (sdram_params->base.dramtype == LPDDR3) {
-		if (sdram_params->base.odt == 1) {
+	} else if (params->base.dramtype == LPDDR3) {
+		if (params->base.odt == 1) {
  			vref_mode_dq = 0x5;  /* LPDDR3 ODT */
  			drv_value = (readl(&denali_phy[6]) >> 12) & 0xf;
  			odt_value = (readl(&denali_phy[6]) >> 4) & 0xf;

@@ -370,7 +369,7 @@ static int phy_io_config(const struct chan_info *chan,
  		}
  		vref_mode_ac = 0x2;
  		vref_value_ac = 0x1f;
-	} else if (sdram_params->base.dramtype == DDR3) {
+	} else if (params->base.dramtype == DDR3) {
  		/* DDR3L */
  		vref_mode_dq = 0x1;
  		vref_value_dq = 0x1f;

@@ -397,11 +396,11 @@ static int phy_io_config(const struct chan_info *chan,
  	/* PHY_915 PHY_PAD_VREF_CTRL_AC 12bits offset_16 */
  	clrsetbits_le32(&denali_phy[915], 0xfff << 16, reg_value << 16);
 
-	if (sdram_params->base.dramtype == LPDDR4)
+	if (params->base.dramtype == LPDDR4)
  		mode_sel = 0x6;
-	else if (sdram_params->base.dramtype == LPDDR3)
+	else if (params->base.dramtype == LPDDR3)
  		mode_sel = 0x0;
-	else if (sdram_params->base.dramtype == DDR3)
+	else if (params->base.dramtype == DDR3)
  		mode_sel = 0x1;
  	else
  		return -EINVAL;

@@ -424,11 +423,11 @@ static int phy_io_config(const struct chan_info *chan,
  	clrsetbits_le32(&denali_phy[939], 0x7 << 14, mode_sel << 14);
 
  	/* speed setting */
-	if (sdram_params->base.ddr_freq < 400)
+	if (params->base.ddr_freq < 400)
  		speed = 0x0;
-	else if (sdram_params->base.ddr_freq < 800)
+	else if (params->base.ddr_freq < 800)
  		speed = 0x1;
-	else if (sdram_params->base.ddr_freq < 1200)
+	else if (params->base.ddr_freq < 1200)
  		speed = 0x2;
  	else
  		speed = 0x3;

@@ -454,13 +453,13 @@ static int phy_io_config(const struct chan_info *chan,
  }
 
  static int pctl_cfg(const struct chan_info *chan, u32 channel,
-		    const struct rk3399_sdram_params *sdram_params)
+		    const struct rk3399_sdram_params *params)
  {
  	u32 *denali_ctl = chan->pctl->denali_ctl;
  	u32 *denali_pi = chan->pi->denali_pi;
  	u32 *denali_phy = chan->publ->denali_phy;
-	const u32 *params_ctl = sdram_params->pctl_regs.denali_ctl;
-	const u32 *params_phy = sdram_params->phy_regs.denali_phy;
+	const u32 *params_ctl = params->pctl_regs.denali_ctl;
+	const u32 *params_phy = params->phy_regs.denali_phy;
  	u32 tmp, tmp1, tmp2;
  	u32 pwrup_srefresh_exit;
  	int ret;

@@ -474,15 +473,15 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
  		    sizeof(struct rk3399_ddr_pctl_regs) - 4);
  	writel(params_ctl[0], &denali_ctl[0]);
 
-	copy_to_reg(denali_pi, &sdram_params->pi_regs.denali_pi[0],
+	copy_to_reg(denali_pi, &params->pi_regs.denali_pi[0],
  		    sizeof(struct rk3399_ddr_pi_regs));
 
  	/* rank count need to set for init */
-	set_memory_map(chan, channel, sdram_params);
+	set_memory_map(chan, channel, params);
 
-	writel(sdram_params->phy_regs.denali_phy[910], &denali_phy[910]);
-	writel(sdram_params->phy_regs.denali_phy[911], &denali_phy[911]);
-	writel(sdram_params->phy_regs.denali_phy[912], &denali_phy[912]);
+	writel(params->phy_regs.denali_phy[910], &denali_phy[910]);
+	writel(params->phy_regs.denali_phy[911], &denali_phy[911]);
+	writel(params->phy_regs.denali_phy[912], &denali_phy[912]);
 
  	pwrup_srefresh_exit = readl(&denali_ctl[68]) & PWRUP_SREFRESH_EXIT;
  	clrbits_le32(&denali_ctl[68], PWRUP_SREFRESH_EXIT);

@@ -513,7 +512,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
  	copy_to_reg(&denali_phy[512], &params_phy[512], (549 - 512 + 1) * 4);
  	copy_to_reg(&denali_phy[640], &params_phy[640], (677 - 640 + 1) * 4);
  	copy_to_reg(&denali_phy[768], &params_phy[768], (805 - 768 + 1) * 4);
-	set_ds_odt(chan, sdram_params);
+	set_ds_odt(chan, params);
 
  	/*
  	 * phy_dqs_tsel_wr_timing_X 8bits DENALI_PHY_84/212/340/468 offset_8

@@ -541,7 +540,7 @@ static int pctl_cfg(const struct chan_info *chan, u32 channel,
  	tmp = (readl(&denali_phy[467]) >> 16) & 0xff;
  	clrsetbits_le32(&denali_phy[467], 0xff << 16, (tmp + 0x10) << 16);
 
-	ret = phy_io_config(chan, sdram_params);
+	ret = phy_io_config(chan, params);
  	if (ret)
  		return ret;
 

@@ -612,13 +611,13 @@ static void override_write_leveling_value(const struct chan_info *chan)
  }
 
  static int data_training_ca(const struct chan_info *chan, u32 channel,
-			    const struct rk3399_sdram_params *sdram_params)
+			    const struct rk3399_sdram_params *params)
  {
  	u32 *denali_pi = chan->pi->denali_pi;
  	u32 *denali_phy = chan->publ->denali_phy;
  	u32 i, tmp;
  	u32 obs_0, obs_1, obs_2, obs_err = 0;
-	u32 rank = sdram_params->ch[channel].rank;
+	u32 rank = params->ch[channel].rank;
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);

@@ -666,13 +665,13 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
  }
 
  static int data_training_wl(const struct chan_info *chan, u32 channel,
-			    const struct rk3399_sdram_params *sdram_params)
+			    const struct rk3399_sdram_params *params)
  {
  	u32 *denali_pi = chan->pi->denali_pi;
  	u32 *denali_phy = chan->publ->denali_phy;
  	u32 i, tmp;
  	u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
-	u32 rank = sdram_params->ch[channel].rank;
+	u32 rank = params->ch[channel].rank;
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);

@@ -725,13 +724,13 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
  }
 
  static int data_training_rg(const struct chan_info *chan, u32 channel,
-			    const struct rk3399_sdram_params *sdram_params)
+			    const struct rk3399_sdram_params *params)
  {
  	u32 *denali_pi = chan->pi->denali_pi;
  	u32 *denali_phy = chan->publ->denali_phy;
  	u32 i, tmp;
  	u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
-	u32 rank = sdram_params->ch[channel].rank;
+	u32 rank = params->ch[channel].rank;
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);

@@ -786,11 +785,11 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
  }
 
  static int data_training_rl(const struct chan_info *chan, u32 channel,
-			    const struct rk3399_sdram_params *sdram_params)
+			    const struct rk3399_sdram_params *params)
  {
  	u32 *denali_pi = chan->pi->denali_pi;
  	u32 i, tmp;
-	u32 rank = sdram_params->ch[channel].rank;
+	u32 rank = params->ch[channel].rank;
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);

@@ -831,11 +830,11 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
  }
 
  static int data_training_wdql(const struct chan_info *chan, u32 channel,
-			      const struct rk3399_sdram_params *sdram_params)
+			      const struct rk3399_sdram_params *params)
  {
  	u32 *denali_pi = chan->pi->denali_pi;
  	u32 i, tmp;
-	u32 rank = sdram_params->ch[channel].rank;
+	u32 rank = params->ch[channel].rank;
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);

@@ -876,7 +875,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
  }
 
  static int data_training(const struct chan_info *chan, u32 channel,
-			 const struct rk3399_sdram_params *sdram_params,
+			 const struct rk3399_sdram_params *params,
  			 u32 training_flag)
  {
  	u32 *denali_phy = chan->publ->denali_phy;

@@ -885,14 +884,14 @@ static int data_training(const struct chan_info *chan, u32 channel,
  	setbits_le32(&denali_phy[927], (1 << 22));
 
  	if (training_flag == PI_FULL_TRAINING) {
-		if (sdram_params->base.dramtype == LPDDR4) {
+		if (params->base.dramtype == LPDDR4) {
  			training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
  					PI_READ_GATE_TRAINING |
  					PI_READ_LEVELING | PI_WDQ_LEVELING;
-		} else if (sdram_params->base.dramtype == LPDDR3) {
+		} else if (params->base.dramtype == LPDDR3) {
  			training_flag = PI_CA_TRAINING | PI_WRITE_LEVELING |
  					PI_READ_GATE_TRAINING;
-		} else if (sdram_params->base.dramtype == DDR3) {
+		} else if (params->base.dramtype == DDR3) {
  			training_flag = PI_WRITE_LEVELING |
  					PI_READ_GATE_TRAINING |
  					PI_READ_LEVELING;

@@ -901,23 +900,23 @@ static int data_training(const struct chan_info *chan, u32 channel,
 
  	/* ca training(LPDDR4,LPDDR3 support) */
  	if ((training_flag & PI_CA_TRAINING) == PI_CA_TRAINING)
-		data_training_ca(chan, channel, sdram_params);
+		data_training_ca(chan, channel, params);
 
  	/* write leveling(LPDDR4,LPDDR3,DDR3 support) */
  	if ((training_flag & PI_WRITE_LEVELING) == PI_WRITE_LEVELING)
-		data_training_wl(chan, channel, sdram_params);
+		data_training_wl(chan, channel, params);
 
  	/* read gate training(LPDDR4,LPDDR3,DDR3 support) */
  	if ((training_flag & PI_READ_GATE_TRAINING) == PI_READ_GATE_TRAINING)
-		data_training_rg(chan, channel, sdram_params);
+		data_training_rg(chan, channel, params);
 
  	/* read leveling(LPDDR4,LPDDR3,DDR3 support) */
  	if ((training_flag & PI_READ_LEVELING) == PI_READ_LEVELING)
-		data_training_rl(chan, channel, sdram_params);
+		data_training_rl(chan, channel, params);
 
  	/* wdq leveling(LPDDR4 support) */
  	if ((training_flag & PI_WDQ_LEVELING) == PI_WDQ_LEVELING)
-		data_training_wdql(chan, channel, sdram_params);
+		data_training_wdql(chan, channel, params);
 
  	/* PHY_927 PHY_PAD_DQS_DRIVE  RPULL offset_22 */
  	clrbits_le32(&denali_phy[927], (1 << 22));

@@ -926,7 +925,7 @@ static int data_training(const struct chan_info *chan, u32 channel,
  }
 
  static void set_ddrconfig(const struct chan_info *chan,
-			  const struct rk3399_sdram_params *sdram_params,
+			  const struct rk3399_sdram_params *params,
  			  unsigned char channel, u32 ddrconfig)
  {
  	/* only need to set ddrconfig */

@@ -934,14 +933,14 @@ static void set_ddrconfig(const struct chan_info *chan,
  	unsigned int cs0_cap = 0;
  	unsigned int cs1_cap = 0;
 
-	cs0_cap = (1 << (sdram_params->ch[channel].cs0_row
-			+ sdram_params->ch[channel].col
-			+ sdram_params->ch[channel].bk
-			+ sdram_params->ch[channel].bw - 20));
-	if (sdram_params->ch[channel].rank > 1)
-		cs1_cap = cs0_cap >> (sdram_params->ch[channel].cs0_row
-				- sdram_params->ch[channel].cs1_row);
-	if (sdram_params->ch[channel].row_3_4) {
+	cs0_cap = (1 << (params->ch[channel].cs0_row
+			+ params->ch[channel].col
+			+ params->ch[channel].bk
+			+ params->ch[channel].bw - 20));
+	if (params->ch[channel].rank > 1)
+		cs1_cap = cs0_cap >> (params->ch[channel].cs0_row
+				- params->ch[channel].cs1_row);
+	if (params->ch[channel].row_3_4) {
  		cs0_cap = cs0_cap * 3 / 4;
  		cs1_cap = cs1_cap * 3 / 4;
  	}

@@ -952,24 +951,22 @@ static void set_ddrconfig(const struct chan_info *chan,
  }
 
  static void dram_all_config(struct dram_info *dram,
-			    const struct rk3399_sdram_params *sdram_params)
+			    const struct rk3399_sdram_params *params)
  {
  	u32 sys_reg = 0;
  	unsigned int channel, idx;
 
-	sys_reg |= sdram_params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
-	sys_reg |= (sdram_params->base.num_channels - 1)
-		    << SYS_REG_NUM_CH_SHIFT;
+	sys_reg |= params->base.dramtype << SYS_REG_DDRTYPE_SHIFT;
+	sys_reg |= (params->base.num_channels - 1) << SYS_REG_NUM_CH_SHIFT;
 
  	for (channel = 0, idx = 0;
-	     (idx < sdram_params->base.num_channels) && (channel < 2);
+	     (idx < params->base.num_channels) && (channel < 2);
  	     channel++) {
-		const struct rk3399_sdram_channel *info =
-			&sdram_params->ch[channel];
+		const struct rk3399_sdram_channel *info = &params->ch[channel];
  		struct rk3399_msch_regs *ddr_msch_regs;
  		const struct rk3399_msch_timings *noc_timing;
 
-		if (sdram_params->ch[channel].col == 0)
+		if (params->ch[channel].col == 0)
  			continue;
  		idx++;
  		sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel);

@@ -985,7 +982,7 @@ static void dram_all_config(struct dram_info *dram,
  		sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
 
  		ddr_msch_regs = dram->chan[channel].msch;
-		noc_timing = &sdram_params->ch[channel].noc_timings;
+		noc_timing = &params->ch[channel].noc_timings;
  		writel(noc_timing->ddrtiminga0,
  		       &ddr_msch_regs->ddrtiminga0);
  		writel(noc_timing->ddrtimingb0,

@@ -998,14 +995,14 @@ static void dram_all_config(struct dram_info *dram,
  		       &ddr_msch_regs->ddrmode);
 
  		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
-		if (sdram_params->ch[channel].rank == 1)
+		if (params->ch[channel].rank == 1)
  			setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
  				     1 << 17);
  	}
 
  	writel(sys_reg, &dram->pmugrf->os_reg2);
  	rk_clrsetreg(&dram->pmusgrf->soc_con4, 0x1f << 10,
-		     sdram_params->base.stride << 10);
+		     params->base.stride << 10);
 
  	/* reboot hold register set */
  	writel(PRESET_SGRF_HOLD(0) | PRESET_GPIO0_HOLD(1) |

@@ -1015,11 +1012,11 @@ static void dram_all_config(struct dram_info *dram,
  }
 
  static int switch_to_phy_index1(struct dram_info *dram,
-				const struct rk3399_sdram_params *sdram_params)
+				const struct rk3399_sdram_params *params)
  {
  	u32 channel;
  	u32 *denali_phy;
-	u32 ch_count = sdram_params->base.num_channels;
+	u32 ch_count = params->base.num_channels;
  	int ret;
  	int i = 0;
 

@@ -1050,7 +1047,7 @@ static int switch_to_phy_index1(struct dram_info *dram,
  		denali_phy = dram->chan[channel].publ->denali_phy;
  		clrsetbits_le32(&denali_phy[896], (0x3 << 8) | 1, 1 << 8);
  		ret = data_training(&dram->chan[channel], channel,
-				    sdram_params, PI_FULL_TRAINING);
+				    params, PI_FULL_TRAINING);
  		if (ret) {
  			debug("index1 training failed\n");
  			return ret;

@@ -1061,10 +1058,10 @@ static int switch_to_phy_index1(struct dram_info *dram,
  }
 
  static int sdram_init(struct dram_info *dram,
-		      const struct rk3399_sdram_params *sdram_params)
+		      const struct rk3399_sdram_params *params)
  {
-	unsigned char dramtype = sdram_params->base.dramtype;
-	unsigned int ddr_freq = sdram_params->base.ddr_freq;
+	unsigned char dramtype = params->base.dramtype;
+	unsigned int ddr_freq = params->base.ddr_freq;
  	int channel;
 
  	debug("Starting SDRAM initialization...\n");

@@ -1082,10 +1079,10 @@ static int sdram_init(struct dram_info *dram,
 
  		phy_dll_bypass_set(publ, ddr_freq);
 
-		if (channel >= sdram_params->base.num_channels)
+		if (channel >= params->base.num_channels)
  			continue;
 
-		if (pctl_cfg(chan, channel, sdram_params) != 0) {
+		if (pctl_cfg(chan, channel, params) != 0) {
  			printf("pctl_cfg fail, reset\n");
  			return -EIO;
  		}

@@ -1094,17 +1091,16 @@ static int sdram_init(struct dram_info *dram,
  		if (dramtype == LPDDR3)
  			udelay(10);
 
-		if (data_training(chan, channel,
-				  sdram_params, PI_FULL_TRAINING)) {
+		if (data_training(chan, channel, params, PI_FULL_TRAINING)) {
  			printf("SDRAM initialization failed, reset\n");
  			return -EIO;
  		}
 
-		set_ddrconfig(chan, sdram_params, channel,
-			      sdram_params->ch[channel].ddrconfig);

Add proper return type handling of pctl_cfg with
meaningful print statement.

Signed-off-by Jagan Teki <[email protected]>

---
  drivers/ram/rockchip/sdram_rk3399.c | 8 +++++---
  1 file changed, 5 insertions(+), 3 deletions(-)

drivers/ram/rockchip/sdram_rk3399.c +1 -0

index c918c2e588..de5d8c1b5f 100644
@@ -1063,6 +1063,7 @@ static int sdram_init(struct dram_info *dram,
  	unsigned char dramtype = params->base.dramtype;
  	unsigned int ddr_freq = params->base.ddr_freq;
  	int channel;
+	int ret;
 
  	debug("Starting SDRAM initialization...\n");
 

@@ -1082,9 +1083,10 @@ static int sdram_init(struct dram_info *dram,
  		if (channel >= params->base.num_channels)
  			continue;
 

Rename tsel_wr_select_n to tsel_wr_select_dq_n based on the bsp code.

No functionality change.

Signed-off-by Jagan Teki <[email protected]>

Signed-off-by YouMin Chen <[email protected]>

---
  drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------
  1 file changed, 6 insertions(+), 6 deletions(-)

drivers/ram/rockchip/sdram_rk3399.c +5 -5

index de5d8c1b5f..85ff47f133 100644
@@ -161,7 +161,7 @@ static void set_ds_odt(const struct chan_info *chan,
  	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
  	u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
  	u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
-	u32 tsel_idle_select_n, tsel_wr_select_n, tsel_rd_select_n;
+	u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
  	u32 reg_value;
 
  	if (params->base.dramtype == LPDDR4) {

@@ -171,7 +171,7 @@ static void set_ds_odt(const struct chan_info *chan,
  		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 
  		tsel_rd_select_n = PHY_DRV_ODT_240;
-		tsel_wr_select_n = PHY_DRV_ODT_40;
+		tsel_wr_select_dq_n = PHY_DRV_ODT_40;
  		ca_tsel_wr_select_n = PHY_DRV_ODT_40;
  		tsel_idle_select_n = PHY_DRV_ODT_240;
  	} else if (params->base.dramtype == LPDDR3) {

@@ -181,7 +181,7 @@ static void set_ds_odt(const struct chan_info *chan,
  		tsel_idle_select_p = PHY_DRV_ODT_240;
 
  		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
-		tsel_wr_select_n = PHY_DRV_ODT_34_3;
+		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
  		ca_tsel_wr_select_n = PHY_DRV_ODT_48;
  		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
  	} else {

@@ -191,7 +191,7 @@ static void set_ds_odt(const struct chan_info *chan,
  		tsel_idle_select_p = PHY_DRV_ODT_240;
 
  		tsel_rd_select_n = PHY_DRV_ODT_240;
-		tsel_wr_select_n = PHY_DRV_ODT_34_3;
+		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
  		ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
  		tsel_idle_select_n = PHY_DRV_ODT_240;
  	}

@@ -210,7 +210,7 @@ static void set_ds_odt(const struct chan_info *chan,
  	 * for write cycles for DQ/DM
  	 */
  	reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
-		    (tsel_wr_select_n << 8) | (tsel_wr_select_p << 12) |
+		    (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) |
  		    (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
  	clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
  	clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);

Rename tsel_wr_select_p to tsel_wr_select_dq_p based on the bsp code.

No functionality change.

Signed-off-by Jagan Teki <[email protected]>

Signed-off-by YouMin Chen <[email protected]>

---
  drivers/ram/rockchip/sdram_rk3399.c | 12 ++++++------
  1 file changed, 6 insertions(+), 6 deletions(-)

drivers/ram/rockchip/sdram_rk3399.c +5 -5

index 85ff47f133..3ec32bdbc0 100644
@@ -159,14 +159,14 @@ static void set_ds_odt(const struct chan_info *chan,
  	u32 *denali_phy = chan->publ->denali_phy;
 
  	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
-	u32 tsel_idle_select_p, tsel_wr_select_p, tsel_rd_select_p;
+	u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
  	u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
  	u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
  	u32 reg_value;
 
  	if (params->base.dramtype == LPDDR4) {
  		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
-		tsel_wr_select_p = PHY_DRV_ODT_40;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
  		ca_tsel_wr_select_p = PHY_DRV_ODT_40;
  		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 

@@ -176,7 +176,7 @@ static void set_ds_odt(const struct chan_info *chan,
  		tsel_idle_select_n = PHY_DRV_ODT_240;
  	} else if (params->base.dramtype == LPDDR3) {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
-		tsel_wr_select_p = PHY_DRV_ODT_34_3;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
  		ca_tsel_wr_select_p = PHY_DRV_ODT_48;
  		tsel_idle_select_p = PHY_DRV_ODT_240;
 

@@ -186,7 +186,7 @@ static void set_ds_odt(const struct chan_info *chan,
  		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
  	} else {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
-		tsel_wr_select_p = PHY_DRV_ODT_34_3;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
  		ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
  		tsel_idle_select_p = PHY_DRV_ODT_240;
 

@@ -210,7 +210,7 @@ static void set_ds_odt(const struct chan_info *chan,
  	 * for write cycles for DQ/DM
  	 */
  	reg_value = tsel_rd_select_n | (tsel_rd_select_p << 0x4) |
-		    (tsel_wr_select_dq_n << 8) | (tsel_wr_select_p << 12) |
+		    (tsel_wr_select_dq_n << 8) | (tsel_wr_select_dq_p << 12) |
  		    (tsel_idle_select_n << 16) | (tsel_idle_select_p << 20);
  	clrsetbits_le32(&denali_phy[6], 0xffffff, reg_value);
  	clrsetbits_le32(&denali_phy[134], 0xffffff, reg_value);

Rename ca_tsel_wr_select_n to tsel_wr_select_ca_n based on the bsp code.

No functionality change.

Signed-off-by Jagan Teki <[email protected]>

Signed-off-by YouMin Chen <[email protected]>

---
  drivers/ram/rockchip/sdram_rk3399.c | 10 +++++-----
  1 file changed, 5 insertions(+), 5 deletions(-)

drivers/ram/rockchip/sdram_rk3399.c +4 -4

index 3ec32bdbc0..bdb46a0128 100644
@@ -160,7 +160,7 @@ static void set_ds_odt(const struct chan_info *chan,
 
  	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
  	u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
-	u32 ca_tsel_wr_select_p, ca_tsel_wr_select_n;
+	u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n;
  	u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
  	u32 reg_value;
 

@@ -172,7 +172,7 @@ static void set_ds_odt(const struct chan_info *chan,
 
  		tsel_rd_select_n = PHY_DRV_ODT_240;
  		tsel_wr_select_dq_n = PHY_DRV_ODT_40;
-		ca_tsel_wr_select_n = PHY_DRV_ODT_40;
+		tsel_wr_select_ca_n = PHY_DRV_ODT_40;
  		tsel_idle_select_n = PHY_DRV_ODT_240;
  	} else if (params->base.dramtype == LPDDR3) {
  		tsel_rd_select_p = PHY_DRV_ODT_240;

@@ -182,7 +182,7 @@ static void set_ds_odt(const struct chan_info *chan,
 
  		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
  		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
-		ca_tsel_wr_select_n = PHY_DRV_ODT_48;
+		tsel_wr_select_ca_n = PHY_DRV_ODT_48;
  		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
  	} else {
  		tsel_rd_select_p = PHY_DRV_ODT_240;

@@ -192,7 +192,7 @@ static void set_ds_odt(const struct chan_info *chan,
 
  		tsel_rd_select_n = PHY_DRV_ODT_240;
  		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
-		ca_tsel_wr_select_n = PHY_DRV_ODT_34_3;
+		tsel_wr_select_ca_n = PHY_DRV_ODT_34_3;
  		tsel_idle_select_n = PHY_DRV_ODT_240;
  	}
 

Rename ca_tsel_wr_select_p to tsel_wr_select_ca_p based on the bsp code.

No functionality change.

Signed-off-by Jagan Teki <[email protected]>

Signed-off-by YouMin Chen <[email protected]>

---
  drivers/ram/rockchip/sdram_rk3399.c | 10 +++++-----
  1 file changed, 5 insertions(+), 5 deletions(-)

drivers/ram/rockchip/sdram_rk3399.c +4 -4

index bdb46a0128..8a983f9bb1 100644
@@ -160,14 +160,14 @@ static void set_ds_odt(const struct chan_info *chan,
 
  	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
  	u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
-	u32 ca_tsel_wr_select_p, tsel_wr_select_ca_n;
+	u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
  	u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
  	u32 reg_value;
 
  	if (params->base.dramtype == LPDDR4) {
  		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
  		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
-		ca_tsel_wr_select_p = PHY_DRV_ODT_40;
+		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
  		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
 
  		tsel_rd_select_n = PHY_DRV_ODT_240;

@@ -177,7 +177,7 @@ static void set_ds_odt(const struct chan_info *chan,
  	} else if (params->base.dramtype == LPDDR3) {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
  		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
-		ca_tsel_wr_select_p = PHY_DRV_ODT_48;
+		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
  		tsel_idle_select_p = PHY_DRV_ODT_240;
 
  		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;

@@ -187,7 +187,7 @@ static void set_ds_odt(const struct chan_info *chan,
  	} else {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
  		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
-		ca_tsel_wr_select_p = PHY_DRV_ODT_34_3;
+		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
  		tsel_idle_select_p = PHY_DRV_ODT_240;
 
  		tsel_rd_select_n = PHY_DRV_ODT_240;

Order tsel* variable declarations and assignment in proper and meaningful way.

No functionality change.

Signed-off-by Jagan Teki <[email protected]>

Signed-off-by YouMin Chen <[email protected]>

---
  drivers/ram/rockchip/sdram_rk3399.c | 37 +++++++++++++++++------------
  1 file changed, 22 insertions(+), 15 deletions(-)

drivers/ram/rockchip/sdram_rk3399.c +19 -13

index 8a983f9bb1..043b27737d 100644
@@ -159,41 +159,48 @@ static void set_ds_odt(const struct chan_info *chan,
  	u32 *denali_phy = chan->publ->denali_phy;
 
  	u32 tsel_idle_en, tsel_wr_en, tsel_rd_en;
-	u32 tsel_idle_select_p, tsel_wr_select_dq_p, tsel_rd_select_p;
-	u32 tsel_wr_select_ca_p, tsel_wr_select_ca_n;
-	u32 tsel_idle_select_n, tsel_wr_select_dq_n, tsel_rd_select_n;
+	u32 tsel_idle_select_p, tsel_rd_select_p;
+	u32 tsel_idle_select_n, tsel_rd_select_n;
+	u32 tsel_wr_select_dq_p, tsel_wr_select_ca_p;
+	u32 tsel_wr_select_dq_n, tsel_wr_select_ca_n;
  	u32 reg_value;
 
  	if (params->base.dramtype == LPDDR4) {
  		tsel_rd_select_p = PHY_DRV_ODT_HI_Z;
-		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
-		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
+		tsel_rd_select_n = PHY_DRV_ODT_240;
+
  		tsel_idle_select_p = PHY_DRV_ODT_HI_Z;
+		tsel_idle_select_n = PHY_DRV_ODT_240;
 
-		tsel_rd_select_n = PHY_DRV_ODT_240;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_40;
  		tsel_wr_select_dq_n = PHY_DRV_ODT_40;
+
+		tsel_wr_select_ca_p = PHY_DRV_ODT_40;
  		tsel_wr_select_ca_n = PHY_DRV_ODT_40;
-		tsel_idle_select_n = PHY_DRV_ODT_240;
  	} else if (params->base.dramtype == LPDDR3) {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
-		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
-		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
+		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+
  		tsel_idle_select_p = PHY_DRV_ODT_240;
+		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
 
-		tsel_rd_select_n = PHY_DRV_ODT_HI_Z;
+		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
  		tsel_wr_select_dq_n = PHY_DRV_ODT_34_3;
+
+		tsel_wr_select_ca_p = PHY_DRV_ODT_48;
  		tsel_wr_select_ca_n = PHY_DRV_ODT_48;
-		tsel_idle_select_n = PHY_DRV_ODT_HI_Z;
  	} else {
  		tsel_rd_select_p = PHY_DRV_ODT_240;
-		tsel_wr_select_dq_p = PHY_DRV_ODT_34_3;
-		tsel_wr_select_ca_p = PHY_DRV_ODT_34_3;
+		tsel_rd_select_n = PHY_DRV_ODT_240;
+
  		tsel_idle_select_p = PHY_DRV_ODT_240;
+		tsel_idle_select_n = PHY_DRV_ODT_240;
 

Group common ddr attributes like
- rank
- col
- bk
- bw
- dbw
- row_3_4
- cs0_row
- cs1_row
- ddrconfig

into a common cap_info structure for more code readability and extend if possible based on the new features.

Signed-off-by Jagan Teki <[email protected]>

---
  .../include/asm/arch-rockchip/sdram_rk3399.h  |  6 +-
  drivers/ram/rockchip/sdram_rk3399.c           | 73 ++++++++++---------
  2 files changed, 45 insertions(+), 34 deletions(-)

arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +5 -1

index c6a260bad8..683093d4ca 100644
@@ -71,7 +71,7 @@ struct rk3399_ddr_cic_regs {
  /* DENALI_CTL_274 */
  #define MEM_RST_VALID	1
 
-struct rk3399_sdram_channel {
+struct sdram_cap_info {
  	unsigned int rank;
  	/* dram column number, 0 means this channel is invalid */
  	unsigned int col;

@@ -89,6 +89,10 @@ struct rk3399_sdram_channel {
  	unsigned int cs0_row;
  	unsigned int cs1_row;
  	unsigned int ddrconfig;
+};
+
+struct rk3399_sdram_channel {
+	struct sdram_cap_info cap_info;
  	struct rk3399_msch_timings noc_timings;
  };
 

drivers/ram/rockchip/sdram_rk3399.c +39 -32

index 043b27737d..492b0975dd 100644
@@ -121,35 +121,36 @@ static void set_memory_map(const struct chan_info *chan, u32 channel,
  	u32 row;
 
  	/* Get row number from ddrconfig setting */
-	if (sdram_ch->ddrconfig < 2 || sdram_ch->ddrconfig == 4)
+	if (sdram_ch->cap_info.ddrconfig < 2 ||
+	    sdram_ch->cap_info.ddrconfig == 4)
  		row = 16;
-	else if (sdram_ch->ddrconfig == 3)
+	else if (sdram_ch->cap_info.ddrconfig == 3)
  		row = 14;
  	else
  		row = 15;
 
-	cs_map = (sdram_ch->rank > 1) ? 3 : 1;
-	reduc = (sdram_ch->bw == 2) ? 0 : 1;
+	cs_map = (sdram_ch->cap_info.rank > 1) ? 3 : 1;
+	reduc = (sdram_ch->cap_info.bw == 2) ? 0 : 1;
 
  	/* Set the dram configuration to ctrl */
-	clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->col));
+	clrsetbits_le32(&denali_ctl[191], 0xF, (12 - sdram_ch->cap_info.col));
  	clrsetbits_le32(&denali_ctl[190], (0x3 << 16) | (0x7 << 24),
-			((3 - sdram_ch->bk) << 16) |
+			((3 - sdram_ch->cap_info.bk) << 16) |
  			((16 - row) << 24));
 
  	clrsetbits_le32(&denali_ctl[196], 0x3 | (1 << 16),
  			cs_map | (reduc << 16));
 
  	/* PI_199 PI_COL_DIFF:RW:0:4 */
-	clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->col));
+	clrsetbits_le32(&denali_pi[199], 0xF, (12 - sdram_ch->cap_info.col));
 
  	/* PI_155 PI_ROW_DIFF:RW:24:3 PI_BANK_DIFF:RW:16:2 */
  	clrsetbits_le32(&denali_pi[155], (0x3 << 16) | (0x7 << 24),
-			((3 - sdram_ch->bk) << 16) |
+			((3 - sdram_ch->cap_info.bk) << 16) |
  			((16 - row) << 24));
  	/* PI_41 PI_CS_MAP:RW:24:4 */
  	clrsetbits_le32(&denali_pi[41], 0xf << 24, cs_map << 24);
-	if (sdram_ch->rank == 1 && params->base.dramtype == DDR3)
+	if (sdram_ch->cap_info.rank == 1 && params->base.dramtype == DDR3)
  		writel(0x2EC7FFFF, &denali_pi[34]);
  }
 

@@ -624,7 +625,7 @@ static int data_training_ca(const struct chan_info *chan, u32 channel,
  	u32 *denali_phy = chan->publ->denali_phy;
  	u32 i, tmp;
  	u32 obs_0, obs_1, obs_2, obs_err = 0;
-	u32 rank = params->ch[channel].rank;
+	u32 rank = params->ch[channel].cap_info.rank;
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);

@@ -678,7 +679,7 @@ static int data_training_wl(const struct chan_info *chan, u32 channel,
  	u32 *denali_phy = chan->publ->denali_phy;
  	u32 i, tmp;
  	u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
-	u32 rank = params->ch[channel].rank;
+	u32 rank = params->ch[channel].cap_info.rank;
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);

@@ -737,7 +738,7 @@ static int data_training_rg(const struct chan_info *chan, u32 channel,
  	u32 *denali_phy = chan->publ->denali_phy;
  	u32 i, tmp;
  	u32 obs_0, obs_1, obs_2, obs_3, obs_err = 0;
-	u32 rank = params->ch[channel].rank;
+	u32 rank = params->ch[channel].cap_info.rank;
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);

@@ -796,7 +797,7 @@ static int data_training_rl(const struct chan_info *chan, u32 channel,
  {
  	u32 *denali_pi = chan->pi->denali_pi;
  	u32 i, tmp;
-	u32 rank = params->ch[channel].rank;
+	u32 rank = params->ch[channel].cap_info.rank;
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);

@@ -841,7 +842,7 @@ static int data_training_wdql(const struct chan_info *chan, u32 channel,
  {
  	u32 *denali_pi = chan->pi->denali_pi;
  	u32 i, tmp;
-	u32 rank = params->ch[channel].rank;
+	u32 rank = params->ch[channel].cap_info.rank;
 
  	for (i = 0; i < rank; i++) {
  		select_per_cs_training_index(chan, i);

@@ -940,14 +941,14 @@ static void set_ddrconfig(const struct chan_info *chan,
  	unsigned int cs0_cap = 0;
  	unsigned int cs1_cap = 0;
 
-	cs0_cap = (1 << (params->ch[channel].cs0_row
-			+ params->ch[channel].col
-			+ params->ch[channel].bk
-			+ params->ch[channel].bw - 20));
-	if (params->ch[channel].rank > 1)
-		cs1_cap = cs0_cap >> (params->ch[channel].cs0_row
-				- params->ch[channel].cs1_row);
-	if (params->ch[channel].row_3_4) {
+	cs0_cap = (1 << (params->ch[channel].cap_info.cs0_row
+			+ params->ch[channel].cap_info.col
+			+ params->ch[channel].cap_info.bk
+			+ params->ch[channel].cap_info.bw - 20));
+	if (params->ch[channel].cap_info.rank > 1)
+		cs1_cap = cs0_cap >> (params->ch[channel].cap_info.cs0_row
+				- params->ch[channel].cap_info.cs1_row);
+	if (params->ch[channel].cap_info.row_3_4) {
  		cs0_cap = cs0_cap * 3 / 4;
  		cs1_cap = cs1_cap * 3 / 4;
  	}

@@ -973,20 +974,26 @@ static void dram_all_config(struct dram_info *dram,
  		struct rk3399_msch_regs *ddr_msch_regs;
  		const struct rk3399_msch_timings *noc_timing;
 
-		if (params->ch[channel].col == 0)
+		if (params->ch[channel].cap_info.col == 0)
  			continue;
  		idx++;
-		sys_reg |= info->row_3_4 << SYS_REG_ROW_3_4_SHIFT(channel);
+		sys_reg |= info->cap_info.row_3_4 <<
+			   SYS_REG_ROW_3_4_SHIFT(channel);
  		sys_reg |= 1 << SYS_REG_CHINFO_SHIFT(channel);
-		sys_reg |= (info->rank - 1) << SYS_REG_RANK_SHIFT(channel);
-		sys_reg |= (info->col - 9) << SYS_REG_COL_SHIFT(channel);
-		sys_reg |= info->bk == 3 ? 0 : 1 << SYS_REG_BK_SHIFT(channel);
-		sys_reg |= (info->cs0_row - 13) <<
+		sys_reg |= (info->cap_info.rank - 1) <<
+			   SYS_REG_RANK_SHIFT(channel);
+		sys_reg |= (info->cap_info.col - 9) <<
+			   SYS_REG_COL_SHIFT(channel);
+		sys_reg |= info->cap_info.bk == 3 ? 0 : 1 <<
+			   SYS_REG_BK_SHIFT(channel);
+		sys_reg |= (info->cap_info.cs0_row - 13) <<
  			    SYS_REG_CS0_ROW_SHIFT(channel);
-		sys_reg |= (info->cs1_row - 13) <<
+		sys_reg |= (info->cap_info.cs1_row - 13) <<
  			    SYS_REG_CS1_ROW_SHIFT(channel);
-		sys_reg |= (2 >> info->bw) << SYS_REG_BW_SHIFT(channel);
-		sys_reg |= (2 >> info->dbw) << SYS_REG_DBW_SHIFT(channel);
+		sys_reg |= (2 >> info->cap_info.bw) <<
+			   SYS_REG_BW_SHIFT(channel);
+		sys_reg |= (2 >> info->cap_info.dbw) <<
+			   SYS_REG_DBW_SHIFT(channel);
 
  		ddr_msch_regs = dram->chan[channel].msch;
  		noc_timing = &params->ch[channel].noc_timings;

@@ -1002,7 +1009,7 @@ static void dram_all_config(struct dram_info *dram,
  		       &ddr_msch_regs->ddrmode);
 
  		/* rank 1 memory clock disable (dfi_dram_clk_disable = 1) */
-		if (params->ch[channel].rank == 1)
+		if (params->ch[channel].cap_info.rank == 1)
  			setbits_le32(&dram->chan[channel].pctl->denali_ctl[276],
  				     1 << 17);
  	}

Most of the ddr parameters are common in rk3399_base_params structure and which would reuse it in another controller like px30 in future.

So, rename the structure from rk3399_base_params into sdram_base_params.

Signed-off-by Jagan Teki <[email protected]>

Signed-off-by YouMin Chen <[email protected]>

---
  arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 4 ++--
  1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +1 -1

index 683093d4ca..5614b94ecb 100644
@@ -96,7 +96,7 @@ struct rk3399_sdram_channel {
  	struct rk3399_msch_timings noc_timings;
  };
 
-struct rk3399_base_params {
+struct sdram_base_params {
  	unsigned int ddr_freq;
  	unsigned int dramtype;
  	unsigned int num_channels;

Move common sdram structures like sdram_cap_info, sdram_base_params into sdram_common header, this would help to reuse the same from another controllers like px30.

Signed-off-by Jagan Teki <[email protected]>

---
  .../include/asm/arch-rockchip/sdram_common.h  | 29 +++++++++++++++++++
  .../include/asm/arch-rockchip/sdram_rk3399.h  | 28 ------------------
  2 files changed, 29 insertions(+), 28 deletions(-)

arch/arm/include/asm/arch-rockchip/sdram_common.h +29 -0

index 671c318d50..82ce3d3fc9 100644
@@ -5,6 +5,35 @@
 
  #ifndef _ASM_ARCH_SDRAM_COMMON_H
  #define _ASM_ARCH_SDRAM_COMMON_H
+
+struct sdram_cap_info {
+	unsigned int rank;
+	/* dram column number, 0 means this channel is invalid */
+	unsigned int col;
+	/* dram bank number, 3:8bank, 2:4bank */
+	unsigned int bk;
+	/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
+	unsigned int bw;
+	/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
+	unsigned int dbw;
+	/*
+	 * row_3_4 = 1: 6Gb or 12Gb die
+	 * row_3_4 = 0: normal die, power of 2
+	 */
+	unsigned int row_3_4;
+	unsigned int cs0_row;
+	unsigned int cs1_row;
+	unsigned int ddrconfig;
+};
+
+struct sdram_base_params {
+	unsigned int ddr_freq;
+	unsigned int dramtype;
+	unsigned int num_channels;
+	unsigned int stride;
+	unsigned int odt;
+};
+
  /*
   * sys_reg bitfield struct
   * [31]		row_3_4_ch1

arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +0 -21

index 5614b94ecb..65c92cf744 100644
@@ -71,39 +71,11 @@ struct rk3399_ddr_cic_regs {
  /* DENALI_CTL_274 */
  #define MEM_RST_VALID	1
 
-struct sdram_cap_info {
-	unsigned int rank;
-	/* dram column number, 0 means this channel is invalid */
-	unsigned int col;
-	/* dram bank number, 3:8bank, 2:4bank */
-	unsigned int bk;
-	/* channel buswidth, 2:32bit, 1:16bit, 0:8bit */
-	unsigned int bw;
-	/* die buswidth, 2:32bit, 1:16bit, 0:8bit */
-	unsigned int dbw;
-	/*
-	 * row_3_4 = 1: 6Gb or 12Gb die
-	 * row_3_4 = 0: normal die, power of 2
-	 */
-	unsigned int row_3_4;
-	unsigned int cs0_row;
-	unsigned int cs1_row;
-	unsigned int ddrconfig;
-};
-
  struct rk3399_sdram_channel {
  	struct sdram_cap_info cap_info;
  	struct rk3399_msch_timings noc_timings;
  };
 
-struct sdram_base_params {

dramtype enum numbers as common across all dram controllers in rockchip, so move the eneum values in common header.

Signed-off-by Jagan Teki <[email protected]>

---
  arch/arm/include/asm/arch-rockchip/sdram.h        | 6 ------
  arch/arm/include/asm/arch-rockchip/sdram_common.h | 8 ++++++++
  arch/arm/include/asm/arch-rockchip/sdram_rk322x.h | 7 -------
  arch/arm/include/asm/arch-rockchip/sdram_rk3399.h | 8 --------
  4 files changed, 8 insertions(+), 21 deletions(-)

arch/arm/include/asm/arch-rockchip/sdram.h +0 -6

index bbe425deb9..9220763fa7 100644
@@ -8,12 +8,6 @@
  #ifndef _ASM_ARCH_RK3288_SDRAM_H__
  #define _ASM_ARCH_RK3288_SDRAM_H__
 
-enum {
-	DDR3 = 3,
-	LPDDR3 = 6,
-	UNUSED = 0xFF,
-};
-
  struct rk3288_sdram_channel {
  	/*
  	 * bit width in address, eg:

arch/arm/include/asm/arch-rockchip/sdram_common.h +8 -0

index 82ce3d3fc9..55abcdae77 100644
@@ -6,6 +6,14 @@
  #ifndef _ASM_ARCH_SDRAM_COMMON_H
  #define _ASM_ARCH_SDRAM_COMMON_H
 
+enum {
+	DDR3 = 0x3,
+	LPDDR2 = 0x5,
+	LPDDR3 = 0x6,
+	LPDDR4 = 0x7,
+	UNUSED = 0xFF
+};
+
  struct sdram_cap_info {
  	unsigned int rank;
  	/* dram column number, 0 means this channel is invalid */

arch/arm/include/asm/arch-rockchip/sdram_rk322x.h +0 -7

index d0091a7aaf..336c5d7e8c 100644
@@ -7,13 +7,6 @@
 
  #include <common.h>
 
-enum {
-	DDR3		= 3,
-	LPDDR2		= 5,
-	LPDDR3		= 6,
-	UNUSED		= 0xFF,
-};
-
  struct rk322x_sdram_channel {
  	/*
  	 * bit width in address, eg:

arch/arm/include/asm/arch-rockchip/sdram_rk3399.h +0 -1

index 65c92cf744..471702f935 100644
@@ -6,14 +6,6 @@
  #ifndef _ASM_ARCH_SDRAM_RK3399_H
  #define _ASM_ARCH_SDRAM_RK3399_H
 
-enum {