memory: tegra: Introduce Tegra30 EMC driver
Subsystems (5)
v8 cover memory: tegra: Introduce Tegra30 EMC driver
Hello,
This series introduces driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change. The driver was tested using the ACTMON devfreq driver that performs memory frequency scaling based on memory-usage load.
Changelog:
v8: - Added two new patches:
memory: tegra20-emc: Increase handshake timeout
memory: tegra20-emc: wait_for_completion_timeout() doesn't return error
Turned out that memory-clk handshake may take much more time under some circumstances. The second patch is a minor cleanup. The same changes are also applied to the Terga30 EMC driver addition-patch.
The pattern-properties of YAML bindings gained "type: object", for consistency.
v7: - Addressed review comments that were made by Rob Herring to v6 by
removing old Terga30 Memory Controller binding once it's converted to YAML, by using explicit patterns for the sub-nodes and specifying min/max clock rates in the YAML.
- Two patches that were added in v6 are removed from the series:
clk: tegra20: emc: Add tegra20_clk_emc_on_pllp()
ARM: tegra30: cpuidle: Don't enter LP2 on CPU0 when EMC runs off PLLP
Because the problem with the PLLP is resolved now, turned out it was a bug in the CPU-suspend code.
- The "Introduce Tegra30 EMC driver" patch got a fix for the "Same Freq" bit typo, it's a bit 27 and not 16.
v6: - Tegra124 Memory Controller binding factored out into standalone
binding because it requires to specify MC_EMEM_ARB_MISC1 for EMEM programming, which is not required for Tegra30. This makes the upstream MC registers specification to match downstream exactly, easing porting of boards memory timings configuration to upstream.
- Tegra30/124 Memory Controller binding converted to YAML.
- Tegra30 External Memory Controller binding now is in YAML format.
- Added workaround for hanging during LP2 when EMC runs off PLLP on Tegra30 in this new patches:
clk: tegra20: emc: Add tegra20_clk_emc_on_pllp()
ARM: tegra30: cpuidle: Don't enter LP2 on CPU0 when EMC runs off PLLP
- Added info message to the Tegra20/30 EMC drivers, telling about RAM code and a number of available timings:
memory: tegra20-emc: Print a brief info message about the timings
v5: - Addressed review comments that were made by Thierry Reding to v4 by
adding appropriate copyrights to the source code headers and making Tegra30 EMC driver to use common Tegra20 CLK API directly instead of having a dummy-proxy functions specifically for Tegra30.
- Addressed review comments that were made by Stephen Boyd to v4 by rewording commit message of the "Add custom EMC clock implementation" patch and adding clarifying comment (to that patch as well) which tells why EMC is a critical clock.
- Added suspend-resume to Tegra30 EMC driver to error out if EMC driver is in a "bad state" as it will likely cause a hang on entering suspend.
- Dropped patch "tegra20-emc: Replace clk_get_sys with devm_clk_get" because the replaced clocks are actually should be removed altogether in the "Drop setting EMC rate to max on probe" patch and that was missed by an accident.
- Added "tegra20-emc: Pre-configure debug register" patch which ensures that inappropriate HW debug features are disabled at a probe time. The same change is also made in the "Introduce Tegra30 EMC driver" patch.
- Added ACKs to the patches from Peter De Schrijver that he gave to v4 since all of the v5 changes are actually very minor.
v4: - Addressed review comments that were made by Peter De Schrijver to v3
by adding fence_udelay() after writes in the "Add custom EMC clock implementation" patch.
- Added two new minor patches:
memory: tegra: Ensure timing control debug features are disabled
memory: tegra: Consolidate registers definition into one place
The first one is needed to ensure that EMC driver will work properly regardless of hardware configuration left after boot. The second patch is just a minor code cleanup.
- The "Introduce Tegra30 EMC driver" got also few very minor changes. Now every possible error case is handled, nothing is ignored. The EMC_DBG register is explicitly initialized during probe to be on the safe side.
v3: - Addressed review comments that were made by Stephen Boyd to v2 by
adding explicit typing for the callback variable, by including "clk-provider.h" directly in the code and by dropping __clk_lookup usage where possible.
- Added more patches into this series:
memory: tegra20-emc: Drop setting EMC rate to max on probe
memory: tegra20-emc: Adapt for clock driver changes
memory: tegra20-emc: Include io.h instead of iopoll.h
memory: tegra20-emc: Replace clk_get_sys with devm_clk_get
Initially I was going to include these patches into other patchset, but changed my mind after rearranging things a tad. The "Adapt for clock driver changes" patch is directly related to the clock changes done in the first patch of this series, the rest are minor cleanups that are fine to include here as well.
- Added some more words to the commit message of "Add binding for NVIDIA Tegra30 External Memory Controller" patch, clarifying why common DDR timing device-tree form isn't suitable for Tegra30.
- The Tegra30 EMC driver now explicitly selects the registers access mode (EMC_DBG mux), not relying on the setting left from bootloader.
v2: - Added support for changing MC clock diver configuration based on
Memory Controller (MC) configuration which is part of the memory timing.
- Merged the "Add custom EMC clock implementation" patch into this series because the "Introduce Tegra30 EMC driver" patch directly depends on it. Please note that Tegra20 EMC driver will need to be adapted for the clock changes as well, I'll send out the Tegra20 patches after this series will be applied because of some other dependencies (devfreq) and because the temporary breakage won't be critical (driver will just error out on probe).
- EMC driver now performs MC configuration validation by checking that the number of MC / EMC timings matches and that the timings rate is the same.
- EMC driver now supports timings that want to change the MC clock configuration.
- Other minor prettifying changes of the code.
Dmitry Osipenko (15):
clk: tegra20/30: Add custom EMC clock implementation
memory: tegra20-emc: Drop setting EMC rate to max on probe
memory: tegra20-emc: Adapt for clock driver changes
memory: tegra20-emc: Include io.h instead of iopoll.h
memory: tegra20-emc: Pre-configure debug register
memory: tegra20-emc: Print a brief info message about the timings
memory: tegra20-emc: Increase handshake timeout
memory: tegra20-emc: wait_for_completion_timeout() doesn't return
error
dt-bindings: memory: tegra30: Convert to Tegra124 YAML
dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller
dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory
Controller
memory: tegra: Introduce Tegra30 EMC driver
memory: tegra: Ensure timing control debug features are disabled
memory: tegra: Consolidate registers definition into common header
ARM: dts: tegra30: Add External Memory Controller node
.../nvidia,tegra124-mc.yaml | 156 +++ .../nvidia,tegra30-emc.yaml | 341 +++++ .../memory-controllers/nvidia,tegra30-mc.txt | 123 -- .../memory-controllers/nvidia,tegra30-mc.yaml | 173 +++ arch/arm/boot/dts/tegra30.dtsi | 9 + drivers/clk/tegra/Makefile | 2 + drivers/clk/tegra/clk-tegra20-emc.c | 293 ++++ drivers/clk/tegra/clk-tegra20.c | 55 +- drivers/clk/tegra/clk-tegra30.c | 38 +- drivers/clk/tegra/clk.h | 3 + drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/mc.c | 42 +- drivers/memory/tegra/mc.h | 74 +- drivers/memory/tegra/tegra124.c | 20 - drivers/memory/tegra/tegra20-emc.c | 134 +- drivers/memory/tegra/tegra30-emc.c | 1230 +++++++++++++++++ drivers/memory/tegra/tegra30.c | 23 + include/linux/clk/tegra.h | 11 + include/soc/tegra/mc.h | 2 +- 20 files changed, 2427 insertions(+), 313 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml create mode 100644 drivers/clk/tegra/clk-tegra20-emc.c create mode 100644 drivers/memory/tegra/tegra30-emc.c
Signature · 1 line
2.22.0
PATCH v8 1/15 clk: tegra20/30: Add custom EMC clock implementation
A proper External Memory Controller clock rounding and parent selection functionality is required by the EMC drivers, it is not available using the generic clock implementation because only the Memory Controller driver is aware of what clock rates are actually available for a particular device. EMC drivers will have to register a Tegra-specific CLK-API callback which will perform rounding of a requested rate. EMC clock users won't be able to request EMC clock by getting -EPROBE_DEFER until EMC driver is probed and the callback is set up.
The functionality is somewhat similar to the clk-emc.c which serves Tegra124+ SoCs. The later HW generations support more parent clock sources and the HW configuration / integration with the EMC drivers differs a tad from the older gens, hence it's not really worth to try to squash everything into a single source file.
--- drivers/clk/tegra/Makefile | 2 + drivers/clk/tegra/clk-tegra20-emc.c | 293 ++++++++++++++++++++++++++++ drivers/clk/tegra/clk-tegra20.c | 55 ++---- drivers/clk/tegra/clk-tegra30.c | 38 ++-- drivers/clk/tegra/clk.h | 3 + include/linux/clk/tegra.h | 11 ++ 6 files changed, 350 insertions(+), 52 deletions(-) create mode 100644 drivers/clk/tegra/clk-tegra20-emc.c
drivers/clk/tegra/Makefile +2 -0
@@ -17,7 +17,9 @@ obj-y += clk-tegra-fixed.o obj-y += clk-tegra-super-gen4.o obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o +obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20-emc.o obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra30.o +obj-$(CONFIG_ARCH_TEGRA_3x_SOC) += clk-tegra20-emc.o obj-$(CONFIG_ARCH_TEGRA_114_SOC) += clk-tegra114.o obj-$(CONFIG_ARCH_TEGRA_124_SOC) += clk-tegra124.o obj-$(CONFIG_TEGRA_CLK_DFLL) += clk-tegra124-dfll-fcpu.o
drivers/clk/tegra/clk-tegra20-emc.c new file +293 -0
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drivers/clk/tegra/clk-tegra20.c +14 -41
96 lines not on this page · raw message
drivers/clk/tegra/clk-tegra30.c +27 -11
@@ -151,7 +151,6 @@ static unsigned long input_freq;static DEFINE_SPINLOCK (cml_lock);static DEFINE_SPINLOCK (pll_d_lock); -static DEFINE_SPINLOCK (emc_lock);#define TEGRA_INIT_DATA_MUX (_name, _parents, _offset, \ _clk_num, _gate_flags, _clk_id) \
@@ -808,7 +807,7 @@ static struct tegra_clk tegra30_clks[tegra_clk_max] __initdata = { [tegra_clk_pll_a] = { .dt_id = TEGRA30_CLK_PLL_A, .present = true }, [tegra_clk_pll_a_out0] = { .dt_id = TEGRA30_CLK_PLL_A_OUT0, .present = true }, [tegra_clk_cec] = { .dt_id = TEGRA30_CLK_CEC, .present = true }, - [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = true }, + [tegra_clk_emc] = { .dt_id = TEGRA30_CLK_EMC, .present = false }, };static const char *pll_e_parents[] = {"pll_ref" ,"pll_p" };
@@ -995,7 +994,6 @@ static void __init tegra30_super_clk_init(void)static const char *mux_pllacp_clkm[] = {"pll_a_out0" ,"unused" ,"pll_p" ,"clk_m" };static const char *mux_pllpcm_clkm[] = {"pll_p" ,"pll_c" ,"pll_m" ,"clk_m" }; -static const char *mux_pllmcp_clkm[] = {"pll_m" ,"pll_c" ,"pll_p" ,"clk_m" };static const char *spdif_out_parents[] = {"pll_a_out0" ,"spdif_2x" ,"pll_p" ,"clk_m" };static const char *mux_pllmcpa[] = {"pll_m" ,"pll_c" ,"pll_p" ,"pll_a_out0" };
@@ -1044,14 +1042,12 @@ static void __init tegra30_periph_clk_init(void) clks[TEGRA30_CLK_AFI ] = clk;/* emc */ - clk =clk_register_mux (NULL ,"emc_mux" , mux_pllmcp_clkm, -ARRAY_SIZE (mux_pllmcp_clkm), -CLK_SET_RATE_NO_REPARENT , - clk_base +CLK_SOURCE_EMC , -30 ,2 ,0 , &emc_lock); + clk =tegra20_clk_register_emc (clk_base +CLK_SOURCE_EMC , true); + + clks[TEGRA30_CLK_EMC ] = clk; - clk =tegra_clk_register_mc ("mc" ,"emc_mux" , clk_base +CLK_SOURCE_EMC , - &emc_lock); + clk =tegra_clk_register_mc ("mc" ,"emc" , clk_base +CLK_SOURCE_EMC , +NULL ); clks[TEGRA30_CLK_MC ] = clk;/* cml0 */
@@ -1302,6 +1298,26 @@ static struct tegra_audio_clk_info tegra30_audio_plls[] = { { "pll_a", &pll_a_params, tegra_clk_pll_a, "pll_p_out1" }, }; +static struct clk *tegra30_clk_src_onecell_get (struct of_phandle_args *clkspec, +void *data) +{ +struct clk_hw *hw; +struct clk *clk; + + clk =of_clk_src_onecell_get (clkspec, data); +if (IS_ERR (clk)) +return clk; + + hw =__clk_get_hw (clk); + +if (clkspec->args[0 ] ==TEGRA30_CLK_EMC ) { +if (!tegra20_clk_emc_driver_available (hw)) +return ERR_PTR (-EPROBE_DEFER ); + } + +return clk; +} +static void __init tegra30_clock_init (struct device_node *np) {struct device_node *node;
@@ -1345,7 +1361,7 @@ static void __init tegra30_clock_init(struct device_node *np)tegra_init_dup_clks (tegra_clk_duplicates, clks,TEGRA30_CLK_CLK_MAX ); -tegra_add_of_provider (np, of_clk_src_onecell_get); +tegra_add_of_provider (np, tegra30_clk_src_onecell_get);tegra_register_devclks (devclks,ARRAY_SIZE (devclks)); tegra_clk_apply_init_table = tegra30_clock_apply_init_table;
drivers/clk/tegra/clk.h +3 -0
@@ -842,4 +842,7 @@ int div_frac_get(unsigned long rate, unsigned parent_rate, u8 width,udelay (delay); \ } while (0) +bool tegra20_clk_emc_driver_available(struct clk_hw *emc_hw); +struct clk *tegra20_clk_register_emc (void __iomem *ioaddr,bool low_jitter); +#endif /* TEGRA_CLK_H */
include/linux/clk/tegra.h +11 -0
@@ -132,4 +132,15 @@ extern void tegra210_put_utmipll_in_iddq(void);extern void tegra210_put_utmipll_out_iddq (void );extern int tegra210_clk_handle_mbist_war (unsigned int id); +struct clk ; + +typedef long (tegra20_clk_emc_round_cb )(unsigned long rate, +unsigned long min_rate, +unsigned long max_rate, +void *arg); + +void tegra20_clk_set_emc_round_callback (tegra20_clk_emc_round_cb *round_cb, +void *cb_arg); +int tegra20_clk_prepare_emc_mc_same_freq (struct clk *emc_clk,bool same); +#endif /* __LINUX_CLK_TEGRA_H_ */
Signature · 1 line
2.22.0
PATCH v8 2/15 memory: tegra20-emc: Drop setting EMC rate to max on probe
In reply to Dmitry OsipenkoThe memory frequency scaling will be managed by tegra20-devfreq driver and PM QoS once all the prerequisite patches will get upstreamed. The parent clock is now managed by the clock driver and we also should assume that PLLM rate can't be changed on some devices (Galaxy Tab 10.1 for example). Altogether there is no point in touching of clock's rate from the EMC driver.
--- drivers/memory/tegra/tegra20-emc.c | 78 +----------------------------- 1 file changed, 1 insertion(+), 77 deletions(-)
drivers/memory/tegra/tegra20-emc.c +1 -77
@@ -137,9 +137,6 @@ struct tegra_emc {struct device *dev;struct completion clk_handshake_complete;struct notifier_block clk_nb; -struct clk *backup_clk; -struct clk *emc_mux; -struct clk *pll_m;struct clk *clk;void __iomem *regs;
@@ -424,41 +421,6 @@ static int emc_setup_hw(struct tegra_emc *emc)return 0 ; } -static int emc_init (struct tegra_emc *emc,unsigned long rate) -{ -int err; - - err =clk_set_parent (emc->emc_mux, emc->backup_clk); -if (err) { -dev_err (emc->dev, -"failed to reparent to backup source: %d\n" , err); -return err; - } - - err =clk_set_rate (emc->pll_m, rate); -if (err) { -dev_err (emc->dev, -"failed to change pll_m rate: %d\n" , err); -return err; - } - - err =clk_set_parent (emc->emc_mux, emc->pll_m); -if (err) { -dev_err (emc->dev, -"failed to reparent to pll_m: %d\n" , err); -return err; - } - - err =clk_set_rate (emc->clk, rate); -if (err) { -dev_err (emc->dev, -"failed to change emc rate: %d\n" , err); -return err; - } - -return 0 ; -} -static int tegra_emc_probe (struct platform_device *pdev) {struct device_node *np;
@@ -522,52 +484,14 @@ static int tegra_emc_probe(struct platform_device *pdev)return err; } - emc->pll_m =clk_get_sys (NULL ,"pll_m" ); -if (IS_ERR (emc->pll_m)) { - err =PTR_ERR (emc->pll_m); -dev_err (&pdev->dev,"failed to get pll_m clock: %d\n" , err); -return err; - } - - emc->backup_clk =clk_get_sys (NULL ,"pll_p" ); -if (IS_ERR (emc->backup_clk)) { - err =PTR_ERR (emc->backup_clk); -dev_err (&pdev->dev,"failed to get pll_p clock: %d\n" , err); - goto put_pll_m; - } - - emc->emc_mux =clk_get_parent (emc->clk); -if (IS_ERR (emc->emc_mux)) { - err =PTR_ERR (emc->emc_mux); -dev_err (&pdev->dev,"failed to get emc_mux clock: %d\n" , err); - goto put_backup; - } - err =clk_notifier_register (emc->clk, &emc->clk_nb);if (err) {dev_err (&pdev->dev,"failed to register clk notifier: %d\n" , err); - goto put_backup; - } - -/* set DRAM clock rate to maximum */ - err =emc_init (emc, emc->timings[emc->num_timings -1 ].rate); -if (err) { -dev_err (&pdev->dev,"failed to initialize EMC clock rate: %d\n" , - err); - goto unreg_notifier; +return err; }return 0 ; - -unreg_notifier: -clk_notifier_unregister (emc->clk, &emc->clk_nb); -put_backup: -clk_put (emc->backup_clk); -put_pll_m: -clk_put (emc->pll_m); - -return err; }static const struct of_device_id tegra_emc_of_match[] = {
Signature · 1 line
2.22.0
PATCH v8 3/15 memory: tegra20-emc: Adapt for clock driver changes
In reply to Dmitry OsipenkoNow Terga20 and Tegra30 EMC drivers should provide clock-rounding functionality using the new Tegra-CLK driver API.
--- drivers/memory/tegra/tegra20-emc.c | 50 ++++++++++++++++++++++++++++-- 1 file changed, 48 insertions(+), 2 deletions(-)
drivers/memory/tegra/tegra20-emc.c +48 -2
@@ -6,6 +6,7 @@*/ #include <linux/clk.h> +#include <linux/clk/tegra.h> #include <linux/completion.h> #include <linux/err.h> #include <linux/interrupt.h>
@@ -421,6 +422,44 @@ static int emc_setup_hw(struct tegra_emc *emc)return 0 ; } +static long emc_round_rate (unsigned long rate, +unsigned long min_rate, +unsigned long max_rate, +void *arg) +{ +struct emc_timing *timing =NULL ; +struct tegra_emc *emc = arg; +unsigned int i; + + min_rate =min (min_rate, emc->timings[emc->num_timings -1 ].rate); + +for (i =0 ; i < emc->num_timings; i++) { +if (emc->timings[i].rate < rate && i != emc->num_timings -1 ) +continue ; + +if (emc->timings[i].rate > max_rate) { + i =max (i,1u ) -1 ; + +if (emc->timings[i].rate < min_rate) +break ; + } + +if (emc->timings[i].rate < min_rate) +continue ; + + timing = &emc->timings[i]; +break ; + } + +if (!timing) { +dev_err (emc->dev,"no timing for rate %lu min %lu max %lu\n" , + rate, min_rate, max_rate); +return -EINVAL ; + } + +return timing->rate; +} +static int tegra_emc_probe (struct platform_device *pdev) {struct device_node *np;
@@ -477,21 +516,28 @@ static int tegra_emc_probe(struct platform_device *pdev)return err; } +tegra20_clk_set_emc_round_callback (emc_round_rate, emc); + emc->clk =devm_clk_get (&pdev->dev,"emc" );if (IS_ERR (emc->clk)) { err =PTR_ERR (emc->clk);dev_err (&pdev->dev,"failed to get emc clock: %d\n" , err); -return err; + goto unset_cb; } err =clk_notifier_register (emc->clk, &emc->clk_nb);if (err) {dev_err (&pdev->dev,"failed to register clk notifier: %d\n" , err); -return err; + goto unset_cb; }return 0 ; + +unset_cb: +tegra20_clk_set_emc_round_callback (NULL ,NULL ); + +return err; }static const struct of_device_id tegra_emc_of_match[] = {
Signature · 1 line
2.22.0
PATCH v8 4/15 memory: tegra20-emc: Include io.h instead of iopoll.h
In reply to Dmitry OsipenkoThe register polling code was gone, but the included header change was missed. Fix it up for consistency.
--- drivers/memory/tegra/tegra20-emc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/memory/tegra/tegra20-emc.c +1 -1
@@ -10,7 +10,7 @@#include <linux/completion.h> #include <linux/err.h> #include <linux/interrupt.h> -#include <linux/iopoll.h> +#include <linux/io.h> #include <linux/kernel.h> #include <linux/module.h> #include <linux/of.h>
Signature · 1 line
2.22.0
PATCH v8 5/15 memory: tegra20-emc: Pre-configure debug register
In reply to Dmitry OsipenkoThe driver expects certain debug features to be disabled in order to work properly. Let's disable them explicitly for consistency and to not rely on a boot state.
--- drivers/memory/tegra/tegra20-emc.c | 17 ++++++++++++++++- 1 file changed, 16 insertions(+), 1 deletion(-)
drivers/memory/tegra/tegra20-emc.c +16 -1
@@ -22,6 +22,7 @@#define EMC_INTSTATUS 0x000#define EMC_INTMASK 0x004 +#define EMC_DBG 0x008#define EMC_TIMING_CONTROL 0x028#define EMC_RC 0x02c#define EMC_RFC 0x030
@@ -80,6 +81,12 @@#define EMC_REFRESH_OVERFLOW_INT BIT(3)#define EMC_CLKCHANGE_COMPLETE_INT BIT(4) +#define EMC_DBG_READ_MUX_ASSEMBLY BIT(0) +#define EMC_DBG_WRITE_MUX_ACTIVE BIT(1) +#define EMC_DBG_FORCE_UPDATE BIT(2) +#define EMC_DBG_READ_DQM_CTRL BIT(9) +#define EMC_DBG_CFG_PRIORITY BIT(24) +static const u16 emc_timing_registers[] = {EMC_RC ,EMC_RFC ,
@@ -396,7 +403,7 @@ tegra_emc_find_node_by_ram_code(struct device *dev)static int emc_setup_hw (struct tegra_emc *emc) {u32 intmask =EMC_REFRESH_OVERFLOW_INT |EMC_CLKCHANGE_COMPLETE_INT ; -u32 emc_cfg; +u32 emc_cfg, emc_dbg; emc_cfg =readl_relaxed (emc->regs +EMC_CFG_2 );
@@ -419,6 +426,14 @@ static int emc_setup_hw(struct tegra_emc *emc)writel_relaxed (intmask, emc->regs +EMC_INTMASK );writel_relaxed (intmask, emc->regs +EMC_INTSTATUS ); +/* ensure that unwanted debug features are disabled */ + emc_dbg =readl_relaxed (emc->regs +EMC_DBG ); + emc_dbg |=EMC_DBG_CFG_PRIORITY ; + emc_dbg &= ~EMC_DBG_READ_MUX_ASSEMBLY ; + emc_dbg &= ~EMC_DBG_WRITE_MUX_ACTIVE ; + emc_dbg &= ~EMC_DBG_FORCE_UPDATE ; +writel_relaxed (emc_dbg, emc->regs +EMC_DBG ); +return 0 ; }
Signature · 1 line
2.22.0
PATCH v8 6/15 memory: tegra20-emc: Print a brief info message about the timings
In reply to Dmitry OsipenkoDuring boot print how many memory timings got the driver and what's the RAM code. This is a very useful information when something is wrong with boards memory timing.
--- drivers/memory/tegra/tegra20-emc.c | 7 +++++++ 1 file changed, 7 insertions(+)
drivers/memory/tegra/tegra20-emc.c +7 -0
@@ -368,6 +368,13 @@ static int tegra_emc_load_timings_from_dt(struct tegra_emc *emc,sort (emc->timings, emc->num_timings,sizeof (*timing), cmp_timings,NULL ); +dev_info (emc->dev, +"got %u timings for RAM code %u (min %luMHz max %luMHz)\n" , + emc->num_timings, +tegra_read_ram_code (), + emc->timings[0 ].rate /1000000 , + emc->timings[emc->num_timings -1 ].rate /1000000 ); +return 0 ; }
Signature · 1 line
2.22.0
PATCH v8 7/15 memory: tegra20-emc: Increase handshake timeout
In reply to Dmitry OsipenkoTurned out that it could take over a millisecond under some circumstances, like running on a very low CPU/memory frequency. TRM says that handshake happens when there is a "safe" moment, but not explains exactly what that moment is. Apparently at least memory should be idling and thus the low frequency should be a reasonable cause for a longer handshake delay.
--- drivers/memory/tegra/tegra20-emc.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/memory/tegra/tegra20-emc.c +1 -1
@@ -236,7 +236,7 @@ static int emc_complete_timing_change(struct tegra_emc *emc, bool flush) } timeout =wait_for_completion_timeout (&emc->clk_handshake_complete, -usecs_to_jiffies (100 )); +msecs_to_jiffies (100 ));if (timeout ==0 ) {dev_err (emc->dev,"EMC-CAR handshake failed\n" );return -EIO ;
Signature · 1 line
2.22.0
PATCH v8 8/15 memory: tegra20-emc: wait_for_completion_timeout() doesn't return error
In reply to Dmitry OsipenkoThe "interruptible" variant may error out, the "uninterruptible" not.
--- drivers/memory/tegra/tegra20-emc.c | 6 +----- 1 file changed, 1 insertion(+), 5 deletions(-)
drivers/memory/tegra/tegra20-emc.c +1 -5
@@ -224,7 +224,7 @@ static int emc_prepare_timing_change(struct tegra_emc *emc, unsigned long rate)static int emc_complete_timing_change (struct tegra_emc *emc,bool flush) { -long timeout; +unsigned long timeout;dev_dbg (emc->dev,"%s: flush %d\n" , __func__, flush);
@@ -240,10 +240,6 @@ static int emc_complete_timing_change(struct tegra_emc *emc, bool flush)if (timeout ==0 ) {dev_err (emc->dev,"EMC-CAR handshake failed\n" );return -EIO ; - }else if (timeout <0 ) { -dev_err (emc->dev,"failed to wait for EMC-CAR handshake: %ld\n" , - timeout); -return timeout; }return 0 ;
Signature · 1 line
2.22.0
PATCH v8 9/15 dt-bindings: memory: tegra30: Convert to Tegra124 YAML
In reply to Dmitry OsipenkoThe Tegra30 binding will actually differ from the Tegra124 a tad, in particular the EMEM configuration description. Hence rename the binding to Tegra124 during of the conversion to YAML.
--- .../nvidia,tegra124-mc.yaml | 156 ++++++++++++++++++ .../memory-controllers/nvidia,tegra30-mc.txt | 123 -------------- 2 files changed, 156 insertions(+), 123 deletions(-) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml delete mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra124-mc.yaml new file +156 -0
@@ -0,0 +1,156 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra124-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra124 SoC Memory Controller + +maintainers: + - Jon Hunter <[email protected]> + - Thierry Reding <[email protected]> + +description: | + Tegra124 SoC features a hybrid 2x32-bit / 1x64-bit memory controller. + These are interleaved to provide high performance with the load shared across + two memory channels. The Tegra124 Memory Controller handles memory requests + from internal clients and arbitrates among them to allocate memory bandwidth + for DDR3L and LPDDR3 SDRAMs. + +properties: + compatible: + const: nvidia,tegra124-mc + + reg: + maxItems: 1 + description: + Physical base address. + + clocks: + maxItems: 1 + description: + Memory Controller clock. + + clock-names: + items: + - const: mc + + interrupts: + maxItems: 1 + description: + Memory Controller interrupt. + + "#reset-cells": + const: 1 + + "#iommu-cells": + const: 1 + +patternProperties: + "^emc-timings-[0-9]+$": + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value of RAM_CODE this timing set is used for. + + patternProperties: + "^timing-[0-9]+$": + properties: + clock-frequency: + description: + Memory clock rate in Hz. + minimum: 1000000 + maximum: 1066000000 + + nvidia,emem-configuration: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Values to be written to the EMEM register block. See section + "15.6.1 MC Registers" in the TRM. + items: + - description: MC_EMEM_ARB_CFG + - description: MC_EMEM_ARB_OUTSTANDING_REQ + - description: MC_EMEM_ARB_TIMING_RCD + - description: MC_EMEM_ARB_TIMING_RP + - description: MC_EMEM_ARB_TIMING_RC + - description: MC_EMEM_ARB_TIMING_RAS + - description: MC_EMEM_ARB_TIMING_FAW + - description: MC_EMEM_ARB_TIMING_RRD + - description: MC_EMEM_ARB_TIMING_RAP2PRE + - description: MC_EMEM_ARB_TIMING_WAP2PRE + - description: MC_EMEM_ARB_TIMING_R2R + - description: MC_EMEM_ARB_TIMING_W2W + - description: MC_EMEM_ARB_TIMING_R2W + - description: MC_EMEM_ARB_TIMING_W2R + - description: MC_EMEM_ARB_DA_TURNS + - description: MC_EMEM_ARB_DA_COVERS + - description: MC_EMEM_ARB_MISC0 + - description: MC_EMEM_ARB_MISC1 + - description: MC_EMEM_ARB_RING1_THROTTLE + + required: + - clock-frequency + - nvidia,emem-configuration + + additionalProperties: false + + required: + - nvidia,ram-code + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#reset-cells" + - "#iommu-cells" + +additionalProperties: false + +examples: + - | + memory-controller@70019000 { + compatible = "nvidia,tegra124-mc"; + reg = <0x0 0x70019000 0x0 0x1000>; + clocks = <&tegra_car 32>; + clock-names = "mc"; + + interrupts = <0 77 4>; + + #iommu-cells = <1>; + #reset-cells = <1>; + + emc-timings-3 { + nvidia,ram-code = <3>; + + timing-12750000 { + clock-frequency = <12750000>; + + nvidia,emem-configuration = < + 0x40040001 /* MC_EMEM_ARB_CFG */ + 0x8000000a /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RC */ + 0x00000000 /* MC_EMEM_ARB_TIMING_RAS */ + 0x00000002 /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000002 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x00000008 /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000003 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000006 /* MC_EMEM_ARB_TIMING_W2R */ + 0x06030203 /* MC_EMEM_ARB_DA_TURNS */ + 0x000a0402 /* MC_EMEM_ARB_DA_COVERS */ + 0x77e30303 /* MC_EMEM_ARB_MISC0 */ + 0x70000f03 /* MC_EMEM_ARB_MISC1 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + };
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.txt deleted +0 -123
123 lines not on this page · raw message
Signature · 1 line
2.22.0
PATCH v8 10/15 dt-bindings: memory: Add binding for NVIDIA Tegra30 Memory Controller
In reply to Dmitry OsipenkoAdd binding for the NVIDIA Tegra30 SoC Memory Controller.
--- .../memory-controllers/nvidia,tegra30-mc.yaml | 173 ++++++++++++++++++ 1 file changed, 173 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-mc.yaml new file +173 -0
@@ -0,0 +1,173 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-mc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra30 SoC Memory Controller + +maintainers: + - Dmitry Osipenko <[email protected]> + - Jon Hunter <[email protected]> + - Thierry Reding <[email protected]> + +description: | + Tegra30 Memory Controller architecturally consists of the following parts: + + Arbitration Domains, which can handle a single request or response per + clock from a group of clients. Typically, a system has a single Arbitration + Domain, but an implementation may divide the client space into multiple + Arbitration Domains to increase the effective system bandwidth. + + Protocol Arbiter, which manage a related pool of memory devices. A system + may have a single Protocol Arbiter or multiple Protocol Arbiters. + + Memory Crossbar, which routes request and responses between Arbitration + Domains and Protocol Arbiters. In the simplest version of the system, the + Memory Crossbar is just a pass through between a single Arbitration Domain + and a single Protocol Arbiter. + + Global Resources, which include things like configuration registers which + are shared across the Memory Subsystem. + + The Tegra30 Memory Controller handles memory requests from internal clients + and arbitrates among them to allocate memory bandwidth for DDR3L and LPDDR2 + SDRAMs. + +properties: + compatible: + const: nvidia,tegra30-mc + + reg: + maxItems: 1 + description: + Physical base address. + + clocks: + maxItems: 1 + description: + Memory Controller clock. + + clock-names: + items: + - const: mc + + interrupts: + maxItems: 1 + description: + Memory Controller interrupt. + + "#reset-cells": + const: 1 + + "#iommu-cells": + const: 1 + +patternProperties: + "^emc-timings-[0-9]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value of RAM_CODE this timing set is used for. + + patternProperties: + "^timing-[0-9]+$": + type: object + properties: + clock-frequency: + description: + Memory clock rate in Hz. + minimum: 1000000 + maximum: 900000000 + + nvidia,emem-configuration: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: | + Values to be written to the EMEM register block. See section + "18.13.1 MC Registers" in the TRM. + items: + - description: MC_EMEM_ARB_CFG + - description: MC_EMEM_ARB_OUTSTANDING_REQ + - description: MC_EMEM_ARB_TIMING_RCD + - description: MC_EMEM_ARB_TIMING_RP + - description: MC_EMEM_ARB_TIMING_RC + - description: MC_EMEM_ARB_TIMING_RAS + - description: MC_EMEM_ARB_TIMING_FAW + - description: MC_EMEM_ARB_TIMING_RRD + - description: MC_EMEM_ARB_TIMING_RAP2PRE + - description: MC_EMEM_ARB_TIMING_WAP2PRE + - description: MC_EMEM_ARB_TIMING_R2R + - description: MC_EMEM_ARB_TIMING_W2W + - description: MC_EMEM_ARB_TIMING_R2W + - description: MC_EMEM_ARB_TIMING_W2R + - description: MC_EMEM_ARB_DA_TURNS + - description: MC_EMEM_ARB_DA_COVERS + - description: MC_EMEM_ARB_MISC0 + - description: MC_EMEM_ARB_RING1_THROTTLE + + required: + - clock-frequency + - nvidia,emem-configuration + + additionalProperties: false + + required: + - nvidia,ram-code + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - clock-names + - "#reset-cells" + - "#iommu-cells" + +additionalProperties: false + +examples: + - | + memory-controller@7000f000 { + compatible = "nvidia,tegra30-mc"; + reg = <0x7000f000 0x400>; + clocks = <&tegra_car 32>; + clock-names = "mc"; + + interrupts = <0 77 4>; + + #iommu-cells = <1>; + #reset-cells = <1>; + + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emem-configuration = < + 0x0000000a /* MC_EMEM_ARB_CFG */ + 0xc0000079 /* MC_EMEM_ARB_OUTSTANDING_REQ */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RCD */ + 0x00000004 /* MC_EMEM_ARB_TIMING_RP */ + 0x00000010 /* MC_EMEM_ARB_TIMING_RC */ + 0x0000000b /* MC_EMEM_ARB_TIMING_RAS */ + 0x0000000a /* MC_EMEM_ARB_TIMING_FAW */ + 0x00000001 /* MC_EMEM_ARB_TIMING_RRD */ + 0x00000003 /* MC_EMEM_ARB_TIMING_RAP2PRE */ + 0x0000000b /* MC_EMEM_ARB_TIMING_WAP2PRE */ + 0x00000002 /* MC_EMEM_ARB_TIMING_R2R */ + 0x00000002 /* MC_EMEM_ARB_TIMING_W2W */ + 0x00000004 /* MC_EMEM_ARB_TIMING_R2W */ + 0x00000008 /* MC_EMEM_ARB_TIMING_W2R */ + 0x08040202 /* MC_EMEM_ARB_DA_TURNS */ + 0x00130b10 /* MC_EMEM_ARB_DA_COVERS */ + 0x70ea1f11 /* MC_EMEM_ARB_MISC0 */ + 0x001f0000 /* MC_EMEM_ARB_RING1_THROTTLE */ + >; + }; + }; + };
Signature · 1 line
2.22.0
PATCH v8 11/15 dt-bindings: memory: Add binding for NVIDIA Tegra30 External Memory Controller
In reply to Dmitry OsipenkoAdd device-tree binding for NVIDIA Tegra30 External Memory Controller. The binding is based on the Tegra124 EMC binding since hardware is similar, although there are couple significant differences.
Note that the memory timing description is given in a platform-specific form because there is no detailed information on how to convert a typical-common DDR timing into the register values. The timing format is borrowed from downstream kernel, hence there is no hurdle in regards to upstreaming of memory timings for the boards.
--- .../nvidia,tegra30-emc.yaml | 341 ++++++++++++++++++ 1 file changed, 341 insertions(+) create mode 100644 Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml
Documentation/devicetree/bindings/memory-controllers/nvidia,tegra30-emc.yaml new file +341 -0
@@ -0,0 +1,341 @@ +# SPDX-License-Identifier: (GPL-2.0) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/memory-controllers/nvidia,tegra30-emc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: NVIDIA Tegra30 SoC External Memory Controller + +maintainers: + - Dmitry Osipenko <[email protected]> + - Jon Hunter <[email protected]> + - Thierry Reding <[email protected]> + +description: | + The EMC interfaces with the off-chip SDRAM to service the request stream + sent from Memory Controller. The EMC also has various performance-affecting + settings beyond the obvious SDRAM configuration parameters and initialization + settings. Tegra30 EMC supports multiple JEDEC standard protocols: LPDDR2, + LPDDR3, and DDR3. + +properties: + compatible: + const: nvidia,tegra30-emc + + reg: + maxItems: 1 + description: + Physical base address. + + clocks: + maxItems: 1 + description: + EMC clock. + + interrupts: + maxItems: 1 + description: + EMC General interrupt. + + nvidia,memory-controller: + $ref: /schemas/types.yaml#/definitions/phandle + description: + Phandle of the Memory Controller node. + +patternProperties: + "^emc-timings-[0-9]+$": + type: object + properties: + nvidia,ram-code: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Value of RAM_CODE this timing set is used for. + + patternProperties: + "^timing-[0-9]+$": + type: object + properties: + clock-frequency: + description: + Memory clock rate in Hz. + minimum: 1000000 + maximum: 900000000 + + nvidia,emc-auto-cal-interval: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Pad calibration interval. + + nvidia,emc-mode-1: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Mode Register 1. + + nvidia,emc-mode-2: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Mode Register 2. + + nvidia,emc-mode-reset: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Mode Register 0. + + nvidia,emc-zcal-cnt-long: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Number of EMC clocks to wait before issuing any commands after + sending ZCAL_MRW_CMD. + + nvidia,emc-cfg-dyn-self-ref: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + Dynamic self-refresh enabled. + + nvidia,emc-cfg-periodic-qrst: + $ref: /schemas/types.yaml#/definitions/uint32 + description: + FBIO "read" FIFO periodic resetting enabled. + + nvidia,emc-configuration: + $ref: /schemas/types.yaml#/definitions/uint32-array + description: + EMC timing characterization data. These are the registers + (see section "18.13.2 EMC Registers" in the TRM) whose values + need to be specified, according to the board documentation. + items: + - description: EMC_RC + - description: EMC_RFC + - description: EMC_RAS + - description: EMC_RP + - description: EMC_R2W + - description: EMC_W2R + - description: EMC_R2P + - description: EMC_W2P + - description: EMC_RD_RCD + - description: EMC_WR_RCD + - description: EMC_RRD + - description: EMC_REXT + - description: EMC_WEXT + - description: EMC_WDV + - description: EMC_QUSE + - description: EMC_QRST + - description: EMC_QSAFE + - description: EMC_RDV + - description: EMC_REFRESH + - description: EMC_BURST_REFRESH_NUM + - description: EMC_PRE_REFRESH_REQ_CNT + - description: EMC_PDEX2WR + - description: EMC_PDEX2RD + - description: EMC_PCHG2PDEN + - description: EMC_ACT2PDEN + - description: EMC_AR2PDEN + - description: EMC_RW2PDEN + - description: EMC_TXSR + - description: EMC_TXSRDLL + - description: EMC_TCKE + - description: EMC_TFAW + - description: EMC_TRPAB + - description: EMC_TCLKSTABLE + - description: EMC_TCLKSTOP + - description: EMC_TREFBW + - description: EMC_QUSE_EXTRA + - description: EMC_FBIO_CFG6 + - description: EMC_ODT_WRITE + - description: EMC_ODT_READ + - description: EMC_FBIO_CFG5 + - description: EMC_CFG_DIG_DLL + - description: EMC_CFG_DIG_DLL_PERIOD + - description: EMC_DLL_XFORM_DQS0 + - description: EMC_DLL_XFORM_DQS1 + - description: EMC_DLL_XFORM_DQS2 + - description: EMC_DLL_XFORM_DQS3 + - description: EMC_DLL_XFORM_DQS4 + - description: EMC_DLL_XFORM_DQS5 + - description: EMC_DLL_XFORM_DQS6 + - description: EMC_DLL_XFORM_DQS7 + - description: EMC_DLL_XFORM_QUSE0 + - description: EMC_DLL_XFORM_QUSE1 + - description: EMC_DLL_XFORM_QUSE2 + - description: EMC_DLL_XFORM_QUSE3 + - description: EMC_DLL_XFORM_QUSE4 + - description: EMC_DLL_XFORM_QUSE5 + - description: EMC_DLL_XFORM_QUSE6 + - description: EMC_DLL_XFORM_QUSE7 + - description: EMC_DLI_TRIM_TXDQS0 + - description: EMC_DLI_TRIM_TXDQS1 + - description: EMC_DLI_TRIM_TXDQS2 + - description: EMC_DLI_TRIM_TXDQS3 + - description: EMC_DLI_TRIM_TXDQS4 + - description: EMC_DLI_TRIM_TXDQS5 + - description: EMC_DLI_TRIM_TXDQS6 + - description: EMC_DLI_TRIM_TXDQS7 + - description: EMC_DLL_XFORM_DQ0 + - description: EMC_DLL_XFORM_DQ1 + - description: EMC_DLL_XFORM_DQ2 + - description: EMC_DLL_XFORM_DQ3 + - description: EMC_XM2CMDPADCTRL + - description: EMC_XM2DQSPADCTRL2 + - description: EMC_XM2DQPADCTRL2 + - description: EMC_XM2CLKPADCTRL + - description: EMC_XM2COMPPADCTRL + - description: EMC_XM2VTTGENPADCTRL + - description: EMC_XM2VTTGENPADCTRL2 + - description: EMC_XM2QUSEPADCTRL + - description: EMC_XM2DQSPADCTRL3 + - description: EMC_CTT_TERM_CTRL + - description: EMC_ZCAL_INTERVAL + - description: EMC_ZCAL_WAIT_CNT + - description: EMC_MRS_WAIT_CNT + - description: EMC_AUTO_CAL_CONFIG + - description: EMC_CTT + - description: EMC_CTT_DURATION + - description: EMC_DYN_SELF_REF_CONTROL + - description: EMC_FBIO_SPARE + - description: EMC_CFG_RSV + + required: + - clock-frequency + - nvidia,emc-auto-cal-interval + - nvidia,emc-mode-1 + - nvidia,emc-mode-2 + - nvidia,emc-mode-reset + - nvidia,emc-zcal-cnt-long + - nvidia,emc-cfg-dyn-self-ref + - nvidia,emc-cfg-periodic-qrst + - nvidia,emc-configuration + + additionalProperties: false + + required: + - nvidia,ram-code + + additionalProperties: false + +required: + - compatible + - reg + - interrupts + - clocks + - nvidia,memory-controller + +additionalProperties: false + +examples: + - | + external-memory-controller@7000f400 { + compatible = "nvidia,tegra30-emc"; + reg = <0x7000f400 0x400>; + interrupts = <0 78 4>; + clocks = <&tegra_car 57>; + + nvidia,memory-controller = <&mc>; + + emc-timings-1 { + nvidia,ram-code = <1>; + + timing-667000000 { + clock-frequency = <667000000>; + + nvidia,emc-auto-cal-interval = <0x001fffff>; + nvidia,emc-mode-1 = <0x80100002>; + nvidia,emc-mode-2 = <0x80200018>; + nvidia,emc-mode-reset = <0x80000b71>; + nvidia,emc-zcal-cnt-long = <0x00000040>; + nvidia,emc-cfg-dyn-self-ref = <0x00000000>; + nvidia,emc-cfg-periodic-qrst = <0x00000001>; + + nvidia,emc-configuration = < + 0x00000020 /* EMC_RC */ + 0x0000006a /* EMC_RFC */ + 0x00000017 /* EMC_RAS */ + 0x00000007 /* EMC_RP */ + 0x00000005 /* EMC_R2W */ + 0x0000000c /* EMC_W2R */ + 0x00000003 /* EMC_R2P */ + 0x00000011 /* EMC_W2P */ + 0x00000007 /* EMC_RD_RCD */ + 0x00000007 /* EMC_WR_RCD */ + 0x00000002 /* EMC_RRD */ + 0x00000001 /* EMC_REXT */ + 0x00000000 /* EMC_WEXT */ + 0x00000007 /* EMC_WDV */ + 0x0000000a /* EMC_QUSE */ + 0x00000009 /* EMC_QRST */ + 0x0000000b /* EMC_QSAFE */ + 0x00000011 /* EMC_RDV */ + 0x00001412 /* EMC_REFRESH */ + 0x00000000 /* EMC_BURST_REFRESH_NUM */ + 0x00000504 /* EMC_PRE_REFRESH_REQ_CNT */ + 0x00000002 /* EMC_PDEX2WR */ + 0x0000000e /* EMC_PDEX2RD */ + 0x00000001 /* EMC_PCHG2PDEN */ + 0x00000000 /* EMC_ACT2PDEN */ + 0x0000000c /* EMC_AR2PDEN */ + 0x00000016 /* EMC_RW2PDEN */ + 0x00000072 /* EMC_TXSR */ + 0x00000200 /* EMC_TXSRDLL */ + 0x00000005 /* EMC_TCKE */ + 0x00000015 /* EMC_TFAW */ + 0x00000000 /* EMC_TRPAB */ + 0x00000006 /* EMC_TCLKSTABLE */ + 0x00000007 /* EMC_TCLKSTOP */ + 0x00001453 /* EMC_TREFBW */ + 0x0000000b /* EMC_QUSE_EXTRA */ + 0x00000006 /* EMC_FBIO_CFG6 */ + 0x00000000 /* EMC_ODT_WRITE */ + 0x00000000 /* EMC_ODT_READ */ + 0x00005088 /* EMC_FBIO_CFG5 */ + 0xf00b0191 /* EMC_CFG_DIG_DLL */ + 0x00008000 /* EMC_CFG_DIG_DLL_PERIOD */ + 0x00000008 /* EMC_DLL_XFORM_DQS0 */ + 0x00000008 /* EMC_DLL_XFORM_DQS1 */ + 0x00000008 /* EMC_DLL_XFORM_DQS2 */ + 0x00000008 /* EMC_DLL_XFORM_DQS3 */ + 0x0000000a /* EMC_DLL_XFORM_DQS4 */ + 0x0000000a /* EMC_DLL_XFORM_DQS5 */ + 0x0000000a /* EMC_DLL_XFORM_DQS6 */ + 0x0000000a /* EMC_DLL_XFORM_DQS7 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE0 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE1 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE2 */ + 0x00018000 /* EMC_DLL_XFORM_QUSE3 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE4 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE5 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE6 */ + 0x00000000 /* EMC_DLL_XFORM_QUSE7 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS0 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS1 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS2 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS3 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS4 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS5 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS6 */ + 0x00000000 /* EMC_DLI_TRIM_TXDQS7 */ + 0x0000000a /* EMC_DLL_XFORM_DQ0 */ + 0x0000000a /* EMC_DLL_XFORM_DQ1 */ + 0x0000000a /* EMC_DLL_XFORM_DQ2 */ + 0x0000000a /* EMC_DLL_XFORM_DQ3 */ + 0x000002a0 /* EMC_XM2CMDPADCTRL */ + 0x0800013d /* EMC_XM2DQSPADCTRL2 */ + 0x22220000 /* EMC_XM2DQPADCTRL2 */ + 0x77fff884 /* EMC_XM2CLKPADCTRL */ + 0x01f1f501 /* EMC_XM2COMPPADCTRL */ + 0x07077404 /* EMC_XM2VTTGENPADCTRL */ + 0x54000000 /* EMC_XM2VTTGENPADCTRL2 */ + 0x080001e8 /* EMC_XM2QUSEPADCTRL */ + 0x0c000021 /* EMC_XM2DQSPADCTRL3 */ + 0x00000802 /* EMC_CTT_TERM_CTRL */ + 0x00020000 /* EMC_ZCAL_INTERVAL */ + 0x00000100 /* EMC_ZCAL_WAIT_CNT */ + 0x0155000c /* EMC_MRS_WAIT_CNT */ + 0xa0f10000 /* EMC_AUTO_CAL_CONFIG */ + 0x00000000 /* EMC_CTT */ + 0x00000000 /* EMC_CTT_DURATION */ + 0x800028a5 /* EMC_DYN_SELF_REF_CONTROL */ + 0xe8000000 /* EMC_FBIO_SPARE */ + 0xff00ff49 /* EMC_CFG_RSV */ + >; + }; + }; + };
Signature · 1 line
2.22.0
PATCH v8 12/15 memory: tegra: Introduce Tegra30 EMC driver
In reply to Dmitry OsipenkoIntroduce driver for the External Memory Controller (EMC) found on Tegra30 chips, it controls the external DRAM on the board. The purpose of this driver is to program memory timing for external memory on the EMC clock rate change.
--- drivers/memory/tegra/Kconfig | 10 + drivers/memory/tegra/Makefile | 1 + drivers/memory/tegra/mc.c | 9 +- drivers/memory/tegra/mc.h | 30 +- drivers/memory/tegra/tegra30-emc.c | 1230 ++++++++++++++++++++++++++++ drivers/memory/tegra/tegra30.c | 42 + include/soc/tegra/mc.h | 2 +- 7 files changed, 1309 insertions(+), 15 deletions(-) create mode 100644 drivers/memory/tegra/tegra30-emc.c
drivers/memory/tegra/Kconfig +10 -0
@@ -17,6 +17,16 @@ config TEGRA20_EMC This driver is required to change memory timings / clock rate for external memory. +config TEGRA30_EMC + bool "NVIDIA Tegra30 External Memory Controller driver" + default y + depends on TEGRA_MC && ARCH_TEGRA_3x_SOC + help + This driver is for the External Memory Controller (EMC) found on + Tegra30 chips. The EMC controls the external DRAM on the board. + This driver is required to change memory timings / clock rate for + external memory. + config TEGRA124_EMC bool "NVIDIA Tegra124 External Memory Controller driver" default y
drivers/memory/tegra/Makefile +1 -0
@@ -11,5 +11,6 @@ tegra-mc-$(CONFIG_ARCH_TEGRA_210_SOC) += tegra210.o obj-$(CONFIG_TEGRA_MC) += tegra-mc.o obj-$(CONFIG_TEGRA20_EMC) += tegra20-emc.o +obj-$(CONFIG_TEGRA30_EMC) += tegra30-emc.o obj-$(CONFIG_TEGRA124_EMC) += tegra124-emc.o obj-$(CONFIG_ARCH_TEGRA_186_SOC) += tegra186.o
drivers/memory/tegra/mc.c +4 -5
@@ -48,9 +48,6 @@#define MC_EMEM_ADR_CFG 0x54#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) -#define MC_TIMING_CONTROL 0xfc -#define MC_TIMING_UPDATE BIT(0) -static const struct of_device_id tegra_mc_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_2x_SOC { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
@@ -307,7 +304,7 @@ static int tegra_mc_setup_latency_allowance(struct tegra_mc *mc)return 0 ; } -void tegra_mc_write_emem_configuration (struct tegra_mc *mc,unsigned long rate) +int tegra_mc_write_emem_configuration (struct tegra_mc *mc,unsigned long rate) {unsigned int i;struct tegra_mc_timing *timing =NULL ;
@@ -322,11 +319,13 @@ void tegra_mc_write_emem_configuration(struct tegra_mc *mc, unsigned long rate)if (!timing) {dev_err (mc->dev,"no memory timing registered for rate %lu\n" , rate); -return ; +return -EINVAL ; }for (i =0 ; i < mc->soc->num_emem_regs; ++i)mc_writel (mc, timing->emem_data[i], mc->soc->emem_regs[i]); + +return 0 ; }unsigned int tegra_mc_get_emem_device_count (struct tegra_mc *mc)
drivers/memory/tegra/mc.h +21 -9
@@ -6,20 +6,32 @@#ifndef MEMORY_TEGRA_MC_H #define MEMORY_TEGRA_MC_H +#include <linux/bits.h> #include <linux/io.h> #include <linux/types.h> #include <soc/tegra/mc.h> -#define MC_INT_DECERR_MTS (1 << 16) -#define MC_INT_SECERR_SEC (1 << 13) -#define MC_INT_DECERR_VPR (1 << 12) -#define MC_INT_INVALID_APB_ASID_UPDATE (1 << 11) -#define MC_INT_INVALID_SMMU_PAGE (1 << 10) -#define MC_INT_ARBITRATION_EMEM (1 << 9) -#define MC_INT_SECURITY_VIOLATION (1 << 8) -#define MC_INT_INVALID_GART_PAGE (1 << 7) -#define MC_INT_DECERR_EMEM (1 << 6) +#define MC_INT_DECERR_MTS BIT(16) +#define MC_INT_SECERR_SEC BIT(13) +#define MC_INT_DECERR_VPR BIT(12) +#define MC_INT_INVALID_APB_ASID_UPDATE BIT(11) +#define MC_INT_INVALID_SMMU_PAGE BIT(10) +#define MC_INT_ARBITRATION_EMEM BIT(9) +#define MC_INT_SECURITY_VIOLATION BIT(8) +#define MC_INT_INVALID_GART_PAGE BIT(7) +#define MC_INT_DECERR_EMEM BIT(6) + +#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 +#define MC_EMEM_ARB_OUTSTANDING_REQ_MAX_MASK 0x1ff +#define MC_EMEM_ARB_OUTSTANDING_REQ_HOLDOFF_OVERRIDE BIT(30) +#define MC_EMEM_ARB_OUTSTANDING_REQ_LIMIT_ENABLE BIT(31) + +#define MC_EMEM_ARB_OVERRIDE 0xe8 +#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3 + +#define MC_TIMING_CONTROL 0xfc +#define MC_TIMING_UPDATE BIT(0)static inline u32 mc_readl (struct tegra_mc *mc,unsigned long offset) {
drivers/memory/tegra/tegra30-emc.c new file +1230 -0
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drivers/memory/tegra/tegra30.c +42 -0
54 lines not on this page · raw message
include/soc/tegra/mc.h +1 -1
@@ -181,7 +181,7 @@ struct tegra_mc { spinlock_t lock; }; -void tegra_mc_write_emem_configuration (struct tegra_mc *mc,unsigned long rate); +int tegra_mc_write_emem_configuration (struct tegra_mc *mc,unsigned long rate);unsigned int tegra_mc_get_emem_device_count (struct tegra_mc *mc);#endif /* __SOC_TEGRA_MC_H__ */
Signature · 1 line
2.22.0
PATCH v8 13/15 memory: tegra: Ensure timing control debug features are disabled
In reply to Dmitry OsipenkoTiming control debug features should be disabled at a boot time, but you never now and hence it's better to disable them explicitly because some of those features are crucial for the driver to do a proper thing.
--- drivers/memory/tegra/mc.c | 3 +++ drivers/memory/tegra/mc.h | 2 ++ 2 files changed, 5 insertions(+)
drivers/memory/tegra/mc.c +3 -0
@@ -657,6 +657,9 @@ static int tegra_mc_probe(struct platform_device *pdev) } else#endif { +/* ensure that debug features are disabled */ +mc_writel (mc,0x00000000 ,MC_TIMING_CONTROL_DBG ); + err =tegra_mc_setup_latency_allowance (mc);if (err <0 ) { dev_err(&pdev->dev,
drivers/memory/tegra/mc.h +2 -0
@@ -30,6 +30,8 @@#define MC_EMEM_ARB_OVERRIDE 0xe8#define MC_EMEM_ARB_OVERRIDE_EACK_MASK 0x3 +#define MC_TIMING_CONTROL_DBG 0xf8 +#define MC_TIMING_CONTROL 0xfc#define MC_TIMING_UPDATE BIT(0)
Signature · 1 line
2.22.0
PATCH v8 14/15 memory: tegra: Consolidate registers definition into common header
In reply to Dmitry OsipenkoThe Memory Controller registers definition is sparse and duplicated, let's consolidate everything into a common place for consistency.
--- drivers/memory/tegra/mc.c | 30 ------------------- drivers/memory/tegra/mc.h | 52 +++++++++++++++++++++++++++++---- drivers/memory/tegra/tegra124.c | 20 ------------- drivers/memory/tegra/tegra30.c | 19 ------------ 4 files changed, 47 insertions(+), 74 deletions(-)
drivers/memory/tegra/mc.c +0 -30
@@ -18,36 +18,6 @@#include "mc.h" -#define MC_INTSTATUS 0x000 - -#define MC_INTMASK 0x004 - -#define MC_ERR_STATUS 0x08 -#define MC_ERR_STATUS_TYPE_SHIFT 28 -#define MC_ERR_STATUS_TYPE_INVALID_SMMU_PAGE (6 << MC_ERR_STATUS_TYPE_SHIFT) -#define MC_ERR_STATUS_TYPE_MASK (0x7 << MC_ERR_STATUS_TYPE_SHIFT) -#define MC_ERR_STATUS_READABLE (1 << 27) -#define MC_ERR_STATUS_WRITABLE (1 << 26) -#define MC_ERR_STATUS_NONSECURE (1 << 25) -#define MC_ERR_STATUS_ADR_HI_SHIFT 20 -#define MC_ERR_STATUS_ADR_HI_MASK 0x3 -#define MC_ERR_STATUS_SECURITY (1 << 17) -#define MC_ERR_STATUS_RW (1 << 16) - -#define MC_ERR_ADR 0x0c - -#define MC_GART_ERROR_REQ 0x30 -#define MC_DECERR_EMEM_OTHERS_STATUS 0x58 -#define MC_SECURITY_VIOLATION_STATUS 0x74 - -#define MC_EMEM_ARB_CFG 0x90 -#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE (x) (((x) & 0x1ff) << 0) -#define MC_EMEM_ARB_CFG_CYCLES_PER_UPDATE_MASK 0x1ff -#define MC_EMEM_ARB_MISC0 0xd8 - -#define MC_EMEM_ADR_CFG 0x54 -#define MC_EMEM_ADR_CFG_EMEM_NUMDEV BIT(0) -static const struct of_device_id tegra_mc_of_match[] = { #ifdef CONFIG_ARCH_TEGRA_2x_SOC { .compatible = "nvidia,tegra20-mc-gart", .data = &tegra20_mc_soc },
drivers/memory/tegra/mc.h +47 -5
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drivers/memory/tegra/tegra124.c +0 -20
@@ -10,26 +10,6 @@#include "mc.h" -#define MC_EMEM_ARB_CFG 0x90 -#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 -#define MC_EMEM_ARB_TIMING_RCD 0x98 -#define MC_EMEM_ARB_TIMING_RP 0x9c -#define MC_EMEM_ARB_TIMING_RC 0xa0 -#define MC_EMEM_ARB_TIMING_RAS 0xa4 -#define MC_EMEM_ARB_TIMING_FAW 0xa8 -#define MC_EMEM_ARB_TIMING_RRD 0xac -#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 -#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 -#define MC_EMEM_ARB_TIMING_R2R 0xb8 -#define MC_EMEM_ARB_TIMING_W2W 0xbc -#define MC_EMEM_ARB_TIMING_R2W 0xc0 -#define MC_EMEM_ARB_TIMING_W2R 0xc4 -#define MC_EMEM_ARB_DA_TURNS 0xd0 -#define MC_EMEM_ARB_DA_COVERS 0xd4 -#define MC_EMEM_ARB_MISC0 0xd8 -#define MC_EMEM_ARB_MISC1 0xdc -#define MC_EMEM_ARB_RING1_THROTTLE 0xe0 -static const struct tegra_mc_client tegra124_mc_clients[] = { { .id =0x00 ,
drivers/memory/tegra/tegra30.c +0 -19
@@ -10,25 +10,6 @@#include "mc.h" -#define MC_EMEM_ARB_CFG 0x90 -#define MC_EMEM_ARB_OUTSTANDING_REQ 0x94 -#define MC_EMEM_ARB_TIMING_RCD 0x98 -#define MC_EMEM_ARB_TIMING_RP 0x9c -#define MC_EMEM_ARB_TIMING_RC 0xa0 -#define MC_EMEM_ARB_TIMING_RAS 0xa4 -#define MC_EMEM_ARB_TIMING_FAW 0xa8 -#define MC_EMEM_ARB_TIMING_RRD 0xac -#define MC_EMEM_ARB_TIMING_RAP2PRE 0xb0 -#define MC_EMEM_ARB_TIMING_WAP2PRE 0xb4 -#define MC_EMEM_ARB_TIMING_R2R 0xb8 -#define MC_EMEM_ARB_TIMING_W2W 0xbc -#define MC_EMEM_ARB_TIMING_R2W 0xc0 -#define MC_EMEM_ARB_TIMING_W2R 0xc4 -#define MC_EMEM_ARB_DA_TURNS 0xd0 -#define MC_EMEM_ARB_DA_COVERS 0xd4 -#define MC_EMEM_ARB_MISC0 0xd8 -#define MC_EMEM_ARB_RING1_THROTTLE 0xe0 -static const unsigned long tegra30_mc_emem_regs[] = {MC_EMEM_ARB_CFG ,MC_EMEM_ARB_OUTSTANDING_REQ ,
Signature · 1 line
2.22.0
PATCH v8 15/15 ARM: dts: tegra30: Add External Memory Controller node
In reply to Dmitry OsipenkoAdd External Memory Controller node to the device-tree.
--- arch/arm/boot/dts/tegra30.dtsi | 9 +++++++++ 1 file changed, 9 insertions(+)
arch/arm/boot/dts/tegra30.dtsi +9 -0
@@ -732,6 +732,15 @@ #reset-cells = <1>; }; + memory-controller@7000f400 { + compatible = "nvidia,tegra30-emc"; + reg = <0x7000f400 0x400>; + interrupts = <GIC_SPI 78 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&tegra_car TEGRA30_CLK_EMC>; + + nvidia,memory-controller = <&mc>; + }; + fuse@7000f800 { compatible = "nvidia,tegra30-efuse"; reg = <0x7000f800 0x400>;
Signature · 1 line
2.22.0