Add non PAS wcss Q6 support for QCS404
Subsystems (5)
v5 cover Add non PAS wcss Q6 support for QCS404
Add non PAS(Peripheral Authentication System) WCSS remoteproc driver support and wcss clock/reset controls for QCS404 SOC. Add WCSS q6 bootup and shutdown sequence handled from Application Processor SubSystem(APSS).
Changes since v4:
removed QDSP6SS clock controls and moved to wcss rproc. renamed wcsccc to q6sstopcc. cleanup/refactoring.
Changes since v3:
dt binding cleanup.
Fixed remoteproc recovery.
Added remoteproc dump support.
wcsscc cleanup/refactoring.
Changes since v2:
Removed unused properties.
Refactored code to have common logic b/w ipq8074 and QCS404, wherever possible. Added compatible example.
Removed wcss-protected bool.
Changes since v1:
Corrected clock names as per comments in v1 patch.
Govind Singh (7):
clk: qcom: Add WCSS gcc clock control for QCS404
dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings
clk: qcom: define probe by index API as common API
clk: qcom: Add Q6SSTOP clock controller for QCS404
remoteproc: qcom: wcss: populate hardcoded param using driver data
remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
remoteproc: qcom: wcss: explicitly request exclusive reset control
.../bindings/clock/qcom,q6sstopcc.txt | 26 + drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/common.c | 20 + drivers/clk/qcom/common.h | 2 + drivers/clk/qcom/gcc-qcs404.c | 30 + drivers/clk/qcom/lpasscc-sdm845.c | 23 +- drivers/clk/qcom/q6sstop-qcs404.c | 223 +++++++ drivers/remoteproc/qcom_q6v5_wcss.c | 599 ++++++++++++++++-- include/dt-bindings/clock/qcom,gcc-qcs404.h | 3 + .../dt-bindings/clock/qcom,q6sstopcc-qcs404.h | 18 + 11 files changed, 890 insertions(+), 63 deletions(-) create mode 100755 Documentation/devicetree/bindings/clock/qcom,q6sstopcc.txt create mode 100644 drivers/clk/qcom/q6sstop-qcs404.c create mode 100644 include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v5 1/7 clk: qcom: Add WCSS gcc clock control for QCS404
Add support for the WCSS QDSP gcc clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required gcc clocks to bring the subsystem out of reset.
Signed-off-by Govind Singh <[email protected]>
--- drivers/clk/qcom/gcc-qcs404.c | 30 +++++++++++++++++++++ include/dt-bindings/clock/qcom,gcc-qcs404.h | 3 +++ 2 files changed, 33 insertions(+)
drivers/clk/qcom/gcc-qcs404.c +30 -0
@@ -2604,6 +2604,32 @@ static struct clk_branch gcc_usb_hs_system_clk = { }, }; +static struct clk_branch gcc_wdsp_q6ss_ahbs_clk = { + .halt_reg =0x1e004 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x1e004 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_wdsp_q6ss_ahbs_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_wdsp_q6ss_axim_clk = { + .halt_reg =0x1e008 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0x1e008 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_wdsp_q6ss_axim_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_hw *gcc_qcs404_hws[] = { &cxo.hw, };
@@ -2749,6 +2775,9 @@ static struct clk_regmap *gcc_qcs404_clocks[] = { [GCC_QDSS_DAP_CLK] = &gcc_qdss_dap_clk.clkr, [GCC_DCC_CLK] = &gcc_dcc_clk.clkr, [GCC_DCC_XO_CLK] = &gcc_dcc_xo_clk.clkr, + [GCC_WCSS_Q6_AHB_CLK] = &gcc_wdsp_q6ss_ahbs_clk.clkr, + [GCC_WCSS_Q6_AXIM_CLK] = &gcc_wdsp_q6ss_axim_clk.clkr, + };static const struct qcom_reset_map gcc_qcs404_resets[] = {
@@ -2774,6 +2803,7 @@ static const struct qcom_reset_map gcc_qcs404_resets[] = { [GCC_PCIE_0_SLEEP_ARES] = { 0x3e040, 1 }, [GCC_PCIE_0_PIPE_ARES] = { 0x3e040, 0 }, [GCC_EMAC_BCR] = { 0x4e000 }, + [GCC_WDSP_RESTART] = {0x19000}, };static const struct regmap_config gcc_qcs404_regmap_config = {
include/dt-bindings/clock/qcom,gcc-qcs404.h +3 -0
@@ -146,6 +146,8 @@#define GCC_MDP_TBU_CLK 138#define GCC_QDSS_DAP_CLK 139#define GCC_DCC_XO_CLK 140 +#define GCC_WCSS_Q6_AHB_CLK 141 +#define GCC_WCSS_Q6_AXIM_CLK 142#define GCC_CDSP_CFG_AHB_CLK 143#define GCC_BIMC_CDSP_CLK 144#define GCC_CDSP_TBU_CLK 145
@@ -173,5 +175,6 @@#define GCC_PCIE_0_CORE_STICKY_ARES 19#define GCC_PCIE_0_SLEEP_ARES 20#define GCC_PCIE_0_PIPE_ARES 21 +#define GCC_WDSP_RESTART 22#endif
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v5 1/7] clk: qcom: Add WCSS gcc clock control for QCS404
Quoting Govind Singh (2019-07-26 02:23:26)
Quoted 6 lines
Add support for the WCSS QDSP gcc clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required gcc clocks to bring the subsystem out of reset.
Signed-off-by Govind Singh <[email protected]>---
Applied to clk-next
PATCH v5 2/7 dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings
In reply to Govind SinghAdd devicetree binding for the Q6SSTOP clock controller found in QCS404.
Signed-off-by Govind Singh <[email protected]>
--- .../bindings/clock/qcom,q6sstopcc.txt | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100755 Documentation/devicetree/bindings/clock/qcom,q6sstopcc.txt
Documentation/devicetree/bindings/clock/qcom,q6sstopcc.txt new file +26 -0
@@ -0,0 +1,26 @@ +Qualcomm Q6SSTOP Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,qcs404-q6sstopcc" +- #clock-cells : from common clock binding, shall contain 1 +- reg : shall contain base register address and size, + in the order + Index 0 maps to Q6SSTOP clocks register region + Index 1 maps to Q6SSTOP_TCSR register region + +Optional properties : +- reg-names : register names of WCSS domain + "q6sstop_cc", "q6sstop_tcsr". + +Example: +The below node has to be defined in the cases where the WCSS peripheral loader +would bring the subsystem out of reset. + + q6sstopcc: clock-controller@7500000 { + compatible = "qcom,qcs404-q6sstopcc"; + reg = <0x7500000 0x4e000>, <0x7550000 0x10000>; + reg-names = "q6sstop_cc", "q6sstop_tcsr"; + clocks = <&gcc GCC_WCSS_Q6_AHB_CLK>; + #clock-cells = <1>; + };
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Stephen Boyd
maintainerRe: [PATCH v5 2/7] dt-bindings: clock: qcom: Add QCOM Q6SSTOP clock controller bindings
Quoting Govind Singh (2019-07-26 02:23:27)
Quoted 3 lines
Add devicetree binding for the Q6SSTOP clock controller found in QCS404.
Signed-off-by Govind Singh <[email protected]>
If this patch goes again, please convert to YAML.
Quoted 25 lines
--- .../bindings/clock/qcom,q6sstopcc.txt | 26 +++++++++++++++++++ 1 file changed, 26 insertions(+) create mode 100755 Documentation/devicetree/bindings/clock/qcom,q6sstopcc.txtDocumentation/devicetree/bindings/clock/qcom,q6sstopcc.txt new file +14
-0@@ -0,0 +1,26 @@ +Qualcomm Q6SSTOP Clock Controller Binding +----------------------------------------------- + +Required properties : +- compatible : shall contain "qcom,qcs404-q6sstopcc" +- #clock-cells : from common clock binding, shall contain 1 +- reg : shall contain base register address and size, + in the order + Index 0 maps to Q6SSTOP clocks register region + Index 1 maps to Q6SSTOP_TCSR register region + +Optional properties : +- reg-names : register names of WCSS domain + "q6sstop_cc", "q6sstop_tcsr".
Documentation/devicetree/bindings/clock/qcom,q6sstopcc.txt line 24
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,q6sstopcc.txt new file +10
-0+ +Example: +The below node has to be defined in the cases where the WCSS peripheral loader +would bring the subsystem out of reset. + + q6sstopcc: clock-controller@7500000 { + compatible = "qcom,qcs404-q6sstopcc"; + reg = <0x7500000 0x4e000>, <0x7550000 0x10000>; + reg-names = "q6sstop_cc", "q6sstop_tcsr"; + clocks = <&gcc GCC_WCSS_Q6_AHB_CLK>;
This isn't described in the binding. Are there clocks that go here? Please add them to the binding.
PATCH v5 3/7 clk: qcom: define probe by index API as common API
In reply to Govind SinghExtend the probe by index API in common code to be used by other qcom clock controller.
Signed-off-by Govind Singh <[email protected]>
--- drivers/clk/qcom/common.c | 20 ++++++++++++++++++++ drivers/clk/qcom/common.h | 2 ++ drivers/clk/qcom/lpasscc-sdm845.c | 23 ++--------------------- 3 files changed, 24 insertions(+), 21 deletions(-)
drivers/clk/qcom/common.c +20 -0
@@ -306,4 +306,24 @@ int qcom_cc_probe(struct platform_device *pdev, const struct qcom_cc_desc *desc) }EXPORT_SYMBOL_GPL (qcom_cc_probe); +int qcom_cc_probe_by_index (struct platform_device *pdev,int index, +const struct qcom_cc_desc *desc) +{ +struct regmap *regmap; +struct resource *res; +void __iomem *base; + + res =platform_get_resource (pdev,IORESOURCE_MEM , index); + base =devm_ioremap_resource (&pdev->dev, res); +if (IS_ERR (base)) +return -ENOMEM ; + + regmap =devm_regmap_init_mmio (&pdev->dev, base, desc->config); +if (IS_ERR (regmap)) +return PTR_ERR (regmap); + +return qcom_cc_really_probe (pdev, desc, regmap); +} +EXPORT_SYMBOL_GPL (qcom_cc_probe_by_index); +MODULE_LICENSE ("GPL v2" );
drivers/clk/qcom/common.h +2 -0
@@ -61,5 +61,7 @@ extern int qcom_cc_really_probe(struct platform_device *pdev, struct regmap *regmap);extern int qcom_cc_probe (struct platform_device *pdev,const struct qcom_cc_desc *desc); +extern int qcom_cc_probe_by_index (struct platform_device *pdev,int index, +const struct qcom_cc_desc *desc);#endif
drivers/clk/qcom/lpasscc-sdm845.c +2 -21
@@ -112,25 +112,6 @@ static const struct qcom_cc_desc lpass_qdsp6ss_sdm845_desc = { .num_clks = ARRAY_SIZE(lpass_qdsp6ss_sdm845_clocks), }; -static int lpass_clocks_sdm845_probe (struct platform_device *pdev,int index, -const struct qcom_cc_desc *desc) -{ -struct regmap *regmap; -struct resource *res; -void __iomem *base; - - res =platform_get_resource (pdev,IORESOURCE_MEM , index); - base =devm_ioremap_resource (&pdev->dev, res); -if (IS_ERR (base)) -return PTR_ERR (base); - - regmap =devm_regmap_init_mmio (&pdev->dev, base, desc->config); -if (IS_ERR (regmap)) -return PTR_ERR (regmap); - -return qcom_cc_really_probe (pdev, desc, regmap); -} -static int lpass_cc_sdm845_probe (struct platform_device *pdev) {const struct qcom_cc_desc *desc;
@@ -139,14 +120,14 @@ static int lpass_cc_sdm845_probe(struct platform_device *pdev) lpass_regmap_config.name ="cc" ; desc = &lpass_cc_sdm845_desc; - ret =lpass_clocks_sdm845_probe (pdev,0 , desc); + ret =qcom_cc_probe_by_index (pdev,0 , desc);if (ret)return ret; lpass_regmap_config.name ="qdsp6ss" ; desc = &lpass_qdsp6ss_sdm845_desc; -return lpass_clocks_sdm845_probe (pdev,1 , desc); +return qcom_cc_probe_by_index (pdev,1 , desc); }static const struct of_device_id lpass_cc_sdm845_match_table[] = {
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v5 3/7] clk: qcom: define probe by index API as common API
Quoting Govind Singh (2019-07-26 02:23:28)
Quoted 5 lines
Extend the probe by index API in common code to be used by other qcom clock controller.
Signed-off-by Govind Singh <[email protected]>---
Applied to clk-next
PATCH v5 4/7 clk: qcom: Add Q6SSTOP clock controller for QCS404
In reply to Govind SinghAdd support for the Q6SSTOP clock control used on qcs404 based devices. This would allow wcss remoteproc driver to control the required WCSS Q6SSTOP clock/reset controls to bring the subsystem out of reset and shutdown the WCSS Q6DSP.
Signed-off-by Govind Singh <[email protected]>
--- drivers/clk/qcom/Kconfig | 8 + drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/q6sstop-qcs404.c | 223 ++++++++++++++++++ .../dt-bindings/clock/qcom,q6sstopcc-qcs404.h | 18 ++ 4 files changed, 250 insertions(+) create mode 100644 drivers/clk/qcom/q6sstop-qcs404.c create mode 100644 include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h
drivers/clk/qcom/Kconfig +8 -0
@@ -250,6 +250,14 @@ config QCS_TURING_404 Support for the Turing Clock Controller on QCS404, provides clocks and resets for the Turing subsystem. +config QCS_Q6SSTOP_404 + tristate "QCS404 Q6SSTOP Clock Controller" + select QCS_GCC_404 + help + Support for the Q6SSTOP clock controller on QCS404 devices. + Say Y if you want to use the Q6SSTOP branch clocks of the WCSS clock + controller to reset the Q6SSTOP subsystem. + config SDM_GCC_845 tristate "SDM845 Global Clock Controller" select QCOM_GDSC
drivers/clk/qcom/Makefile +1 -0
@@ -43,6 +43,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o +obj-$(CONFIG_QCS_Q6SSTOP_404) += q6sstop-qcs404.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
drivers/clk/qcom/q6sstop-qcs404.c new file +223 -0
223 lines not on this page · raw message
include/dt-bindings/clock/qcom,q6sstopcc-qcs404.h new file +18 -0
@@ -0,0 +1,18 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2018, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H +#define _DT_BINDINGS_CLK_Q6SSTOP_QCS404_H + +#define LCC_AHBFABRIC_CBC_CLK 0 +#define LCC_Q6SS_AHBS_CBC_CLK 1 +#define LCC_Q6SS_TCM_SLAVE_CBC_CLK 2 +#define LCC_Q6SS_AHBM_CBC_CLK 3 +#define LCC_Q6SS_AXIM_CBC_CLK 4 +#define LCC_Q6SS_BCR_SLEEP_CLK 5 +#define TCSR_Q6SS_LCC_CBCR_CLK 6 + +#define Q6SSTOP_BCR_RESET 1 +#endif
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Stephen Boyd
maintainerRe: [PATCH v5 4/7] clk: qcom: Add Q6SSTOP clock controller for QCS404
Quoting Govind Singh (2019-07-26 02:23:29)
Quoted 6 lines
drivers/clk/qcom/q6sstop-qcs404.c new file +0
-0@@ -0,0 +1,223 @@
[...]
drivers/clk/qcom/q6sstop-qcs404.c line 216
Quoted 9 lines
drivers/clk/qcom/q6sstop-qcs404.c new file +9
-0+}; + +static struct platform_driver q6sstopcc_qcs404_driver = { + .probe = q6sstopcc_qcs404_probe, + .remove = q6sstopcc_qcs404_remove, + .driver = { + .name ="qcs404-q6sstopcc" , + .of_match_table = q6sstopcc_qcs404_match_table, + .pm = &q6sstopcc_pm_ops,
This got some weird indent.
Quoted 7 lines
drivers/clk/qcom/q6sstop-qcs404.c new file +7
-0+ }, +}; + +module_platform_driver (q6sstopcc_qcs404_driver); + +MODULE_DESCRIPTION ("QTI QCS404 Q6SSTOP Clock Controller Driver" ); +MODULE_LICENSE ("GPL v2" );
Re: [PATCH v5 4/7] clk: qcom: Add Q6SSTOP clock controller for QCS404
Hi Stephen,
Quoted 8 lines · Stephen Boyd
Quoting Govind Singh (2019-07-26 02:23:29)
Quoted 6 lines
drivers/clk/qcom/q6sstop-qcs404.c new file +0
-0@@ -0,0 +1,223 @@[...]
Quoted 12 lines
drivers/clk/qcom/q6sstop-qcs404.c line 216
Quoted 9 lines
drivers/clk/qcom/q6sstop-qcs404.c new file +9
-0+}; + +static struct platform_driver q6sstopcc_qcs404_driver = { + .probe = q6sstopcc_qcs404_probe, + .remove = q6sstopcc_qcs404_remove, + .driver = { + .name ="qcs404-q6sstopcc" , + .of_match_table = q6sstopcc_qcs404_match_table, + .pm = &q6sstopcc_pm_ops,This got some weird indent.
Fixed in next rev.
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=159221
I have removed this change from the previous series. DT binding change is converted to YAML.
Quoted 7 lines
drivers/clk/qcom/q6sstop-qcs404.c line 223
Quoted 7 lines
drivers/clk/qcom/q6sstop-qcs404.c new file +7
-0+ }, +}; + +module_platform_driver (q6sstopcc_qcs404_driver); + +MODULE_DESCRIPTION ("QTI QCS404 Q6SSTOP Clock Controller Driver" ); +MODULE_LICENSE ("GPL v2" );
BR,
Govind
PATCH v5 5/7 remoteproc: qcom: wcss: populate hardcoded param using driver data
In reply to Govind SinghQ6 based WiFi fw loading is supported across different targets, ex: IPQ8074/QCS404. In order to support different fw names/pas id etc, populate hardcoded param using driver data.
Signed-off-by Govind Singh <[email protected]>
--- drivers/remoteproc/qcom_q6v5_wcss.c | 31 ++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +26 -5
@@ -8,6 +8,7 @@#include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> +#include <linux/of_device.h> #include <linux/of_reserved_mem.h> #include <linux/platform_device.h> #include <linux/regmap.h>
@@ -70,6 +71,11 @@#define TCSR_WCSS_CLK_MASK 0x1F#define TCSR_WCSS_CLK_ENABLE 0x14 +struct wcss_data { +const char *firmware_name; +int crash_reason_smem; +}; +struct q6v5_wcss {struct device *dev;
@@ -91,6 +97,8 @@ struct q6v5_wcss {phys_addr_t mem_reloc;void *mem_region;size_t mem_size; + +int crash_reason_smem; };static int q6v5_wcss_reset (struct q6v5_wcss *wcss)
@@ -427,7 +435,7 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) wcss->mem_size, &wcss->mem_reloc); } -static const struct rproc_ops q6v5_wcss_ops = { +static const struct rproc_ops q6v5_wcss_ipq8074_ops = { .start = q6v5_wcss_start, .stop = q6v5_wcss_stop, .da_to_va = q6v5_wcss_da_to_va,
@@ -527,12 +535,17 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)static int q6v5_wcss_probe (struct platform_device *pdev) { +const struct wcss_data *desc;struct q6v5_wcss *wcss;struct rproc *rproc;int ret; - rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ops, -"IPQ8074/q6_fw.mdt" ,sizeof (*wcss)); + desc =of_device_get_match_data (&pdev->dev); +if (!desc) +return -EINVAL ; + + rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, + desc->firmware_name,sizeof (*wcss));if (!rproc) {dev_err (&pdev->dev,"failed to allocate rproc\n" );return -ENOMEM ;
@@ -540,6 +553,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss = rproc->priv; wcss->dev = &pdev->dev; + wcss->crash_reason_smem = desc->crash_reason_smem; ret =q6v5_wcss_init_mmio (wcss, pdev);if (ret)
@@ -553,7 +567,8 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (ret) goto free_rproc; - ret =qcom_q6v5_init (&wcss->q6v5, pdev, rproc,WCSS_CRASH_REASON ,NULL ); + ret =qcom_q6v5_init (&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, +NULL );if (ret) goto free_rproc;
@@ -581,8 +596,14 @@ static int q6v5_wcss_remove(struct platform_device *pdev)return 0 ; } +static const struct wcss_data wcss_ipq8074_res_init = { + .firmware_name ="IPQ8074/q6_fw.mdt" , + .crash_reason_smem =WCSS_CRASH_REASON , +}; +static const struct of_device_id q6v5_wcss_of_match[] = { - { .compatible ="qcom,ipq8074-wcss-pil" }, + { .compatible ="qcom,ipq8074-wcss-pil" , .data = &wcss_ipq8074_res_init }, + { }, };MODULE_DEVICE_TABLE (of, q6v5_wcss_of_match);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v5 6/7 remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
In reply to Govind SinghAdd non PAS WCSS remoteproc driver support for QCS404 SOC. Add WCSS q6 bootup and shutdown sequence handled from Application Processor SubSystem(APSS).
Signed-off-by Govind Singh <[email protected]>
--- drivers/remoteproc/qcom_q6v5_wcss.c | 570 ++++++++++++++++++++++++++-- 1 file changed, 532 insertions(+), 38 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +532 -38
@@ -4,14 +4,19 @@* Copyright (C) 2014 Sony Mobile Communications AB * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. */ +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> +#include <linux/of_address.h> #include <linux/of_device.h> #include <linux/of_reserved_mem.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <linux/regulator/consumer.h> #include <linux/reset.h> #include <linux/soc/qcom/mdt_loader.h> #include "qcom_common.h"
@@ -24,6 +29,9 @@#define Q6SS_GFMUX_CTL_REG 0x020#define Q6SS_PWR_CTL_REG 0x030#define Q6SS_MEM_PWR_CTL 0x0B0 +#define Q6SS_STRAP_ACC 0x110 +#define Q6SS_CGC_OVERRIDE 0x034 +#define Q6SS_BCR_REG 0x6000/* AXI Halt Register Offsets */ #define AXI_HALTREQ_REG 0x0
@@ -37,14 +45,19 @@#define Q6SS_CORE_ARES BIT(1)#define Q6SS_BUS_ARES_ENABLE BIT(2) +/* Q6SS_BRC_RESET */ +#define Q6SS_BRC_BLK_ARES BIT(0) +/* Q6SS_GFMUX_CTL */ #define Q6SS_CLK_ENABLE BIT(1) +#define Q6SS_SWITCH_CLK_SRC BIT(8)/* Q6SS_PWR_CTL */ #define Q6SS_L2DATA_STBY_N BIT(18)#define Q6SS_SLP_RET_N BIT(19)#define Q6SS_CLAMP_IO BIT(20)#define QDSS_BHS_ON BIT(21) +#define QDSS_Q6_MEMORIES GENMASK(15, 0)/* Q6SS parameters */ #define Q6SS_LDO_BYP BIT(25)
@@ -53,6 +66,7 @@#define Q6SS_CLAMP_QMC_MEM BIT(22)#define HALT_CHECK_MAX_LOOPS 200#define Q6SS_XO_CBCR GENMASK(5, 3) +#define Q6SS_SLEEP_CBCR GENMASK(5, 2)/* Q6SS config/status registers */ #define TCSR_GLOBAL_CFG0 0x0
@@ -71,9 +85,23 @@#define TCSR_WCSS_CLK_MASK 0x1F#define TCSR_WCSS_CLK_ENABLE 0x14 +#define MAX_HALT_REG 3 +enum { +WCSS_IPQ8074 , +WCSS_QCS404 , +}; +struct wcss_data {const char *firmware_name;int crash_reason_smem; +u32 version; +bool aon_reset_required; +bool wcss_q6_reset_required; +const char *ssr_name; +const char *sysmon_name; +int ssctl_id; +const struct rproc_ops *ops; +bool requires_force_stop; };struct q6v5_wcss {
@@ -87,9 +115,29 @@ struct q6v5_wcss {u32 halt_wcss;u32 halt_nc; +struct clk *xo; +struct clk *ahbfabric_cbcr_clk; +struct clk *gcc_abhs_cbcr; +struct clk *gcc_axim_cbcr; +struct clk *lcc_csr_cbcr; +struct clk *ahbs_cbcr; +struct clk *tcm_slave_cbcr; +struct clk *qdsp6ss_abhm_cbcr; +struct clk *qdsp6ss_sleep_cbcr; +struct clk *qdsp6ss_axim_cbcr; +struct clk *qdsp6ss_xo_cbcr; +struct clk *qdsp6ss_core_gfmux; +struct clk *lcc_bcr_sleep; +struct regulator *cx_supply; + +struct qcom_rproc_glink glink_subdev; +struct qcom_rproc_ssr ssr_subdev; +struct qcom_sysmon *sysmon; +struct reset_control *wcss_aon_reset;struct reset_control *wcss_reset;struct reset_control *wcss_q6_reset; +struct reset_control *wcss_q6_bcr_reset;struct qcom_q6v5 q6v5;
@@ -99,6 +147,8 @@ struct q6v5_wcss {size_t mem_size;int crash_reason_smem; +u32 version; +bool requires_force_stop; };static int q6v5_wcss_reset (struct q6v5_wcss *wcss)
@@ -241,6 +291,207 @@ static int q6v5_wcss_start(struct rproc *rproc)return ret; } +static int q6v5_wcss_qcs404_power_on (struct q6v5_wcss *wcss) +{ +unsigned long val; +int ret, idx; + +/* Toggle the restart */ +reset_control_assert (wcss->wcss_reset); +usleep_range (200 ,300 ); +reset_control_deassert (wcss->wcss_reset); +usleep_range (200 ,300 ); + +/* Enable GCC_WDSP_Q6SS_AHBS_CBCR clock */ + ret =clk_prepare_enable (wcss->gcc_abhs_cbcr); +if (ret) +return ret; + +/* Remove reset to the WCNSS QDSP6SS */ +reset_control_deassert (wcss->wcss_q6_bcr_reset); + +/* Enable Q6SSTOP_AHBFABRIC_CBCR clock */ + ret =clk_prepare_enable (wcss->ahbfabric_cbcr_clk); +if (ret) + goto disable_gcc_abhs_cbcr_clk; + +/* Enable the LCCCSR CBC clock, Q6SSTOP_Q6SSTOP_LCC_CSR_CBCR clock */ + ret =clk_prepare_enable (wcss->lcc_csr_cbcr); +if (ret) + goto disable_ahbfabric_cbcr_clk; + +/* Enable the Q6AHBS CBC, Q6SSTOP_Q6SS_AHBS_CBCR clock */ + ret =clk_prepare_enable (wcss->ahbs_cbcr); +if (ret) + goto disable_csr_cbcr_clk; + +/* Enable the TCM slave CBC, Q6SSTOP_Q6SS_TCM_SLAVE_CBCR clock */ + ret =clk_prepare_enable (wcss->tcm_slave_cbcr); +if (ret) + goto disable_ahbs_cbcr_clk; + +/* Enable the Q6SS AHB master CBC, Q6SSTOP_Q6SS_AHBM_CBCR clock */ + ret =clk_prepare_enable (wcss->qdsp6ss_abhm_cbcr); +if (ret) + goto disable_tcm_slave_cbcr_clk; + +/* Enable the Q6SS AXI master CBC, Q6SSTOP_Q6SS_AXIM_CBCR clock */ + ret =clk_prepare_enable (wcss->qdsp6ss_axim_cbcr); +if (ret) + goto disable_abhm_cbcr_clk; + +/* Enable the Q6SS XO CBC */ + val =readl (wcss->reg_base +Q6SS_XO_CBCR ); + val |=BIT (0 ); +writel (val, wcss->reg_base +Q6SS_XO_CBCR ); +/* Read CLKOFF bit to go low indicating CLK is enabled */ + ret =readl_poll_timeout (wcss->reg_base +Q6SS_XO_CBCR , + val, !(val &BIT (31 )),1 , +HALT_CHECK_MAX_LOOPS ); +if (ret) { +dev_err (wcss->dev, +"xo cbcr enabling timed out (rc:%d)\n" , ret); +return ret; + } + +writel (0 , wcss->reg_base +Q6SS_CGC_OVERRIDE ); + +/* Enable QDSP6 sleep clock clock */ + val =readl (wcss->reg_base +Q6SS_SLEEP_CBCR ); + val |=BIT (0 ); +writel (val, wcss->reg_base +Q6SS_SLEEP_CBCR ); + +/* Enable the Enable the Q6 AXI clock, GCC_WDSP_Q6SS_AXIM_CBCR*/ + ret =clk_prepare_enable (wcss->gcc_axim_cbcr); +if (ret) + goto disable_sleep_cbcr_clk; + +/* Assert resets, stop core */ + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val |=Q6SS_CORE_ARES |Q6SS_BUS_ARES_ENABLE |Q6SS_STOP_CORE ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +/* Program the QDSP6SS PWR_CTL register */ +writel (0x01700000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x03700000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x03300000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x033C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +/* +* Enable memories by turning on the QDSP6 memory foot/head switch, one +* bank at a time to avoid in-rush current +*/ +for (idx =28 ; idx >=0 ; idx--) { +writel ((readl (wcss->reg_base +Q6SS_MEM_PWR_CTL ) | + (1 << idx)), wcss->reg_base +Q6SS_MEM_PWR_CTL ); + } + +writel (0x031C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); +writel (0x030C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val &= ~Q6SS_CORE_ARES ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +/* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */ + val =readl (wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + val |=Q6SS_CLK_ENABLE |Q6SS_SWITCH_CLK_SRC ; +writel (val, wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + +/* Enable sleep clock branch needed for BCR circuit */ + ret =clk_prepare_enable (wcss->lcc_bcr_sleep); +if (ret) + goto disable_core_gfmux_clk; + +return 0 ; + +disable_core_gfmux_clk: + val =readl (wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + val &= ~(Q6SS_CLK_ENABLE |Q6SS_SWITCH_CLK_SRC ); +writel (val, wcss->reg_base +Q6SS_GFMUX_CTL_REG ); +clk_disable_unprepare (wcss->gcc_axim_cbcr); +disable_sleep_cbcr_clk: + val =readl (wcss->reg_base +Q6SS_SLEEP_CBCR ); + val &= ~Q6SS_CLK_ENABLE ; +writel (val, wcss->reg_base +Q6SS_SLEEP_CBCR ); + val =readl (wcss->reg_base +Q6SS_XO_CBCR ); + val &= ~Q6SS_CLK_ENABLE ; +writel (val, wcss->reg_base +Q6SS_XO_CBCR ); +clk_disable_unprepare (wcss->qdsp6ss_axim_cbcr); +disable_abhm_cbcr_clk: +clk_disable_unprepare (wcss->qdsp6ss_abhm_cbcr); +disable_tcm_slave_cbcr_clk: +clk_disable_unprepare (wcss->tcm_slave_cbcr); +disable_ahbs_cbcr_clk: +clk_disable_unprepare (wcss->ahbs_cbcr); +disable_csr_cbcr_clk: +clk_disable_unprepare (wcss->lcc_csr_cbcr); +disable_ahbfabric_cbcr_clk: +clk_disable_unprepare (wcss->ahbfabric_cbcr_clk); +disable_gcc_abhs_cbcr_clk: +clk_disable_unprepare (wcss->gcc_abhs_cbcr); + +return ret; +} + +static inline int q6v5_wcss_qcs404_reset (struct q6v5_wcss *wcss) +{ +unsigned long val; + +writel (0x80800000 , wcss->reg_base +Q6SS_STRAP_ACC ); + +/* Start core execution */ + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val &= ~Q6SS_STOP_CORE ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +return 0 ; +} + +static int q6v5_qcs404_wcss_start (struct rproc *rproc) +{ +struct q6v5_wcss *wcss = rproc->priv; +int ret; + + ret =clk_prepare_enable (wcss->xo); +if (ret) +return ret; + + ret =regulator_enable (wcss->cx_supply); +if (ret) + goto disable_xo_clk; + +qcom_q6v5_prepare (&wcss->q6v5); + + ret =q6v5_wcss_qcs404_power_on (wcss); +if (ret) { +dev_err (wcss->dev,"wcss clk_enable failed\n" ); + goto disable_cx_supply; + } + +writel (rproc->bootaddr >>4 , wcss->reg_base +Q6SS_RST_EVB ); + +q6v5_wcss_qcs404_reset (wcss); + + ret =qcom_q6v5_wait_for_start (&wcss->q6v5,5 *HZ ); +if (ret == -ETIMEDOUT ) { +dev_err (wcss->dev,"start timed out\n" ); + goto disable_cx_supply; + } + +return 0 ; + +disable_cx_supply: +regulator_disable (wcss->cx_supply); +disable_xo_clk: +clk_disable_unprepare (wcss->xo); + +return ret; +} +static void q6v5_wcss_halt_axi_port (struct q6v5_wcss *wcss,struct regmap *halt_map,u32 offset)
@@ -275,6 +526,70 @@ static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,regmap_write (halt_map, offset +AXI_HALTREQ_REG ,0 ); } +static int q6v5_qcs404_wcss_shutdown (struct q6v5_wcss *wcss) +{ +unsigned long val; +int ret; + +q6v5_wcss_halt_axi_port (wcss, wcss->halt_map, wcss->halt_wcss); + +/* assert clamps to avoid MX current inrush */ + val =readl (wcss->reg_base +Q6SS_PWR_CTL_REG ); + val |= (Q6SS_CLAMP_IO |Q6SS_CLAMP_WL |Q6SS_CLAMP_QMC_MEM ); +writel (val, wcss->reg_base +Q6SS_PWR_CTL_REG ); + +/* Disable memories by turning off memory foot/headswitch */ +writel ((readl (wcss->reg_base +Q6SS_MEM_PWR_CTL ) & + ~QDSS_Q6_MEMORIES ), + wcss->reg_base +Q6SS_MEM_PWR_CTL ); + +/* Clear the BHS_ON bit */ + val =readl (wcss->reg_base +Q6SS_PWR_CTL_REG ); + val &= ~Q6SS_BHS_ON ; +writel (val, wcss->reg_base +Q6SS_PWR_CTL_REG ); + +clk_disable_unprepare (wcss->ahbfabric_cbcr_clk); +clk_disable_unprepare (wcss->lcc_csr_cbcr); +clk_disable_unprepare (wcss->tcm_slave_cbcr); +clk_disable_unprepare (wcss->qdsp6ss_abhm_cbcr); +clk_disable_unprepare (wcss->qdsp6ss_axim_cbcr); + + val =readl (wcss->reg_base +Q6SS_SLEEP_CBCR ); + val &= ~BIT (0 ); +writel (val, wcss->reg_base +Q6SS_SLEEP_CBCR ); + + val =readl (wcss->reg_base +Q6SS_XO_CBCR ); + val &= ~BIT (0 ); +writel (val, wcss->reg_base +Q6SS_XO_CBCR ); + +clk_disable_unprepare (wcss->ahbs_cbcr); +clk_disable_unprepare (wcss->lcc_bcr_sleep); + + val =readl (wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + val &= ~(Q6SS_CLK_ENABLE |Q6SS_SWITCH_CLK_SRC ); +writel (val, wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + +clk_disable_unprepare (wcss->gcc_abhs_cbcr); + + ret =reset_control_assert (wcss->wcss_reset); +if (ret) { +dev_err (wcss->dev,"wcss_reset failed\n" ); +return ret; + } +usleep_range (200 ,300 ); + + ret =reset_control_deassert (wcss->wcss_reset); +if (ret) { +dev_err (wcss->dev,"wcss_reset failed\n" ); +return ret; + } +usleep_range (200 ,300 ); + +clk_disable_unprepare (wcss->gcc_axim_cbcr); + +return 0 ; +} +static int q6v5_wcss_powerdown (struct q6v5_wcss *wcss) {int ret;
@@ -394,20 +709,28 @@ static int q6v5_wcss_stop(struct rproc *rproc)int ret;/* WCSS powerdown */ - ret =qcom_q6v5_request_stop (&wcss->q6v5); -if (ret == -ETIMEDOUT ) { -dev_err (wcss->dev,"timed out on wait\n" ); -return ret; +if (wcss->requires_force_stop) { + ret =qcom_q6v5_request_stop (&wcss->q6v5); +if (ret == -ETIMEDOUT ) { +dev_err (wcss->dev,"timed out on wait\n" ); +return ret; + } } - ret =q6v5_wcss_powerdown (wcss); -if (ret) -return ret; - -/* Q6 Power down */ - ret =q6v5_q6_powerdown (wcss); -if (ret) -return ret; +if (wcss->version ==WCSS_QCS404 ) { + ret =q6v5_qcs404_wcss_shutdown (wcss); +if (ret) +return ret; + }else { + ret =q6v5_wcss_powerdown (wcss); +if (ret) +return ret; + +/* Q6 Power down */ + ret =q6v5_q6_powerdown (wcss); +if (ret) +return ret; + }qcom_q6v5_unprepare (&wcss->q6v5);
@@ -443,14 +766,26 @@ static const struct rproc_ops q6v5_wcss_ipq8074_ops = { .get_boot_addr = rproc_elf_get_boot_addr, }; -static int q6v5_wcss_init_reset (struct q6v5_wcss *wcss) +static const struct rproc_ops q6v5_wcss_qcs404_ops = { + .start = q6v5_qcs404_wcss_start, + .stop = q6v5_wcss_stop, + .da_to_va = q6v5_wcss_da_to_va, + .load = q6v5_wcss_load, + .get_boot_addr = rproc_elf_get_boot_addr, + .parse_fw = qcom_register_dump_segments, +}; + +static int q6v5_wcss_init_reset (struct q6v5_wcss *wcss, +const struct wcss_data *desc) {struct device *dev = wcss->dev; - wcss->wcss_aon_reset =devm_reset_control_get (dev,"wcss_aon_reset" ); -if (IS_ERR (wcss->wcss_aon_reset)) { -dev_err (wcss->dev,"unable to acquire wcss_aon_reset\n" ); -return PTR_ERR (wcss->wcss_aon_reset); +if (desc->aon_reset_required) { + wcss->wcss_aon_reset =devm_reset_control_get (dev,"wcss_aon_reset" );; +if (IS_ERR (wcss->wcss_aon_reset)) { +dev_err (wcss->dev,"fail to acquire wcss_aon_reset\n" ); +return PTR_ERR (wcss->wcss_aon_reset); + } } wcss->wcss_reset =devm_reset_control_get (dev,"wcss_reset" );
@@ -459,10 +794,18 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)return PTR_ERR (wcss->wcss_reset); } - wcss->wcss_q6_reset =devm_reset_control_get (dev,"wcss_q6_reset" ); -if (IS_ERR (wcss->wcss_q6_reset)) { -dev_err (wcss->dev,"unable to acquire wcss_q6_reset\n" ); -return PTR_ERR (wcss->wcss_q6_reset); +if (desc->wcss_q6_reset_required) { + wcss->wcss_q6_reset =devm_reset_control_get (dev,"wcss_q6_reset" ); +if (IS_ERR (wcss->wcss_q6_reset)) { +dev_err (wcss->dev,"unable to acquire wcss_q6_reset\n" ); +return PTR_ERR (wcss->wcss_q6_reset); + } + } + + wcss->wcss_q6_bcr_reset =devm_reset_control_get_exclusive (dev,"wcss_q6_bcr_reset" ); +if (IS_ERR (wcss->wcss_q6_bcr_reset)) { +dev_err (wcss->dev,"unable to acquire wcss_q6_bcr_reset\n" ); +return PTR_ERR (wcss->wcss_q6_bcr_reset); }return 0 ;
@@ -471,35 +814,48 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)static int q6v5_wcss_init_mmio (struct q6v5_wcss *wcss,struct platform_device *pdev) { -struct of_phandle_args args; +unsigned int halt_reg[MAX_HALT_REG ] = {0 }; +struct device_node *syscon;struct resource *res;int ret; res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"qdsp6" ); - wcss->reg_base =devm_ioremap_resource (&pdev->dev, res); + wcss->reg_base =devm_ioremap (&pdev->dev, res->start, +resource_size (res));if (IS_ERR (wcss->reg_base))return PTR_ERR (wcss->reg_base); - res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"rmb" ); - wcss->rmb_base =devm_ioremap_resource (&pdev->dev, res); -if (IS_ERR (wcss->rmb_base)) -return PTR_ERR (wcss->rmb_base); +if (wcss->version ==WCSS_IPQ8074 ) { + res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"rmb" ); + wcss->rmb_base =devm_ioremap_resource (&pdev->dev, res); +if (IS_ERR (wcss->rmb_base)) +return PTR_ERR (wcss->rmb_base); + } - ret =of_parse_phandle_with_fixed_args (pdev->dev.of_node, -"qcom,halt-regs" ,3 ,0 , &args); -if (ret <0 ) { + syscon =of_parse_phandle (pdev->dev.of_node, +"qcom,halt-regs" ,0 ); +if (!syscon) {dev_err (&pdev->dev,"failed to parse qcom,halt-regs\n" );return -EINVAL ; } - wcss->halt_map =syscon_node_to_regmap (args.np); -of_node_put (args.np); + wcss->halt_map =syscon_node_to_regmap (syscon); +of_node_put (syscon);if (IS_ERR (wcss->halt_map))return PTR_ERR (wcss->halt_map); - wcss->halt_q6 = args.args[0 ]; - wcss->halt_wcss = args.args[1 ]; - wcss->halt_nc = args.args[2 ]; + ret =of_property_read_variable_u32_array (pdev->dev.of_node, +"qcom,halt-regs" , + halt_reg,0 , +MAX_HALT_REG ); +if (ret <0 ) { +dev_err (&pdev->dev,"failed to parse qcom,halt-regs\n" ); +return -EINVAL ; + } + + wcss->halt_q6 = halt_reg[0 ]; + wcss->halt_wcss = halt_reg[1 ]; + wcss->halt_nc = halt_reg[2 ];return 0 ; }
@@ -533,6 +889,107 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)return 0 ; } +static int q6v5_wcss_init_clock (struct q6v5_wcss *wcss) +{ +int ret; + + wcss->xo =devm_clk_get (wcss->dev,"xo" ); +if (IS_ERR (wcss->xo)) { + ret =PTR_ERR (wcss->xo); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get xo clock" ); +return ret; + } + + wcss->gcc_abhs_cbcr =devm_clk_get (wcss->dev,"gcc_abhs_cbcr" ); +if (IS_ERR (wcss->gcc_abhs_cbcr)) { + ret =PTR_ERR (wcss->gcc_abhs_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get gcc abhs clock" ); +return PTR_ERR (wcss->gcc_abhs_cbcr); + } + + wcss->gcc_axim_cbcr =devm_clk_get (wcss->dev,"gcc_axim_cbcr" ); +if (IS_ERR (wcss->gcc_axim_cbcr)) { + ret =PTR_ERR (wcss->gcc_axim_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get gcc axim clock\n" ); +return PTR_ERR (wcss->gcc_axim_cbcr); + } + + wcss->ahbfabric_cbcr_clk =devm_clk_get (wcss->dev, +"lcc_ahbfabric_cbc" ); +if (IS_ERR (wcss->ahbfabric_cbcr_clk)) { + ret =PTR_ERR (wcss->ahbfabric_cbcr_clk); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get ahbfabric clock\n" ); +return PTR_ERR (wcss->ahbfabric_cbcr_clk); + } + + wcss->lcc_csr_cbcr =devm_clk_get (wcss->dev,"tcsr_lcc_cbc" ); +if (IS_ERR (wcss->lcc_csr_cbcr)) { + ret =PTR_ERR (wcss->lcc_csr_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get csr cbcr clk\n" ); +return PTR_ERR (wcss->lcc_csr_cbcr); + } + + wcss->ahbs_cbcr =devm_clk_get (wcss->dev, +"lcc_abhs_cbc" ); +if (IS_ERR (wcss->ahbs_cbcr)) { + ret =PTR_ERR (wcss->ahbs_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get ahbs_cbcr clk\n" ); +return PTR_ERR (wcss->ahbs_cbcr); + } + + wcss->tcm_slave_cbcr =devm_clk_get (wcss->dev, +"lcc_tcm_slave_cbc" ); +if (IS_ERR (wcss->tcm_slave_cbcr)) { + ret =PTR_ERR (wcss->tcm_slave_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get tcm cbcr clk\n" ); +return PTR_ERR (wcss->tcm_slave_cbcr); + } + + wcss->qdsp6ss_abhm_cbcr =devm_clk_get (wcss->dev,"lcc_abhm_cbc" ); +if (IS_ERR (wcss->qdsp6ss_abhm_cbcr)) { + ret =PTR_ERR (wcss->qdsp6ss_abhm_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get abhm cbcr clk\n" ); +return PTR_ERR (wcss->qdsp6ss_abhm_cbcr); + } + + wcss->qdsp6ss_axim_cbcr =devm_clk_get (wcss->dev,"lcc_axim_cbc" ); +if (IS_ERR (wcss->qdsp6ss_axim_cbcr)) { + ret =PTR_ERR (wcss->qdsp6ss_axim_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get axim cbcr clk\n" ); +return PTR_ERR (wcss->qdsp6ss_abhm_cbcr); + } + + wcss->lcc_bcr_sleep =devm_clk_get (wcss->dev,"lcc_bcr_sleep" ); +if (IS_ERR (wcss->lcc_bcr_sleep)) { + ret =PTR_ERR (wcss->lcc_bcr_sleep); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get bcr cbcr clk\n" ); +return PTR_ERR (wcss->lcc_bcr_sleep); + } + +return 0 ; +} + +static int q6v5_wcss_init_regulator (struct q6v5_wcss *wcss) +{ + wcss->cx_supply =devm_regulator_get (wcss->dev,"cx" ); +if (IS_ERR (wcss->cx_supply)) +return PTR_ERR (wcss->cx_supply); + +regulator_set_load (wcss->cx_supply,100000 ); + +return 0 ; +} +static int q6v5_wcss_probe (struct platform_device *pdev) {const struct wcss_data *desc;
@@ -544,7 +1001,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (!desc)return -EINVAL ; - rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, + rproc =rproc_alloc (&pdev->dev, pdev->name, desc->ops, desc->firmware_name,sizeof (*wcss));if (!rproc) {dev_err (&pdev->dev,"failed to allocate rproc\n" );
@@ -553,7 +1010,10 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss = rproc->priv; wcss->dev = &pdev->dev; - wcss->crash_reason_smem = desc->crash_reason_smem; + wcss->version = desc->version; + + wcss->version = desc->version; + wcss->requires_force_stop = desc->requires_force_stop; ret =q6v5_wcss_init_mmio (wcss, pdev);if (ret)
@@ -563,7 +1023,17 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (ret) goto free_rproc; - ret =q6v5_wcss_init_reset (wcss); +if (wcss->version ==WCSS_QCS404 ) { + ret =q6v5_wcss_init_clock (wcss); +if (ret) + goto free_rproc; + + ret =q6v5_wcss_init_regulator (wcss); +if (ret) + goto free_rproc; + } + + ret =q6v5_wcss_init_reset (wcss, desc);if (ret) goto free_rproc;
@@ -572,6 +1042,12 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (ret) goto free_rproc; +qcom_add_glink_subdev (rproc, &wcss->glink_subdev); +qcom_add_ssr_subdev (rproc, &wcss->ssr_subdev, desc->ssr_name); + wcss->sysmon =qcom_add_sysmon_subdev (rproc, + desc->sysmon_name, + desc->ssctl_id); + ret =rproc_add (rproc);if (ret) goto free_rproc;
@@ -599,10 +1075,28 @@ static int q6v5_wcss_remove(struct platform_device *pdev)static const struct wcss_data wcss_ipq8074_res_init = { .firmware_name ="IPQ8074/q6_fw.mdt" , .crash_reason_smem =WCSS_CRASH_REASON , + .aon_reset_required = true, + .wcss_q6_reset_required = true, + .ops = &q6v5_wcss_ipq8074_ops, + .requires_force_stop = true, +}; + +static const struct wcss_data wcss_qcs404_res_init = { + .crash_reason_smem =WCSS_CRASH_REASON , + .firmware_name ="wcnss.mdt" , + .version =WCSS_QCS404 , + .aon_reset_required = false, + .wcss_q6_reset_required = false, + .ssr_name ="mpss" , + .sysmon_name ="wcnss" , + .ssctl_id =0x12 , + .ops = &q6v5_wcss_qcs404_ops, + .requires_force_stop = false, };static const struct of_device_id q6v5_wcss_of_match[] = { { .compatible ="qcom,ipq8074-wcss-pil" , .data = &wcss_ipq8074_res_init }, + { .compatible ="qcom,qcs404-wcss-pil" , .data = &wcss_qcs404_res_init }, { }, };
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v5 7/7 remoteproc: qcom: wcss: explicitly request exclusive reset control
In reply to Govind SinghUse request exclusive reset control for wcss reset controls.
Signed-off-by Govind Singh <[email protected]>
--- drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +3 -3
@@ -781,21 +781,21 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss,struct device *dev = wcss->dev;if (desc->aon_reset_required) { - wcss->wcss_aon_reset =devm_reset_control_get (dev,"wcss_aon_reset" );; + wcss->wcss_aon_reset =devm_reset_control_get_exclusive (dev,"wcss_aon_reset" );;if (IS_ERR (wcss->wcss_aon_reset)) {dev_err (wcss->dev,"fail to acquire wcss_aon_reset\n" );return PTR_ERR (wcss->wcss_aon_reset); } } - wcss->wcss_reset =devm_reset_control_get (dev,"wcss_reset" ); + wcss->wcss_reset =devm_reset_control_get_exclusive (dev,"wcss_reset" );if (IS_ERR (wcss->wcss_reset)) {dev_err (wcss->dev,"unable to acquire wcss_reset\n" );return PTR_ERR (wcss->wcss_reset); }if (desc->wcss_q6_reset_required) { - wcss->wcss_q6_reset =devm_reset_control_get (dev,"wcss_q6_reset" ); + wcss->wcss_q6_reset =devm_reset_control_get_exclusive (dev,"wcss_q6_reset" );if (IS_ERR (wcss->wcss_q6_reset)) {dev_err (wcss->dev,"unable to acquire wcss_q6_reset\n" );return PTR_ERR (wcss->wcss_q6_reset);
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
v6 cover Add non PAS wcss Q6 support for QCS404
In reply to Govind SinghChanges since v5:
Rebased all the unmerged patches on top of linux-5.8-rc3 Added dt-binding for qcom,qcs404-wcss-pil Removed typo
Changes since v4:
removed QDSP6SS clock controls and moved to wcss rproc. renamed wcsccc to q6sstopcc. cleanup/refactoring.
Changes since v3:
dt binding cleanup.
Fixed remoteproc recovery.
Added remoteproc dump support.
wcsscc cleanup/refactoring.
Changes since v2:
Removed unused properties.
Refactored code to have common logic b/w ipq8074 and QCS404, wherever possible. Added compatible example.
Removed wcss-protected bool.
Changes since v1:
Corrected clock names as per comments in v1 patch.
Govind Singh (4):
remoteproc: qcom: wcss: populate hardcoded param using driver data
dt-bindings: remoteproc: qcom: Add Q6V5 Modem PIL binding for QCS404
remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
remoteproc: qcom: wcss: explicitly request exclusive reset control
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 9 + drivers/remoteproc/qcom_q6v5_wcss.c | 596 +++++++++++++++++++-- 2 files changed, 563 insertions(+), 42 deletions(-)
Signature · 1 line
2.7.4
PATCH v6 1/4 remoteproc: qcom: wcss: populate hardcoded param using driver data
From: Govind Singh <[email protected]>
Q6 based WiFi fw loading is supported across different targets, ex: IPQ8074/QCS404. In order to support different fw names/pas id etc, populate hardcoded param using driver data.
Signed-off-by Govind Singh <[email protected]>
[rebased on top of 5.8-rc3]
Signed-off-by Gokul Sriram Palanisamy <[email protected]>
--- drivers/remoteproc/qcom_q6v5_wcss.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +26 -5
@@ -8,6 +8,7 @@#include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> +#include <linux/of_device.h> #include <linux/of_reserved_mem.h> #include <linux/platform_device.h> #include <linux/regmap.h>
@@ -70,6 +71,11 @@#define TCSR_WCSS_CLK_MASK 0x1F#define TCSR_WCSS_CLK_ENABLE 0x14 +struct wcss_data { +const char *firmware_name; +int crash_reason_smem; +}; +struct q6v5_wcss {struct device *dev;
@@ -92,6 +98,8 @@ struct q6v5_wcss {void *mem_region;size_t mem_size; +int crash_reason_smem; +struct qcom_rproc_glink glink_subdev;struct qcom_rproc_ssr ssr_subdev; };
@@ -430,7 +438,7 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) wcss->mem_size, &wcss->mem_reloc); } -static const struct rproc_ops q6v5_wcss_ops = { +static const struct rproc_ops q6v5_wcss_ipq8074_ops = { .start = q6v5_wcss_start, .stop = q6v5_wcss_stop, .da_to_va = q6v5_wcss_da_to_va,
@@ -530,12 +538,17 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)static int q6v5_wcss_probe (struct platform_device *pdev) { +const struct wcss_data *desc;struct q6v5_wcss *wcss;struct rproc *rproc;int ret; - rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ops, -"IPQ8074/q6_fw.mdt" ,sizeof (*wcss)); + desc =of_device_get_match_data (&pdev->dev); +if (!desc) +return -EINVAL ; + + rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, + desc->firmware_name,sizeof (*wcss));if (!rproc) {dev_err (&pdev->dev,"failed to allocate rproc\n" );return -ENOMEM ;
@@ -543,6 +556,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss = rproc->priv; wcss->dev = &pdev->dev; + wcss->crash_reason_smem = desc->crash_reason_smem; ret =q6v5_wcss_init_mmio (wcss, pdev);if (ret)
@@ -556,7 +570,8 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (ret) goto free_rproc; - ret =qcom_q6v5_init (&wcss->q6v5, pdev, rproc,WCSS_CRASH_REASON ,NULL ); + ret =qcom_q6v5_init (&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, +NULL );if (ret) goto free_rproc;
@@ -587,8 +602,14 @@ static int q6v5_wcss_remove(struct platform_device *pdev)return 0 ; } +static const struct wcss_data wcss_ipq8074_res_init = { + .firmware_name ="IPQ8074/q6_fw.mdt" , + .crash_reason_smem =WCSS_CRASH_REASON , +}; +static const struct of_device_id q6v5_wcss_of_match[] = { - { .compatible ="qcom,ipq8074-wcss-pil" }, + { .compatible ="qcom,ipq8074-wcss-pil" , .data = &wcss_ipq8074_res_init }, + { }, };MODULE_DEVICE_TABLE (of, q6v5_wcss_of_match);
Signature · 1 line
2.7.4
PATCH v6 2/4 dt-bindings: remoteproc: qcom: Add Q6V5 Modem PIL binding for QCS404
In reply to Gokul Sriram PalanisamyFrom: Govind Singh <[email protected]>
Add a new modem compatible string for Qualcomm QCS404 SoCs
Signed-off-by Govind Singh <[email protected]>
[rebased on top of 5.8-rc3]
Signed-off-by Gokul Sriram Palanisamy <[email protected]>
--- Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 9 +++++++++ 1 file changed, 9 insertions(+)
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +9 -0
@@ -9,6 +9,7 @@ on the Qualcomm Hexagon core. Definition: must be one of: "qcom,q6v5-pil", "qcom,ipq8074-wcss-pil" + "qcom,qcs404-wcss-pil" "qcom,msm8916-mss-pil", "qcom,msm8974-mss-pil" "qcom,msm8996-mss-pil"
@@ -39,6 +40,7 @@ on the Qualcomm Hexagon core. string: qcom,q6v5-pil: qcom,ipq8074-wcss-pil: + qcom,qcs404-wcss-pil: qcom,msm8916-mss-pil: qcom,msm8974-mss-pil: must be "wdog", "fatal", "ready", "handover", "stop-ack"
@@ -67,6 +69,11 @@ on the Qualcomm Hexagon core. Definition: The clocks needed depend on the compatible string: qcom,ipq8074-wcss-pil: no clock names required + qcom,qcs404-wcss-pil: + must be "xo", "gcc_abhs_cbcr", "gcc_abhs_cbcr", + "gcc_axim_cbcr", "lcc_ahbfabric_cbc", "tcsr_lcc_cbc", + "lcc_abhs_cbc", "lcc_tcm_slave_cbc", "lcc_abhm_cbc", + "lcc_axim_cbc", "lcc_bcr_sleep" qcom,q6v5-pil: qcom,msm8916-mss-pil: qcom,msm8974-mss-pil:
@@ -154,6 +161,8 @@ For the compatible string below the following supplies are required: qcom,msm8916-mss-pil: qcom,msm8974-mss-pil: no power-domain names required + qcom,qcs404-wcss-pil: + must be "cx" qcom,msm8996-mss-pil: qcom,msm8998-mss-pil: must be "cx", "mx"
Signature · 1 line
2.7.4
PATCH v6 3/4 remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
In reply to Gokul Sriram PalanisamyFrom: Govind Singh <[email protected]>
Add non PAS WCSS remoteproc driver support for QCS404 SOC. Add WCSS q6 bootup and shutdown sequence handled from Application Processor SubSystem(APSS).
Signed-off-by Govind Singh <[email protected]>
[rebased on top of 5.8-rc3]
Signed-off-by Gokul Sriram Palanisamy <[email protected]>
--- drivers/remoteproc/qcom_q6v5_wcss.c | 567 +++++++++++++++++++++++++++++++++--- 1 file changed, 529 insertions(+), 38 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +529 -38
@@ -4,14 +4,19 @@* Copyright (C) 2014 Sony Mobile Communications AB * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. */ +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> +#include <linux/of_address.h> #include <linux/of_device.h> #include <linux/of_reserved_mem.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <linux/regulator/consumer.h> #include <linux/reset.h> #include <linux/soc/qcom/mdt_loader.h> #include "qcom_common.h"
@@ -24,6 +29,9 @@#define Q6SS_GFMUX_CTL_REG 0x020#define Q6SS_PWR_CTL_REG 0x030#define Q6SS_MEM_PWR_CTL 0x0B0 +#define Q6SS_STRAP_ACC 0x110 +#define Q6SS_CGC_OVERRIDE 0x034 +#define Q6SS_BCR_REG 0x6000/* AXI Halt Register Offsets */ #define AXI_HALTREQ_REG 0x0
@@ -37,14 +45,19 @@#define Q6SS_CORE_ARES BIT(1)#define Q6SS_BUS_ARES_ENABLE BIT(2) +/* Q6SS_BRC_RESET */ +#define Q6SS_BRC_BLK_ARES BIT(0) +/* Q6SS_GFMUX_CTL */ #define Q6SS_CLK_ENABLE BIT(1) +#define Q6SS_SWITCH_CLK_SRC BIT(8)/* Q6SS_PWR_CTL */ #define Q6SS_L2DATA_STBY_N BIT(18)#define Q6SS_SLP_RET_N BIT(19)#define Q6SS_CLAMP_IO BIT(20)#define QDSS_BHS_ON BIT(21) +#define QDSS_Q6_MEMORIES GENMASK(15, 0)/* Q6SS parameters */ #define Q6SS_LDO_BYP BIT(25)
@@ -53,6 +66,7 @@#define Q6SS_CLAMP_QMC_MEM BIT(22)#define HALT_CHECK_MAX_LOOPS 200#define Q6SS_XO_CBCR GENMASK(5, 3) +#define Q6SS_SLEEP_CBCR GENMASK(5, 2)/* Q6SS config/status registers */ #define TCSR_GLOBAL_CFG0 0x0
@@ -71,9 +85,23 @@#define TCSR_WCSS_CLK_MASK 0x1F#define TCSR_WCSS_CLK_ENABLE 0x14 +#define MAX_HALT_REG 3 +enum { +WCSS_IPQ8074 , +WCSS_QCS404 , +}; +struct wcss_data {const char *firmware_name;int crash_reason_smem; +u32 version; +bool aon_reset_required; +bool wcss_q6_reset_required; +const char *ssr_name; +const char *sysmon_name; +int ssctl_id; +const struct rproc_ops *ops; +bool requires_force_stop; };struct q6v5_wcss {
@@ -87,9 +115,29 @@ struct q6v5_wcss {u32 halt_wcss;u32 halt_nc; +struct clk *xo; +struct clk *ahbfabric_cbcr_clk; +struct clk *gcc_abhs_cbcr; +struct clk *gcc_axim_cbcr; +struct clk *lcc_csr_cbcr; +struct clk *ahbs_cbcr; +struct clk *tcm_slave_cbcr; +struct clk *qdsp6ss_abhm_cbcr; +struct clk *qdsp6ss_sleep_cbcr; +struct clk *qdsp6ss_axim_cbcr; +struct clk *qdsp6ss_xo_cbcr; +struct clk *qdsp6ss_core_gfmux; +struct clk *lcc_bcr_sleep; +struct regulator *cx_supply; + +struct qcom_rproc_glink glink_subdev; +struct qcom_rproc_ssr ssr_subdev; +struct qcom_sysmon *sysmon; +struct reset_control *wcss_aon_reset;struct reset_control *wcss_reset;struct reset_control *wcss_q6_reset; +struct reset_control *wcss_q6_bcr_reset;struct qcom_q6v5 q6v5;
@@ -99,6 +147,8 @@ struct q6v5_wcss {size_t mem_size;int crash_reason_smem; +u32 version; +bool requires_force_stop;struct qcom_rproc_glink glink_subdev;struct qcom_rproc_ssr ssr_subdev;
@@ -244,6 +294,207 @@ static int q6v5_wcss_start(struct rproc *rproc)return ret; } +static int q6v5_wcss_qcs404_power_on (struct q6v5_wcss *wcss) +{ +unsigned long val; +int ret, idx; + +/* Toggle the restart */ +reset_control_assert (wcss->wcss_reset); +usleep_range (200 ,300 ); +reset_control_deassert (wcss->wcss_reset); +usleep_range (200 ,300 ); + +/* Enable GCC_WDSP_Q6SS_AHBS_CBCR clock */ + ret =clk_prepare_enable (wcss->gcc_abhs_cbcr); +if (ret) +return ret; + +/* Remove reset to the WCNSS QDSP6SS */ +reset_control_deassert (wcss->wcss_q6_bcr_reset); + +/* Enable Q6SSTOP_AHBFABRIC_CBCR clock */ + ret =clk_prepare_enable (wcss->ahbfabric_cbcr_clk); +if (ret) + goto disable_gcc_abhs_cbcr_clk; + +/* Enable the LCCCSR CBC clock, Q6SSTOP_Q6SSTOP_LCC_CSR_CBCR clock */ + ret =clk_prepare_enable (wcss->lcc_csr_cbcr); +if (ret) + goto disable_ahbfabric_cbcr_clk; + +/* Enable the Q6AHBS CBC, Q6SSTOP_Q6SS_AHBS_CBCR clock */ + ret =clk_prepare_enable (wcss->ahbs_cbcr); +if (ret) + goto disable_csr_cbcr_clk; + +/* Enable the TCM slave CBC, Q6SSTOP_Q6SS_TCM_SLAVE_CBCR clock */ + ret =clk_prepare_enable (wcss->tcm_slave_cbcr); +if (ret) + goto disable_ahbs_cbcr_clk; + +/* Enable the Q6SS AHB master CBC, Q6SSTOP_Q6SS_AHBM_CBCR clock */ + ret =clk_prepare_enable (wcss->qdsp6ss_abhm_cbcr); +if (ret) + goto disable_tcm_slave_cbcr_clk; + +/* Enable the Q6SS AXI master CBC, Q6SSTOP_Q6SS_AXIM_CBCR clock */ + ret =clk_prepare_enable (wcss->qdsp6ss_axim_cbcr); +if (ret) + goto disable_abhm_cbcr_clk; + +/* Enable the Q6SS XO CBC */ + val =readl (wcss->reg_base +Q6SS_XO_CBCR ); + val |=BIT (0 ); +writel (val, wcss->reg_base +Q6SS_XO_CBCR ); +/* Read CLKOFF bit to go low indicating CLK is enabled */ + ret =readl_poll_timeout (wcss->reg_base +Q6SS_XO_CBCR , + val, !(val &BIT (31 )),1 , +HALT_CHECK_MAX_LOOPS ); +if (ret) { +dev_err (wcss->dev, +"xo cbcr enabling timed out (rc:%d)\n" , ret); +return ret; + } + +writel (0 , wcss->reg_base +Q6SS_CGC_OVERRIDE ); + +/* Enable QDSP6 sleep clock clock */ + val =readl (wcss->reg_base +Q6SS_SLEEP_CBCR ); + val |=BIT (0 ); +writel (val, wcss->reg_base +Q6SS_SLEEP_CBCR ); + +/* Enable the Enable the Q6 AXI clock, GCC_WDSP_Q6SS_AXIM_CBCR*/ + ret =clk_prepare_enable (wcss->gcc_axim_cbcr); +if (ret) + goto disable_sleep_cbcr_clk; + +/* Assert resets, stop core */ + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val |=Q6SS_CORE_ARES |Q6SS_BUS_ARES_ENABLE |Q6SS_STOP_CORE ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +/* Program the QDSP6SS PWR_CTL register */ +writel (0x01700000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x03700000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x03300000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x033C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +/* +* Enable memories by turning on the QDSP6 memory foot/head switch, one +* bank at a time to avoid in-rush current +*/ +for (idx =28 ; idx >=0 ; idx--) { +writel ((readl (wcss->reg_base +Q6SS_MEM_PWR_CTL ) | + (1 << idx)), wcss->reg_base +Q6SS_MEM_PWR_CTL ); + } + +writel (0x031C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); +writel (0x030C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val &= ~Q6SS_CORE_ARES ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +/* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */ + val =readl (wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + val |=Q6SS_CLK_ENABLE |Q6SS_SWITCH_CLK_SRC ; +writel (val, wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + +/* Enable sleep clock branch needed for BCR circuit */ + ret =clk_prepare_enable (wcss->lcc_bcr_sleep); +if (ret) + goto disable_core_gfmux_clk; + +return 0 ; + +disable_core_gfmux_clk: + val =readl (wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + val &= ~(Q6SS_CLK_ENABLE |Q6SS_SWITCH_CLK_SRC ); +writel (val, wcss->reg_base +Q6SS_GFMUX_CTL_REG ); +clk_disable_unprepare (wcss->gcc_axim_cbcr); +disable_sleep_cbcr_clk: + val =readl (wcss->reg_base +Q6SS_SLEEP_CBCR ); + val &= ~Q6SS_CLK_ENABLE ; +writel (val, wcss->reg_base +Q6SS_SLEEP_CBCR ); + val =readl (wcss->reg_base +Q6SS_XO_CBCR ); + val &= ~Q6SS_CLK_ENABLE ; +writel (val, wcss->reg_base +Q6SS_XO_CBCR ); +clk_disable_unprepare (wcss->qdsp6ss_axim_cbcr); +disable_abhm_cbcr_clk: +clk_disable_unprepare (wcss->qdsp6ss_abhm_cbcr); +disable_tcm_slave_cbcr_clk: +clk_disable_unprepare (wcss->tcm_slave_cbcr); +disable_ahbs_cbcr_clk: +clk_disable_unprepare (wcss->ahbs_cbcr); +disable_csr_cbcr_clk: +clk_disable_unprepare (wcss->lcc_csr_cbcr); +disable_ahbfabric_cbcr_clk: +clk_disable_unprepare (wcss->ahbfabric_cbcr_clk); +disable_gcc_abhs_cbcr_clk: +clk_disable_unprepare (wcss->gcc_abhs_cbcr); + +return ret; +} + +static inline int q6v5_wcss_qcs404_reset (struct q6v5_wcss *wcss) +{ +unsigned long val; + +writel (0x80800000 , wcss->reg_base +Q6SS_STRAP_ACC ); + +/* Start core execution */ + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val &= ~Q6SS_STOP_CORE ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +return 0 ; +} + +static int q6v5_qcs404_wcss_start (struct rproc *rproc) +{ +struct q6v5_wcss *wcss = rproc->priv; +int ret; + + ret =clk_prepare_enable (wcss->xo); +if (ret) +return ret; + + ret =regulator_enable (wcss->cx_supply); +if (ret) + goto disable_xo_clk; + +qcom_q6v5_prepare (&wcss->q6v5); + + ret =q6v5_wcss_qcs404_power_on (wcss); +if (ret) { +dev_err (wcss->dev,"wcss clk_enable failed\n" ); + goto disable_cx_supply; + } + +writel (rproc->bootaddr >>4 , wcss->reg_base +Q6SS_RST_EVB ); + +q6v5_wcss_qcs404_reset (wcss); + + ret =qcom_q6v5_wait_for_start (&wcss->q6v5,5 *HZ ); +if (ret == -ETIMEDOUT ) { +dev_err (wcss->dev,"start timed out\n" ); + goto disable_cx_supply; + } + +return 0 ; + +disable_cx_supply: +regulator_disable (wcss->cx_supply); +disable_xo_clk: +clk_disable_unprepare (wcss->xo); + +return ret; +} +static void q6v5_wcss_halt_axi_port (struct q6v5_wcss *wcss,struct regmap *halt_map,u32 offset)
@@ -278,6 +529,70 @@ static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,regmap_write (halt_map, offset +AXI_HALTREQ_REG ,0 ); } +static int q6v5_qcs404_wcss_shutdown (struct q6v5_wcss *wcss) +{ +unsigned long val; +int ret; + +q6v5_wcss_halt_axi_port (wcss, wcss->halt_map, wcss->halt_wcss); + +/* assert clamps to avoid MX current inrush */ + val =readl (wcss->reg_base +Q6SS_PWR_CTL_REG ); + val |= (Q6SS_CLAMP_IO |Q6SS_CLAMP_WL |Q6SS_CLAMP_QMC_MEM ); +writel (val, wcss->reg_base +Q6SS_PWR_CTL_REG ); + +/* Disable memories by turning off memory foot/headswitch */ +writel ((readl (wcss->reg_base +Q6SS_MEM_PWR_CTL ) & + ~QDSS_Q6_MEMORIES ), + wcss->reg_base +Q6SS_MEM_PWR_CTL ); + +/* Clear the BHS_ON bit */ + val =readl (wcss->reg_base +Q6SS_PWR_CTL_REG ); + val &= ~Q6SS_BHS_ON ; +writel (val, wcss->reg_base +Q6SS_PWR_CTL_REG ); + +clk_disable_unprepare (wcss->ahbfabric_cbcr_clk); +clk_disable_unprepare (wcss->lcc_csr_cbcr); +clk_disable_unprepare (wcss->tcm_slave_cbcr); +clk_disable_unprepare (wcss->qdsp6ss_abhm_cbcr); +clk_disable_unprepare (wcss->qdsp6ss_axim_cbcr); + + val =readl (wcss->reg_base +Q6SS_SLEEP_CBCR ); + val &= ~BIT (0 ); +writel (val, wcss->reg_base +Q6SS_SLEEP_CBCR ); + + val =readl (wcss->reg_base +Q6SS_XO_CBCR ); + val &= ~BIT (0 ); +writel (val, wcss->reg_base +Q6SS_XO_CBCR ); + +clk_disable_unprepare (wcss->ahbs_cbcr); +clk_disable_unprepare (wcss->lcc_bcr_sleep); + + val =readl (wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + val &= ~(Q6SS_CLK_ENABLE |Q6SS_SWITCH_CLK_SRC ); +writel (val, wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + +clk_disable_unprepare (wcss->gcc_abhs_cbcr); + + ret =reset_control_assert (wcss->wcss_reset); +if (ret) { +dev_err (wcss->dev,"wcss_reset failed\n" ); +return ret; + } +usleep_range (200 ,300 ); + + ret =reset_control_deassert (wcss->wcss_reset); +if (ret) { +dev_err (wcss->dev,"wcss_reset failed\n" ); +return ret; + } +usleep_range (200 ,300 ); + +clk_disable_unprepare (wcss->gcc_axim_cbcr); + +return 0 ; +} +static int q6v5_wcss_powerdown (struct q6v5_wcss *wcss) {int ret;
@@ -397,20 +712,28 @@ static int q6v5_wcss_stop(struct rproc *rproc)int ret;/* WCSS powerdown */ - ret =qcom_q6v5_request_stop (&wcss->q6v5); -if (ret == -ETIMEDOUT ) { -dev_err (wcss->dev,"timed out on wait\n" ); -return ret; +if (wcss->requires_force_stop) { + ret =qcom_q6v5_request_stop (&wcss->q6v5); +if (ret == -ETIMEDOUT ) { +dev_err (wcss->dev,"timed out on wait\n" ); +return ret; + } } - ret =q6v5_wcss_powerdown (wcss); -if (ret) -return ret; - -/* Q6 Power down */ - ret =q6v5_q6_powerdown (wcss); -if (ret) -return ret; +if (wcss->version ==WCSS_QCS404 ) { + ret =q6v5_qcs404_wcss_shutdown (wcss); +if (ret) +return ret; + }else { + ret =q6v5_wcss_powerdown (wcss); +if (ret) +return ret; + +/* Q6 Power down */ + ret =q6v5_q6_powerdown (wcss); +if (ret) +return ret; + }qcom_q6v5_unprepare (&wcss->q6v5);
@@ -446,14 +769,26 @@ static const struct rproc_ops q6v5_wcss_ipq8074_ops = { .get_boot_addr = rproc_elf_get_boot_addr, }; -static int q6v5_wcss_init_reset (struct q6v5_wcss *wcss) +static const struct rproc_ops q6v5_wcss_qcs404_ops = { + .start = q6v5_qcs404_wcss_start, + .stop = q6v5_wcss_stop, + .da_to_va = q6v5_wcss_da_to_va, + .load = q6v5_wcss_load, + .get_boot_addr = rproc_elf_get_boot_addr, + .parse_fw = qcom_register_dump_segments, +}; + +static int q6v5_wcss_init_reset (struct q6v5_wcss *wcss, +const struct wcss_data *desc) {struct device *dev = wcss->dev; - wcss->wcss_aon_reset =devm_reset_control_get (dev,"wcss_aon_reset" ); -if (IS_ERR (wcss->wcss_aon_reset)) { -dev_err (wcss->dev,"unable to acquire wcss_aon_reset\n" ); -return PTR_ERR (wcss->wcss_aon_reset); +if (desc->aon_reset_required) { + wcss->wcss_aon_reset =devm_reset_control_get (dev,"wcss_aon_reset" ); +if (IS_ERR (wcss->wcss_aon_reset)) { +dev_err (wcss->dev,"fail to acquire wcss_aon_reset\n" ); +return PTR_ERR (wcss->wcss_aon_reset); + } } wcss->wcss_reset =devm_reset_control_get (dev,"wcss_reset" );
@@ -462,10 +797,18 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)return PTR_ERR (wcss->wcss_reset); } - wcss->wcss_q6_reset =devm_reset_control_get (dev,"wcss_q6_reset" ); -if (IS_ERR (wcss->wcss_q6_reset)) { -dev_err (wcss->dev,"unable to acquire wcss_q6_reset\n" ); -return PTR_ERR (wcss->wcss_q6_reset); +if (desc->wcss_q6_reset_required) { + wcss->wcss_q6_reset =devm_reset_control_get (dev,"wcss_q6_reset" ); +if (IS_ERR (wcss->wcss_q6_reset)) { +dev_err (wcss->dev,"unable to acquire wcss_q6_reset\n" ); +return PTR_ERR (wcss->wcss_q6_reset); + } + } + + wcss->wcss_q6_bcr_reset =devm_reset_control_get_exclusive (dev,"wcss_q6_bcr_reset" ); +if (IS_ERR (wcss->wcss_q6_bcr_reset)) { +dev_err (wcss->dev,"unable to acquire wcss_q6_bcr_reset\n" ); +return PTR_ERR (wcss->wcss_q6_bcr_reset); }return 0 ;
@@ -474,35 +817,48 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)static int q6v5_wcss_init_mmio (struct q6v5_wcss *wcss,struct platform_device *pdev) { -struct of_phandle_args args; +unsigned int halt_reg[MAX_HALT_REG ] = {0 }; +struct device_node *syscon;struct resource *res;int ret; res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"qdsp6" ); - wcss->reg_base =devm_ioremap_resource (&pdev->dev, res); + wcss->reg_base =devm_ioremap (&pdev->dev, res->start, +resource_size (res));if (IS_ERR (wcss->reg_base))return PTR_ERR (wcss->reg_base); - res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"rmb" ); - wcss->rmb_base =devm_ioremap_resource (&pdev->dev, res); -if (IS_ERR (wcss->rmb_base)) -return PTR_ERR (wcss->rmb_base); +if (wcss->version ==WCSS_IPQ8074 ) { + res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"rmb" ); + wcss->rmb_base =devm_ioremap_resource (&pdev->dev, res); +if (IS_ERR (wcss->rmb_base)) +return PTR_ERR (wcss->rmb_base); + } - ret =of_parse_phandle_with_fixed_args (pdev->dev.of_node, -"qcom,halt-regs" ,3 ,0 , &args); -if (ret <0 ) { + syscon =of_parse_phandle (pdev->dev.of_node, +"qcom,halt-regs" ,0 ); +if (!syscon) {dev_err (&pdev->dev,"failed to parse qcom,halt-regs\n" );return -EINVAL ; } - wcss->halt_map =syscon_node_to_regmap (args.np); -of_node_put (args.np); + wcss->halt_map =syscon_node_to_regmap (syscon); +of_node_put (syscon);if (IS_ERR (wcss->halt_map))return PTR_ERR (wcss->halt_map); - wcss->halt_q6 = args.args[0 ]; - wcss->halt_wcss = args.args[1 ]; - wcss->halt_nc = args.args[2 ]; + ret =of_property_read_variable_u32_array (pdev->dev.of_node, +"qcom,halt-regs" , + halt_reg,0 , +MAX_HALT_REG ); +if (ret <0 ) { +dev_err (&pdev->dev,"failed to parse qcom,halt-regs\n" ); +return -EINVAL ; + } + + wcss->halt_q6 = halt_reg[0 ]; + wcss->halt_wcss = halt_reg[1 ]; + wcss->halt_nc = halt_reg[2 ];return 0 ; }
@@ -536,6 +892,107 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)return 0 ; } +static int q6v5_wcss_init_clock (struct q6v5_wcss *wcss) +{ +int ret; + + wcss->xo =devm_clk_get (wcss->dev,"xo" ); +if (IS_ERR (wcss->xo)) { + ret =PTR_ERR (wcss->xo); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get xo clock" ); +return ret; + } + + wcss->gcc_abhs_cbcr =devm_clk_get (wcss->dev,"gcc_abhs_cbcr" ); +if (IS_ERR (wcss->gcc_abhs_cbcr)) { + ret =PTR_ERR (wcss->gcc_abhs_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get gcc abhs clock" ); +return PTR_ERR (wcss->gcc_abhs_cbcr); + } + + wcss->gcc_axim_cbcr =devm_clk_get (wcss->dev,"gcc_axim_cbcr" ); +if (IS_ERR (wcss->gcc_axim_cbcr)) { + ret =PTR_ERR (wcss->gcc_axim_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get gcc axim clock\n" ); +return PTR_ERR (wcss->gcc_axim_cbcr); + } + + wcss->ahbfabric_cbcr_clk =devm_clk_get (wcss->dev, +"lcc_ahbfabric_cbc" ); +if (IS_ERR (wcss->ahbfabric_cbcr_clk)) { + ret =PTR_ERR (wcss->ahbfabric_cbcr_clk); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get ahbfabric clock\n" ); +return PTR_ERR (wcss->ahbfabric_cbcr_clk); + } + + wcss->lcc_csr_cbcr =devm_clk_get (wcss->dev,"tcsr_lcc_cbc" ); +if (IS_ERR (wcss->lcc_csr_cbcr)) { + ret =PTR_ERR (wcss->lcc_csr_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get csr cbcr clk\n" ); +return PTR_ERR (wcss->lcc_csr_cbcr); + } + + wcss->ahbs_cbcr =devm_clk_get (wcss->dev, +"lcc_abhs_cbc" ); +if (IS_ERR (wcss->ahbs_cbcr)) { + ret =PTR_ERR (wcss->ahbs_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get ahbs_cbcr clk\n" ); +return PTR_ERR (wcss->ahbs_cbcr); + } + + wcss->tcm_slave_cbcr =devm_clk_get (wcss->dev, +"lcc_tcm_slave_cbc" ); +if (IS_ERR (wcss->tcm_slave_cbcr)) { + ret =PTR_ERR (wcss->tcm_slave_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get tcm cbcr clk\n" ); +return PTR_ERR (wcss->tcm_slave_cbcr); + } + + wcss->qdsp6ss_abhm_cbcr =devm_clk_get (wcss->dev,"lcc_abhm_cbc" ); +if (IS_ERR (wcss->qdsp6ss_abhm_cbcr)) { + ret =PTR_ERR (wcss->qdsp6ss_abhm_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get abhm cbcr clk\n" ); +return PTR_ERR (wcss->qdsp6ss_abhm_cbcr); + } + + wcss->qdsp6ss_axim_cbcr =devm_clk_get (wcss->dev,"lcc_axim_cbc" ); +if (IS_ERR (wcss->qdsp6ss_axim_cbcr)) { + ret =PTR_ERR (wcss->qdsp6ss_axim_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get axim cbcr clk\n" ); +return PTR_ERR (wcss->qdsp6ss_abhm_cbcr); + } + + wcss->lcc_bcr_sleep =devm_clk_get (wcss->dev,"lcc_bcr_sleep" ); +if (IS_ERR (wcss->lcc_bcr_sleep)) { + ret =PTR_ERR (wcss->lcc_bcr_sleep); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get bcr cbcr clk\n" ); +return PTR_ERR (wcss->lcc_bcr_sleep); + } + +return 0 ; +} + +static int q6v5_wcss_init_regulator (struct q6v5_wcss *wcss) +{ + wcss->cx_supply =devm_regulator_get (wcss->dev,"cx" ); +if (IS_ERR (wcss->cx_supply)) +return PTR_ERR (wcss->cx_supply); + +regulator_set_load (wcss->cx_supply,100000 ); + +return 0 ; +} +static int q6v5_wcss_probe (struct platform_device *pdev) {const struct wcss_data *desc;
@@ -547,7 +1004,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (!desc)return -EINVAL ; - rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, + rproc =rproc_alloc (&pdev->dev, pdev->name, desc->ops, desc->firmware_name,sizeof (*wcss));if (!rproc) {dev_err (&pdev->dev,"failed to allocate rproc\n" );
@@ -556,7 +1013,10 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss = rproc->priv; wcss->dev = &pdev->dev; - wcss->crash_reason_smem = desc->crash_reason_smem; + wcss->version = desc->version; + + wcss->version = desc->version; + wcss->requires_force_stop = desc->requires_force_stop; ret =q6v5_wcss_init_mmio (wcss, pdev);if (ret)
@@ -566,7 +1026,17 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (ret) goto free_rproc; - ret =q6v5_wcss_init_reset (wcss); +if (wcss->version ==WCSS_QCS404 ) { + ret =q6v5_wcss_init_clock (wcss); +if (ret) + goto free_rproc; + + ret =q6v5_wcss_init_regulator (wcss); +if (ret) + goto free_rproc; + } + + ret =q6v5_wcss_init_reset (wcss, desc);if (ret) goto free_rproc;
@@ -577,6 +1047,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev)qcom_add_glink_subdev (rproc, &wcss->glink_subdev,"q6wcss" );qcom_add_ssr_subdev (rproc, &wcss->ssr_subdev,"q6wcss" ); + wcss->sysmon =qcom_add_sysmon_subdev (rproc, + desc->sysmon_name, + desc->ssctl_id); ret =rproc_add (rproc);if (ret)
@@ -605,10 +1078,28 @@ static int q6v5_wcss_remove(struct platform_device *pdev)static const struct wcss_data wcss_ipq8074_res_init = { .firmware_name ="IPQ8074/q6_fw.mdt" , .crash_reason_smem =WCSS_CRASH_REASON , + .aon_reset_required = true, + .wcss_q6_reset_required = true, + .ops = &q6v5_wcss_ipq8074_ops, + .requires_force_stop = true, +}; + +static const struct wcss_data wcss_qcs404_res_init = { + .crash_reason_smem =WCSS_CRASH_REASON , + .firmware_name ="wcnss.mdt" , + .version =WCSS_QCS404 , + .aon_reset_required = false, + .wcss_q6_reset_required = false, + .ssr_name ="mpss" , + .sysmon_name ="wcnss" , + .ssctl_id =0x12 , + .ops = &q6v5_wcss_qcs404_ops, + .requires_force_stop = false, };static const struct of_device_id q6v5_wcss_of_match[] = { { .compatible ="qcom,ipq8074-wcss-pil" , .data = &wcss_ipq8074_res_init }, + { .compatible ="qcom,qcs404-wcss-pil" , .data = &wcss_qcs404_res_init }, { }, };
Signature · 1 line
2.7.4
PATCH v6 4/4 remoteproc: qcom: wcss: explicitly request exclusive reset control
In reply to Gokul Sriram PalanisamyFrom: Govind Singh <[email protected]>
Use request exclusive reset control for wcss reset controls.
Signed-off-by Govind Singh <[email protected]>
--- drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +3 -3
@@ -784,21 +784,21 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss,struct device *dev = wcss->dev;if (desc->aon_reset_required) { - wcss->wcss_aon_reset =devm_reset_control_get (dev,"wcss_aon_reset" ); + wcss->wcss_aon_reset =devm_reset_control_get_exclusive (dev,"wcss_aon_reset" );if (IS_ERR (wcss->wcss_aon_reset)) {dev_err (wcss->dev,"fail to acquire wcss_aon_reset\n" );return PTR_ERR (wcss->wcss_aon_reset); } } - wcss->wcss_reset =devm_reset_control_get (dev,"wcss_reset" ); + wcss->wcss_reset =devm_reset_control_get_exclusive (dev,"wcss_reset" );if (IS_ERR (wcss->wcss_reset)) {dev_err (wcss->dev,"unable to acquire wcss_reset\n" );return PTR_ERR (wcss->wcss_reset); }if (desc->wcss_q6_reset_required) { - wcss->wcss_q6_reset =devm_reset_control_get (dev,"wcss_q6_reset" ); + wcss->wcss_q6_reset =devm_reset_control_get_exclusive (dev,"wcss_q6_reset" );if (IS_ERR (wcss->wcss_q6_reset)) {dev_err (wcss->dev,"unable to acquire wcss_q6_reset\n" );return PTR_ERR (wcss->wcss_q6_reset);
Signature · 1 line
2.7.4
v7 cover Add non PAS wcss Q6 support for QCS404
In reply to Govind SinghChanges since v6:
Removed duplicate structure entry added during rebase in v5
Changes since v5:
Rebased all the unmerged patches on top of linux-5.8-rc3 Added dt-binding for qcom,qcs404-wcss-pil Removed typo
Changes since v4:
removed QDSP6SS clock controls and moved to wcss rproc. renamed wcsccc to q6sstopcc. cleanup/refactoring.
Changes since v3:
dt binding cleanup.
Fixed remoteproc recovery.
Added remoteproc dump support.
wcsscc cleanup/refactoring.
Changes since v2:
Removed unused properties.
Refactored code to have common logic b/w ipq8074 and QCS404, wherever possible. Added compatible example.
Removed wcss-protected bool.
Changes since v1:
Corrected clock names as per comments in v1 patch.
Govind Singh (4):
remoteproc: qcom: wcss: populate hardcoded param using driver data
dt-bindings: remoteproc: qcom: Add Q6V5 Modem PIL binding for QCS404
remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
remoteproc: qcom: wcss: explicitly request exclusive reset control
.../devicetree/bindings/remoteproc/qcom,q6v5.txt | 9 + drivers/remoteproc/qcom_q6v5_wcss.c | 593 +++++++++++++++++++-- 2 files changed, 560 insertions(+), 42 deletions(-)
Signature · 1 line
2.7.4
PATCH v7 1/4 remoteproc: qcom: wcss: populate hardcoded param using driver data
From: Govind Singh <[email protected]>
Q6 based WiFi fw loading is supported across different targets, ex: IPQ8074/QCS404. In order to support different fw names/pas id etc, populate hardcoded param using driver data.
Signed-off-by Govind Singh <[email protected]>
[rebased on top of 5.8-rc3]
Signed-off-by Gokul Sriram Palanisamy <[email protected]>
--- drivers/remoteproc/qcom_q6v5_wcss.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +26 -5
@@ -8,6 +8,7 @@#include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> +#include <linux/of_device.h> #include <linux/of_reserved_mem.h> #include <linux/platform_device.h> #include <linux/regmap.h>
@@ -70,6 +71,11 @@#define TCSR_WCSS_CLK_MASK 0x1F#define TCSR_WCSS_CLK_ENABLE 0x14 +struct wcss_data { +const char *firmware_name; +int crash_reason_smem; +}; +struct q6v5_wcss {struct device *dev;
@@ -92,6 +98,8 @@ struct q6v5_wcss {void *mem_region;size_t mem_size; +int crash_reason_smem; +struct qcom_rproc_glink glink_subdev;struct qcom_rproc_ssr ssr_subdev; };
@@ -430,7 +438,7 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) wcss->mem_size, &wcss->mem_reloc); } -static const struct rproc_ops q6v5_wcss_ops = { +static const struct rproc_ops q6v5_wcss_ipq8074_ops = { .start = q6v5_wcss_start, .stop = q6v5_wcss_stop, .da_to_va = q6v5_wcss_da_to_va,
@@ -530,12 +538,17 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)static int q6v5_wcss_probe (struct platform_device *pdev) { +const struct wcss_data *desc;struct q6v5_wcss *wcss;struct rproc *rproc;int ret; - rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ops, -"IPQ8074/q6_fw.mdt" ,sizeof (*wcss)); + desc =of_device_get_match_data (&pdev->dev); +if (!desc) +return -EINVAL ; + + rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, + desc->firmware_name,sizeof (*wcss));if (!rproc) {dev_err (&pdev->dev,"failed to allocate rproc\n" );return -ENOMEM ;
@@ -543,6 +556,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss = rproc->priv; wcss->dev = &pdev->dev; + wcss->crash_reason_smem = desc->crash_reason_smem; ret =q6v5_wcss_init_mmio (wcss, pdev);if (ret)
@@ -556,7 +570,8 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (ret) goto free_rproc; - ret =qcom_q6v5_init (&wcss->q6v5, pdev, rproc,WCSS_CRASH_REASON ,NULL ); + ret =qcom_q6v5_init (&wcss->q6v5, pdev, rproc, desc->crash_reason_smem, +NULL );if (ret) goto free_rproc;
@@ -587,8 +602,14 @@ static int q6v5_wcss_remove(struct platform_device *pdev)return 0 ; } +static const struct wcss_data wcss_ipq8074_res_init = { + .firmware_name ="IPQ8074/q6_fw.mdt" , + .crash_reason_smem =WCSS_CRASH_REASON , +}; +static const struct of_device_id q6v5_wcss_of_match[] = { - { .compatible ="qcom,ipq8074-wcss-pil" }, + { .compatible ="qcom,ipq8074-wcss-pil" , .data = &wcss_ipq8074_res_init }, + { }, };MODULE_DEVICE_TABLE (of, q6v5_wcss_of_match);
Signature · 1 line
2.7.4
Stephen Boyd
maintainerRe: [v7 1/4] remoteproc: qcom: wcss: populate hardcoded param using driver data
Quoting Gokul Sriram Palanisamy (2020-07-03 01:58:39)
Quoted 9 lines
From: Govind Singh <[email protected]>
Q6 based WiFi fw loading is supported across different targets, ex: IPQ8074/QCS404. In order to support different fw names/pas id etc, populate hardcoded param using driver data.
Signed-off-by Govind Singh <[email protected]>[rebased on top of 5.8-rc3]
This tag is not really useful and doesn't follow the style of having your email prefix the text. I'd expect to see
[[email protected]: made some sort of change]
Quoted 10 lines
Signed-off-by Gokul Sriram Palanisamy <[email protected]>--- drivers/remoteproc/qcom_q6v5_wcss.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-)drivers/remoteproc/qcom_q6v5_wcss.c +0
-0
drivers/remoteproc/qcom_q6v5_wcss.c line 76
Quoted 6 lines
drivers/remoteproc/qcom_q6v5_wcss.c +3
-0@@ -70,6 +71,11 @@#define TCSR_WCSS_CLK_MASK 0x1F#define TCSR_WCSS_CLK_ENABLE 0x14 +struct wcss_data { +const char *firmware_name; +int crash_reason_smem;
Is it signed for some reason?
drivers/remoteproc/qcom_q6v5_wcss.c struct q6v5_wcss { · line 102
Quoted 11 lines
drivers/remoteproc/qcom_q6v5_wcss.c +4
-0+}; +struct q6v5_wcss {struct device *dev;@@ -92,6 +98,8 @@ struct q6v5_wcss {void *mem_region;size_t mem_size; +int crash_reason_smem; +
Same question, why not unsigned?
Quoted 14 lines
drivers/remoteproc/qcom_q6v5_wcss.c +1
-1struct qcom_rproc_glink glink_subdev;struct qcom_rproc_ssr ssr_subdev; };@@ -430,7 +438,7 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) wcss->mem_size, &wcss->mem_reloc); } -static const struct rproc_ops q6v5_wcss_ops = { +static const struct rproc_ops q6v5_wcss_ipq8074_ops = { .start = q6v5_wcss_start, .stop = q6v5_wcss_stop, .da_to_va = q6v5_wcss_da_to_va,@@ -530,12 +538,17 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)
drivers/remoteproc/qcom_q6v5_wcss.c static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) · line 546
Quoted 10 lines
drivers/remoteproc/qcom_q6v5_wcss.c +2
-2static int q6v5_wcss_probe (struct platform_device *pdev) { +const struct wcss_data *desc;struct q6v5_wcss *wcss;struct rproc *rproc;int ret; - rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ops, -"IPQ8074/q6_fw.mdt" ,sizeof (*wcss)); + desc =of_device_get_match_data (&pdev->dev);
Use device_get_match_data() and drop the of_device.h include.
Quoted 11 lines
drivers/remoteproc/qcom_q6v5_wcss.c +5
-0+if (!desc) +return -EINVAL ; + + rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, + desc->firmware_name,sizeof (*wcss));if (!rproc) {dev_err (&pdev->dev,"failed to allocate rproc\n" );return -ENOMEM ;@@ -587,8 +602,14 @@ static int q6v5_wcss_remove(struct platform_device *pdev)return 0 ; }
drivers/remoteproc/qcom_q6v5_wcss.c static int q6v5_wcss_remove(struct platform_device *pdev) · line 612
Quoted 10 lines
drivers/remoteproc/qcom_q6v5_wcss.c +7
-1+static const struct wcss_data wcss_ipq8074_res_init = { + .firmware_name ="IPQ8074/q6_fw.mdt" , + .crash_reason_smem =WCSS_CRASH_REASON , +}; +static const struct of_device_id q6v5_wcss_of_match[] = { - { .compatible ="qcom,ipq8074-wcss-pil" }, + { .compatible ="qcom,ipq8074-wcss-pil" , .data = &wcss_ipq8074_res_init }, +
Please remove this extra newline.
Quoted 3 lines
drivers/remoteproc/qcom_q6v5_wcss.c +0
-0{ }, };MODULE_DEVICE_TABLE (of, q6v5_wcss_of_match);
Re: [v7 1/4] remoteproc: qcom: wcss: populate hardcoded param using driver data
Thanks for your comments Stephen.
Will address your comments below and re-submit.
Quoted 30 lines · Stephen Boyd
Quoting Gokul Sriram Palanisamy (2020-07-03 01:58:39)
Quoted 9 lines
From: Govind Singh <[email protected]>
Q6 based WiFi fw loading is supported across different targets, ex: IPQ8074/QCS404. In order to support different fw names/pas id etc, populate hardcoded param using driver data.
Signed-off-by Govind Singh <[email protected]>[rebased on top of 5.8-rc3]This tag is not really useful and doesn't follow the style of having your email prefix the text. I'd expect to see
[[email protected]: made some sort of change]
Quoted 14 lines
Signed-off-by Gokul Sriram Palanisamy <[email protected]>--- drivers/remoteproc/qcom_q6v5_wcss.c | 31 ++++++++++++++++++++++++++----- 1 file changed, 26 insertions(+), 5 deletions(-)drivers/remoteproc/qcom_q6v5_wcss.c +0
-0@@ -70,6 +71,11 @@#define TCSR_WCSS_CLK_MASK 0x1F#define TCSR_WCSS_CLK_ENABLE 0x14
Quoted 5 lines
drivers/remoteproc/qcom_q6v5_wcss.c line 76
Quoted 3 lines
drivers/remoteproc/qcom_q6v5_wcss.c +3
-0+struct wcss_data { +const char *firmware_name; +int crash_reason_smem;Is it signed for some reason?
Can be unsigned. Will update.
Quoted 6 lines
Quoted 6 lines
drivers/remoteproc/qcom_q6v5_wcss.c +2
-0+}; +struct q6v5_wcss {struct device *dev;
Quoted 8 lines
drivers/remoteproc/qcom_q6v5_wcss.c struct q6v5_wcss { · line 102
Quoted 6 lines
drivers/remoteproc/qcom_q6v5_wcss.c +2
-0@@ -92,6 +98,8 @@ struct q6v5_wcss {void *mem_region;size_t mem_size; +int crash_reason_smem; +Same question, why not unsigned?
Can be unsigned. Will update.
Quoted 25 lines
Quoted 25 lines
drivers/remoteproc/qcom_q6v5_wcss.c +1
-1struct qcom_rproc_glink glink_subdev;struct qcom_rproc_ssr ssr_subdev; };@@ -430,7 +438,7 @@ static int q6v5_wcss_load(struct rproc *rproc, const struct firmware *fw) wcss->mem_size, &wcss->mem_reloc); } -static const struct rproc_ops q6v5_wcss_ops = { +static const struct rproc_ops q6v5_wcss_ipq8074_ops = { .start = q6v5_wcss_start,.stop = q6v5_wcss_stop, .da_to_va = q6v5_wcss_da_to_va,drivers/remoteproc/qcom_q6v5_wcss.c +1
-0@@ -530,12 +538,17 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)static int q6v5_wcss_probe (struct platform_device *pdev) { +const struct wcss_data *desc;struct q6v5_wcss *wcss;struct rproc *rproc;int ret;
Quoted 5 lines
drivers/remoteproc/qcom_q6v5_wcss.c static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss) · line 546
Quoted 3 lines
drivers/remoteproc/qcom_q6v5_wcss.c +1
-2- rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ops, -"IPQ8074/q6_fw.mdt" ,sizeof (*wcss)); + desc =of_device_get_match_data (&pdev->dev);Use
device_get_match_data()and drop theof_device.hinclude.
ok, will do.
Quoted 15 lines
Quoted 15 lines
drivers/remoteproc/qcom_q6v5_wcss.c +5
-0+if (!desc) +return -EINVAL ; + + rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, + desc->firmware_name,sizeof (*wcss));if (!rproc) {dev_err(&pdev->dev, "failed to allocate rproc\n"); return -ENOMEM;drivers/remoteproc/qcom_q6v5_wcss.c +0
-0@@ -587,8 +602,14 @@ static int q6v5_wcss_remove(struct platform_device *pdev)return 0 ; }
Quoted 12 lines
drivers/remoteproc/qcom_q6v5_wcss.c static int q6v5_wcss_remove(struct platform_device *pdev) · line 612
Quoted 10 lines
drivers/remoteproc/qcom_q6v5_wcss.c +7
-1+static const struct wcss_data wcss_ipq8074_res_init = { + .firmware_name ="IPQ8074/q6_fw.mdt" , + .crash_reason_smem =WCSS_CRASH_REASON , +}; +static const struct of_device_id q6v5_wcss_of_match[] = { - { .compatible ="qcom,ipq8074-wcss-pil" }, + { .compatible ="qcom,ipq8074-wcss-pil" , .data = &wcss_ipq8074_res_init }, +Please remove this extra newline.
ok. Will do.
Quoted 4 lines
Quoted 4 lines
drivers/remoteproc/qcom_q6v5_wcss.c +0
-0{ },};
MODULE_DEVICE_TABLE(of, q6v5_wcss_of_match);
PATCH v7 2/4 dt-bindings: remoteproc: qcom: Add Q6V5 Modem PIL binding for QCS404
In reply to Gokul Sriram PalanisamyFrom: Govind Singh <[email protected]>
Add a new modem compatible string for Qualcomm QCS404 SoCs
Signed-off-by Govind Singh <[email protected]>
[rebased on top of 5.8-rc3]
Signed-off-by Gokul Sriram Palanisamy <[email protected]>
--- Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 9 +++++++++ 1 file changed, 9 insertions(+)
Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt +9 -0
@@ -9,6 +9,7 @@ on the Qualcomm Hexagon core. Definition: must be one of: "qcom,q6v5-pil", "qcom,ipq8074-wcss-pil" + "qcom,qcs404-wcss-pil" "qcom,msm8916-mss-pil", "qcom,msm8974-mss-pil" "qcom,msm8996-mss-pil"
@@ -39,6 +40,7 @@ on the Qualcomm Hexagon core. string: qcom,q6v5-pil: qcom,ipq8074-wcss-pil: + qcom,qcs404-wcss-pil: qcom,msm8916-mss-pil: qcom,msm8974-mss-pil: must be "wdog", "fatal", "ready", "handover", "stop-ack"
@@ -67,6 +69,11 @@ on the Qualcomm Hexagon core. Definition: The clocks needed depend on the compatible string: qcom,ipq8074-wcss-pil: no clock names required + qcom,qcs404-wcss-pil: + must be "xo", "gcc_abhs_cbcr", "gcc_abhs_cbcr", + "gcc_axim_cbcr", "lcc_ahbfabric_cbc", "tcsr_lcc_cbc", + "lcc_abhs_cbc", "lcc_tcm_slave_cbc", "lcc_abhm_cbc", + "lcc_axim_cbc", "lcc_bcr_sleep" qcom,q6v5-pil: qcom,msm8916-mss-pil: qcom,msm8974-mss-pil:
@@ -154,6 +161,8 @@ For the compatible string below the following supplies are required: qcom,msm8916-mss-pil: qcom,msm8974-mss-pil: no power-domain names required + qcom,qcs404-wcss-pil: + must be "cx" qcom,msm8996-mss-pil: qcom,msm8998-mss-pil: must be "cx", "mx"
Signature · 1 line
2.7.4
Re: [v7 2/4] dt-bindings: remoteproc: qcom: Add Q6V5 Modem PIL binding for QCS404
Quoted 11 lines · Gokul Sriram Palanisamy
From: Govind Singh <[email protected]>
Add a new modem compatible string for Qualcomm QCS404 SoCs
Signed-off-by Govind Singh <[email protected]>[rebased on top of 5.8-rc3]Signed-off-by Gokul Sriram Palanisamy <[email protected]>--- Documentation/devicetree/bindings/remoteproc/qcom,q6v5.txt | 9 +++++++++ 1 file changed, 9 insertions(+)
Acked-by Rob Herring <[email protected]>
PATCH v7 3/4 remoteproc: qcom: wcss: Add non pas wcss Q6 support for QCS404
In reply to Gokul Sriram PalanisamyFrom: Govind Singh <[email protected]>
Add non PAS WCSS remoteproc driver support for QCS404 SOC. Add WCSS q6 bootup and shutdown sequence handled from Application Processor SubSystem(APSS).
Signed-off-by Govind Singh <[email protected]>
[rebased on top of 5.8-rc3]
Signed-off-by Gokul Sriram Palanisamy <[email protected]>
--- drivers/remoteproc/qcom_q6v5_wcss.c | 564 +++++++++++++++++++++++++++++++++--- 1 file changed, 526 insertions(+), 38 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +526 -38
@@ -4,14 +4,19 @@* Copyright (C) 2014 Sony Mobile Communications AB * Copyright (c) 2012-2018, The Linux Foundation. All rights reserved. */ +#include <linux/clk.h> +#include <linux/delay.h> +#include <linux/io.h> #include <linux/iopoll.h> #include <linux/kernel.h> #include <linux/mfd/syscon.h> #include <linux/module.h> +#include <linux/of_address.h> #include <linux/of_device.h> #include <linux/of_reserved_mem.h> #include <linux/platform_device.h> #include <linux/regmap.h> +#include <linux/regulator/consumer.h> #include <linux/reset.h> #include <linux/soc/qcom/mdt_loader.h> #include "qcom_common.h"
@@ -24,6 +29,9 @@#define Q6SS_GFMUX_CTL_REG 0x020#define Q6SS_PWR_CTL_REG 0x030#define Q6SS_MEM_PWR_CTL 0x0B0 +#define Q6SS_STRAP_ACC 0x110 +#define Q6SS_CGC_OVERRIDE 0x034 +#define Q6SS_BCR_REG 0x6000/* AXI Halt Register Offsets */ #define AXI_HALTREQ_REG 0x0
@@ -37,14 +45,19 @@#define Q6SS_CORE_ARES BIT(1)#define Q6SS_BUS_ARES_ENABLE BIT(2) +/* Q6SS_BRC_RESET */ +#define Q6SS_BRC_BLK_ARES BIT(0) +/* Q6SS_GFMUX_CTL */ #define Q6SS_CLK_ENABLE BIT(1) +#define Q6SS_SWITCH_CLK_SRC BIT(8)/* Q6SS_PWR_CTL */ #define Q6SS_L2DATA_STBY_N BIT(18)#define Q6SS_SLP_RET_N BIT(19)#define Q6SS_CLAMP_IO BIT(20)#define QDSS_BHS_ON BIT(21) +#define QDSS_Q6_MEMORIES GENMASK(15, 0)/* Q6SS parameters */ #define Q6SS_LDO_BYP BIT(25)
@@ -53,6 +66,7 @@#define Q6SS_CLAMP_QMC_MEM BIT(22)#define HALT_CHECK_MAX_LOOPS 200#define Q6SS_XO_CBCR GENMASK(5, 3) +#define Q6SS_SLEEP_CBCR GENMASK(5, 2)/* Q6SS config/status registers */ #define TCSR_GLOBAL_CFG0 0x0
@@ -71,9 +85,23 @@#define TCSR_WCSS_CLK_MASK 0x1F#define TCSR_WCSS_CLK_ENABLE 0x14 +#define MAX_HALT_REG 3 +enum { +WCSS_IPQ8074 , +WCSS_QCS404 , +}; +struct wcss_data {const char *firmware_name;int crash_reason_smem; +u32 version; +bool aon_reset_required; +bool wcss_q6_reset_required; +const char *ssr_name; +const char *sysmon_name; +int ssctl_id; +const struct rproc_ops *ops; +bool requires_force_stop; };struct q6v5_wcss {
@@ -87,9 +115,26 @@ struct q6v5_wcss {u32 halt_wcss;u32 halt_nc; +struct clk *xo; +struct clk *ahbfabric_cbcr_clk; +struct clk *gcc_abhs_cbcr; +struct clk *gcc_axim_cbcr; +struct clk *lcc_csr_cbcr; +struct clk *ahbs_cbcr; +struct clk *tcm_slave_cbcr; +struct clk *qdsp6ss_abhm_cbcr; +struct clk *qdsp6ss_sleep_cbcr; +struct clk *qdsp6ss_axim_cbcr; +struct clk *qdsp6ss_xo_cbcr; +struct clk *qdsp6ss_core_gfmux; +struct clk *lcc_bcr_sleep; +struct regulator *cx_supply; +struct qcom_sysmon *sysmon; +struct reset_control *wcss_aon_reset;struct reset_control *wcss_reset;struct reset_control *wcss_q6_reset; +struct reset_control *wcss_q6_bcr_reset;struct qcom_q6v5 q6v5;
@@ -99,6 +144,8 @@ struct q6v5_wcss {size_t mem_size;int crash_reason_smem; +u32 version; +bool requires_force_stop;struct qcom_rproc_glink glink_subdev;struct qcom_rproc_ssr ssr_subdev;
@@ -244,6 +291,207 @@ static int q6v5_wcss_start(struct rproc *rproc)return ret; } +static int q6v5_wcss_qcs404_power_on (struct q6v5_wcss *wcss) +{ +unsigned long val; +int ret, idx; + +/* Toggle the restart */ +reset_control_assert (wcss->wcss_reset); +usleep_range (200 ,300 ); +reset_control_deassert (wcss->wcss_reset); +usleep_range (200 ,300 ); + +/* Enable GCC_WDSP_Q6SS_AHBS_CBCR clock */ + ret =clk_prepare_enable (wcss->gcc_abhs_cbcr); +if (ret) +return ret; + +/* Remove reset to the WCNSS QDSP6SS */ +reset_control_deassert (wcss->wcss_q6_bcr_reset); + +/* Enable Q6SSTOP_AHBFABRIC_CBCR clock */ + ret =clk_prepare_enable (wcss->ahbfabric_cbcr_clk); +if (ret) + goto disable_gcc_abhs_cbcr_clk; + +/* Enable the LCCCSR CBC clock, Q6SSTOP_Q6SSTOP_LCC_CSR_CBCR clock */ + ret =clk_prepare_enable (wcss->lcc_csr_cbcr); +if (ret) + goto disable_ahbfabric_cbcr_clk; + +/* Enable the Q6AHBS CBC, Q6SSTOP_Q6SS_AHBS_CBCR clock */ + ret =clk_prepare_enable (wcss->ahbs_cbcr); +if (ret) + goto disable_csr_cbcr_clk; + +/* Enable the TCM slave CBC, Q6SSTOP_Q6SS_TCM_SLAVE_CBCR clock */ + ret =clk_prepare_enable (wcss->tcm_slave_cbcr); +if (ret) + goto disable_ahbs_cbcr_clk; + +/* Enable the Q6SS AHB master CBC, Q6SSTOP_Q6SS_AHBM_CBCR clock */ + ret =clk_prepare_enable (wcss->qdsp6ss_abhm_cbcr); +if (ret) + goto disable_tcm_slave_cbcr_clk; + +/* Enable the Q6SS AXI master CBC, Q6SSTOP_Q6SS_AXIM_CBCR clock */ + ret =clk_prepare_enable (wcss->qdsp6ss_axim_cbcr); +if (ret) + goto disable_abhm_cbcr_clk; + +/* Enable the Q6SS XO CBC */ + val =readl (wcss->reg_base +Q6SS_XO_CBCR ); + val |=BIT (0 ); +writel (val, wcss->reg_base +Q6SS_XO_CBCR ); +/* Read CLKOFF bit to go low indicating CLK is enabled */ + ret =readl_poll_timeout (wcss->reg_base +Q6SS_XO_CBCR , + val, !(val &BIT (31 )),1 , +HALT_CHECK_MAX_LOOPS ); +if (ret) { +dev_err (wcss->dev, +"xo cbcr enabling timed out (rc:%d)\n" , ret); +return ret; + } + +writel (0 , wcss->reg_base +Q6SS_CGC_OVERRIDE ); + +/* Enable QDSP6 sleep clock clock */ + val =readl (wcss->reg_base +Q6SS_SLEEP_CBCR ); + val |=BIT (0 ); +writel (val, wcss->reg_base +Q6SS_SLEEP_CBCR ); + +/* Enable the Enable the Q6 AXI clock, GCC_WDSP_Q6SS_AXIM_CBCR*/ + ret =clk_prepare_enable (wcss->gcc_axim_cbcr); +if (ret) + goto disable_sleep_cbcr_clk; + +/* Assert resets, stop core */ + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val |=Q6SS_CORE_ARES |Q6SS_BUS_ARES_ENABLE |Q6SS_STOP_CORE ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +/* Program the QDSP6SS PWR_CTL register */ +writel (0x01700000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x03700000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x03300000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +writel (0x033C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + +/* +* Enable memories by turning on the QDSP6 memory foot/head switch, one +* bank at a time to avoid in-rush current +*/ +for (idx =28 ; idx >=0 ; idx--) { +writel ((readl (wcss->reg_base +Q6SS_MEM_PWR_CTL ) | + (1 << idx)), wcss->reg_base +Q6SS_MEM_PWR_CTL ); + } + +writel (0x031C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); +writel (0x030C0000 , wcss->reg_base +Q6SS_PWR_CTL_REG ); + + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val &= ~Q6SS_CORE_ARES ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +/* Enable the Q6 core clock at the GFM, Q6SSTOP_QDSP6SS_GFMUX_CTL */ + val =readl (wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + val |=Q6SS_CLK_ENABLE |Q6SS_SWITCH_CLK_SRC ; +writel (val, wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + +/* Enable sleep clock branch needed for BCR circuit */ + ret =clk_prepare_enable (wcss->lcc_bcr_sleep); +if (ret) + goto disable_core_gfmux_clk; + +return 0 ; + +disable_core_gfmux_clk: + val =readl (wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + val &= ~(Q6SS_CLK_ENABLE |Q6SS_SWITCH_CLK_SRC ); +writel (val, wcss->reg_base +Q6SS_GFMUX_CTL_REG ); +clk_disable_unprepare (wcss->gcc_axim_cbcr); +disable_sleep_cbcr_clk: + val =readl (wcss->reg_base +Q6SS_SLEEP_CBCR ); + val &= ~Q6SS_CLK_ENABLE ; +writel (val, wcss->reg_base +Q6SS_SLEEP_CBCR ); + val =readl (wcss->reg_base +Q6SS_XO_CBCR ); + val &= ~Q6SS_CLK_ENABLE ; +writel (val, wcss->reg_base +Q6SS_XO_CBCR ); +clk_disable_unprepare (wcss->qdsp6ss_axim_cbcr); +disable_abhm_cbcr_clk: +clk_disable_unprepare (wcss->qdsp6ss_abhm_cbcr); +disable_tcm_slave_cbcr_clk: +clk_disable_unprepare (wcss->tcm_slave_cbcr); +disable_ahbs_cbcr_clk: +clk_disable_unprepare (wcss->ahbs_cbcr); +disable_csr_cbcr_clk: +clk_disable_unprepare (wcss->lcc_csr_cbcr); +disable_ahbfabric_cbcr_clk: +clk_disable_unprepare (wcss->ahbfabric_cbcr_clk); +disable_gcc_abhs_cbcr_clk: +clk_disable_unprepare (wcss->gcc_abhs_cbcr); + +return ret; +} + +static inline int q6v5_wcss_qcs404_reset (struct q6v5_wcss *wcss) +{ +unsigned long val; + +writel (0x80800000 , wcss->reg_base +Q6SS_STRAP_ACC ); + +/* Start core execution */ + val =readl (wcss->reg_base +Q6SS_RESET_REG ); + val &= ~Q6SS_STOP_CORE ; +writel (val, wcss->reg_base +Q6SS_RESET_REG ); + +return 0 ; +} + +static int q6v5_qcs404_wcss_start (struct rproc *rproc) +{ +struct q6v5_wcss *wcss = rproc->priv; +int ret; + + ret =clk_prepare_enable (wcss->xo); +if (ret) +return ret; + + ret =regulator_enable (wcss->cx_supply); +if (ret) + goto disable_xo_clk; + +qcom_q6v5_prepare (&wcss->q6v5); + + ret =q6v5_wcss_qcs404_power_on (wcss); +if (ret) { +dev_err (wcss->dev,"wcss clk_enable failed\n" ); + goto disable_cx_supply; + } + +writel (rproc->bootaddr >>4 , wcss->reg_base +Q6SS_RST_EVB ); + +q6v5_wcss_qcs404_reset (wcss); + + ret =qcom_q6v5_wait_for_start (&wcss->q6v5,5 *HZ ); +if (ret == -ETIMEDOUT ) { +dev_err (wcss->dev,"start timed out\n" ); + goto disable_cx_supply; + } + +return 0 ; + +disable_cx_supply: +regulator_disable (wcss->cx_supply); +disable_xo_clk: +clk_disable_unprepare (wcss->xo); + +return ret; +} +static void q6v5_wcss_halt_axi_port (struct q6v5_wcss *wcss,struct regmap *halt_map,u32 offset)
@@ -278,6 +526,70 @@ static void q6v5_wcss_halt_axi_port(struct q6v5_wcss *wcss,regmap_write (halt_map, offset +AXI_HALTREQ_REG ,0 ); } +static int q6v5_qcs404_wcss_shutdown (struct q6v5_wcss *wcss) +{ +unsigned long val; +int ret; + +q6v5_wcss_halt_axi_port (wcss, wcss->halt_map, wcss->halt_wcss); + +/* assert clamps to avoid MX current inrush */ + val =readl (wcss->reg_base +Q6SS_PWR_CTL_REG ); + val |= (Q6SS_CLAMP_IO |Q6SS_CLAMP_WL |Q6SS_CLAMP_QMC_MEM ); +writel (val, wcss->reg_base +Q6SS_PWR_CTL_REG ); + +/* Disable memories by turning off memory foot/headswitch */ +writel ((readl (wcss->reg_base +Q6SS_MEM_PWR_CTL ) & + ~QDSS_Q6_MEMORIES ), + wcss->reg_base +Q6SS_MEM_PWR_CTL ); + +/* Clear the BHS_ON bit */ + val =readl (wcss->reg_base +Q6SS_PWR_CTL_REG ); + val &= ~Q6SS_BHS_ON ; +writel (val, wcss->reg_base +Q6SS_PWR_CTL_REG ); + +clk_disable_unprepare (wcss->ahbfabric_cbcr_clk); +clk_disable_unprepare (wcss->lcc_csr_cbcr); +clk_disable_unprepare (wcss->tcm_slave_cbcr); +clk_disable_unprepare (wcss->qdsp6ss_abhm_cbcr); +clk_disable_unprepare (wcss->qdsp6ss_axim_cbcr); + + val =readl (wcss->reg_base +Q6SS_SLEEP_CBCR ); + val &= ~BIT (0 ); +writel (val, wcss->reg_base +Q6SS_SLEEP_CBCR ); + + val =readl (wcss->reg_base +Q6SS_XO_CBCR ); + val &= ~BIT (0 ); +writel (val, wcss->reg_base +Q6SS_XO_CBCR ); + +clk_disable_unprepare (wcss->ahbs_cbcr); +clk_disable_unprepare (wcss->lcc_bcr_sleep); + + val =readl (wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + val &= ~(Q6SS_CLK_ENABLE |Q6SS_SWITCH_CLK_SRC ); +writel (val, wcss->reg_base +Q6SS_GFMUX_CTL_REG ); + +clk_disable_unprepare (wcss->gcc_abhs_cbcr); + + ret =reset_control_assert (wcss->wcss_reset); +if (ret) { +dev_err (wcss->dev,"wcss_reset failed\n" ); +return ret; + } +usleep_range (200 ,300 ); + + ret =reset_control_deassert (wcss->wcss_reset); +if (ret) { +dev_err (wcss->dev,"wcss_reset failed\n" ); +return ret; + } +usleep_range (200 ,300 ); + +clk_disable_unprepare (wcss->gcc_axim_cbcr); + +return 0 ; +} +static int q6v5_wcss_powerdown (struct q6v5_wcss *wcss) {int ret;
@@ -397,20 +709,28 @@ static int q6v5_wcss_stop(struct rproc *rproc)int ret;/* WCSS powerdown */ - ret =qcom_q6v5_request_stop (&wcss->q6v5); -if (ret == -ETIMEDOUT ) { -dev_err (wcss->dev,"timed out on wait\n" ); -return ret; +if (wcss->requires_force_stop) { + ret =qcom_q6v5_request_stop (&wcss->q6v5); +if (ret == -ETIMEDOUT ) { +dev_err (wcss->dev,"timed out on wait\n" ); +return ret; + } } - ret =q6v5_wcss_powerdown (wcss); -if (ret) -return ret; - -/* Q6 Power down */ - ret =q6v5_q6_powerdown (wcss); -if (ret) -return ret; +if (wcss->version ==WCSS_QCS404 ) { + ret =q6v5_qcs404_wcss_shutdown (wcss); +if (ret) +return ret; + }else { + ret =q6v5_wcss_powerdown (wcss); +if (ret) +return ret; + +/* Q6 Power down */ + ret =q6v5_q6_powerdown (wcss); +if (ret) +return ret; + }qcom_q6v5_unprepare (&wcss->q6v5);
@@ -446,14 +766,26 @@ static const struct rproc_ops q6v5_wcss_ipq8074_ops = { .get_boot_addr = rproc_elf_get_boot_addr, }; -static int q6v5_wcss_init_reset (struct q6v5_wcss *wcss) +static const struct rproc_ops q6v5_wcss_qcs404_ops = { + .start = q6v5_qcs404_wcss_start, + .stop = q6v5_wcss_stop, + .da_to_va = q6v5_wcss_da_to_va, + .load = q6v5_wcss_load, + .get_boot_addr = rproc_elf_get_boot_addr, + .parse_fw = qcom_register_dump_segments, +}; + +static int q6v5_wcss_init_reset (struct q6v5_wcss *wcss, +const struct wcss_data *desc) {struct device *dev = wcss->dev; - wcss->wcss_aon_reset =devm_reset_control_get (dev,"wcss_aon_reset" ); -if (IS_ERR (wcss->wcss_aon_reset)) { -dev_err (wcss->dev,"unable to acquire wcss_aon_reset\n" ); -return PTR_ERR (wcss->wcss_aon_reset); +if (desc->aon_reset_required) { + wcss->wcss_aon_reset =devm_reset_control_get (dev,"wcss_aon_reset" ); +if (IS_ERR (wcss->wcss_aon_reset)) { +dev_err (wcss->dev,"fail to acquire wcss_aon_reset\n" ); +return PTR_ERR (wcss->wcss_aon_reset); + } } wcss->wcss_reset =devm_reset_control_get (dev,"wcss_reset" );
@@ -462,10 +794,18 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)return PTR_ERR (wcss->wcss_reset); } - wcss->wcss_q6_reset =devm_reset_control_get (dev,"wcss_q6_reset" ); -if (IS_ERR (wcss->wcss_q6_reset)) { -dev_err (wcss->dev,"unable to acquire wcss_q6_reset\n" ); -return PTR_ERR (wcss->wcss_q6_reset); +if (desc->wcss_q6_reset_required) { + wcss->wcss_q6_reset =devm_reset_control_get (dev,"wcss_q6_reset" ); +if (IS_ERR (wcss->wcss_q6_reset)) { +dev_err (wcss->dev,"unable to acquire wcss_q6_reset\n" ); +return PTR_ERR (wcss->wcss_q6_reset); + } + } + + wcss->wcss_q6_bcr_reset =devm_reset_control_get_exclusive (dev,"wcss_q6_bcr_reset" ); +if (IS_ERR (wcss->wcss_q6_bcr_reset)) { +dev_err (wcss->dev,"unable to acquire wcss_q6_bcr_reset\n" ); +return PTR_ERR (wcss->wcss_q6_bcr_reset); }return 0 ;
@@ -474,35 +814,48 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss)static int q6v5_wcss_init_mmio (struct q6v5_wcss *wcss,struct platform_device *pdev) { -struct of_phandle_args args; +unsigned int halt_reg[MAX_HALT_REG ] = {0 }; +struct device_node *syscon;struct resource *res;int ret; res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"qdsp6" ); - wcss->reg_base =devm_ioremap_resource (&pdev->dev, res); + wcss->reg_base =devm_ioremap (&pdev->dev, res->start, +resource_size (res));if (IS_ERR (wcss->reg_base))return PTR_ERR (wcss->reg_base); - res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"rmb" ); - wcss->rmb_base =devm_ioremap_resource (&pdev->dev, res); -if (IS_ERR (wcss->rmb_base)) -return PTR_ERR (wcss->rmb_base); +if (wcss->version ==WCSS_IPQ8074 ) { + res =platform_get_resource_byname (pdev,IORESOURCE_MEM ,"rmb" ); + wcss->rmb_base =devm_ioremap_resource (&pdev->dev, res); +if (IS_ERR (wcss->rmb_base)) +return PTR_ERR (wcss->rmb_base); + } - ret =of_parse_phandle_with_fixed_args (pdev->dev.of_node, -"qcom,halt-regs" ,3 ,0 , &args); -if (ret <0 ) { + syscon =of_parse_phandle (pdev->dev.of_node, +"qcom,halt-regs" ,0 ); +if (!syscon) {dev_err (&pdev->dev,"failed to parse qcom,halt-regs\n" );return -EINVAL ; } - wcss->halt_map =syscon_node_to_regmap (args.np); -of_node_put (args.np); + wcss->halt_map =syscon_node_to_regmap (syscon); +of_node_put (syscon);if (IS_ERR (wcss->halt_map))return PTR_ERR (wcss->halt_map); - wcss->halt_q6 = args.args[0 ]; - wcss->halt_wcss = args.args[1 ]; - wcss->halt_nc = args.args[2 ]; + ret =of_property_read_variable_u32_array (pdev->dev.of_node, +"qcom,halt-regs" , + halt_reg,0 , +MAX_HALT_REG ); +if (ret <0 ) { +dev_err (&pdev->dev,"failed to parse qcom,halt-regs\n" ); +return -EINVAL ; + } + + wcss->halt_q6 = halt_reg[0 ]; + wcss->halt_wcss = halt_reg[1 ]; + wcss->halt_nc = halt_reg[2 ];return 0 ; }
@@ -536,6 +889,107 @@ static int q6v5_alloc_memory_region(struct q6v5_wcss *wcss)return 0 ; } +static int q6v5_wcss_init_clock (struct q6v5_wcss *wcss) +{ +int ret; + + wcss->xo =devm_clk_get (wcss->dev,"xo" ); +if (IS_ERR (wcss->xo)) { + ret =PTR_ERR (wcss->xo); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get xo clock" ); +return ret; + } + + wcss->gcc_abhs_cbcr =devm_clk_get (wcss->dev,"gcc_abhs_cbcr" ); +if (IS_ERR (wcss->gcc_abhs_cbcr)) { + ret =PTR_ERR (wcss->gcc_abhs_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get gcc abhs clock" ); +return PTR_ERR (wcss->gcc_abhs_cbcr); + } + + wcss->gcc_axim_cbcr =devm_clk_get (wcss->dev,"gcc_axim_cbcr" ); +if (IS_ERR (wcss->gcc_axim_cbcr)) { + ret =PTR_ERR (wcss->gcc_axim_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get gcc axim clock\n" ); +return PTR_ERR (wcss->gcc_axim_cbcr); + } + + wcss->ahbfabric_cbcr_clk =devm_clk_get (wcss->dev, +"lcc_ahbfabric_cbc" ); +if (IS_ERR (wcss->ahbfabric_cbcr_clk)) { + ret =PTR_ERR (wcss->ahbfabric_cbcr_clk); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get ahbfabric clock\n" ); +return PTR_ERR (wcss->ahbfabric_cbcr_clk); + } + + wcss->lcc_csr_cbcr =devm_clk_get (wcss->dev,"tcsr_lcc_cbc" ); +if (IS_ERR (wcss->lcc_csr_cbcr)) { + ret =PTR_ERR (wcss->lcc_csr_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get csr cbcr clk\n" ); +return PTR_ERR (wcss->lcc_csr_cbcr); + } + + wcss->ahbs_cbcr =devm_clk_get (wcss->dev, +"lcc_abhs_cbc" ); +if (IS_ERR (wcss->ahbs_cbcr)) { + ret =PTR_ERR (wcss->ahbs_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get ahbs_cbcr clk\n" ); +return PTR_ERR (wcss->ahbs_cbcr); + } + + wcss->tcm_slave_cbcr =devm_clk_get (wcss->dev, +"lcc_tcm_slave_cbc" ); +if (IS_ERR (wcss->tcm_slave_cbcr)) { + ret =PTR_ERR (wcss->tcm_slave_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get tcm cbcr clk\n" ); +return PTR_ERR (wcss->tcm_slave_cbcr); + } + + wcss->qdsp6ss_abhm_cbcr =devm_clk_get (wcss->dev,"lcc_abhm_cbc" ); +if (IS_ERR (wcss->qdsp6ss_abhm_cbcr)) { + ret =PTR_ERR (wcss->qdsp6ss_abhm_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get abhm cbcr clk\n" ); +return PTR_ERR (wcss->qdsp6ss_abhm_cbcr); + } + + wcss->qdsp6ss_axim_cbcr =devm_clk_get (wcss->dev,"lcc_axim_cbc" ); +if (IS_ERR (wcss->qdsp6ss_axim_cbcr)) { + ret =PTR_ERR (wcss->qdsp6ss_axim_cbcr); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get axim cbcr clk\n" ); +return PTR_ERR (wcss->qdsp6ss_abhm_cbcr); + } + + wcss->lcc_bcr_sleep =devm_clk_get (wcss->dev,"lcc_bcr_sleep" ); +if (IS_ERR (wcss->lcc_bcr_sleep)) { + ret =PTR_ERR (wcss->lcc_bcr_sleep); +if (ret != -EPROBE_DEFER ) +dev_err (wcss->dev,"failed to get bcr cbcr clk\n" ); +return PTR_ERR (wcss->lcc_bcr_sleep); + } + +return 0 ; +} + +static int q6v5_wcss_init_regulator (struct q6v5_wcss *wcss) +{ + wcss->cx_supply =devm_regulator_get (wcss->dev,"cx" ); +if (IS_ERR (wcss->cx_supply)) +return PTR_ERR (wcss->cx_supply); + +regulator_set_load (wcss->cx_supply,100000 ); + +return 0 ; +} +static int q6v5_wcss_probe (struct platform_device *pdev) {const struct wcss_data *desc;
@@ -547,7 +1001,7 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (!desc)return -EINVAL ; - rproc =rproc_alloc (&pdev->dev, pdev->name, &q6v5_wcss_ipq8074_ops, + rproc =rproc_alloc (&pdev->dev, pdev->name, desc->ops, desc->firmware_name,sizeof (*wcss));if (!rproc) {dev_err (&pdev->dev,"failed to allocate rproc\n" );
@@ -556,7 +1010,10 @@ static int q6v5_wcss_probe(struct platform_device *pdev) wcss = rproc->priv; wcss->dev = &pdev->dev; - wcss->crash_reason_smem = desc->crash_reason_smem; + wcss->version = desc->version; + + wcss->version = desc->version; + wcss->requires_force_stop = desc->requires_force_stop; ret =q6v5_wcss_init_mmio (wcss, pdev);if (ret)
@@ -566,7 +1023,17 @@ static int q6v5_wcss_probe(struct platform_device *pdev)if (ret) goto free_rproc; - ret =q6v5_wcss_init_reset (wcss); +if (wcss->version ==WCSS_QCS404 ) { + ret =q6v5_wcss_init_clock (wcss); +if (ret) + goto free_rproc; + + ret =q6v5_wcss_init_regulator (wcss); +if (ret) + goto free_rproc; + } + + ret =q6v5_wcss_init_reset (wcss, desc);if (ret) goto free_rproc;
@@ -577,6 +1044,9 @@ static int q6v5_wcss_probe(struct platform_device *pdev)qcom_add_glink_subdev (rproc, &wcss->glink_subdev,"q6wcss" );qcom_add_ssr_subdev (rproc, &wcss->ssr_subdev,"q6wcss" ); + wcss->sysmon =qcom_add_sysmon_subdev (rproc, + desc->sysmon_name, + desc->ssctl_id); ret =rproc_add (rproc);if (ret)
@@ -605,10 +1075,28 @@ static int q6v5_wcss_remove(struct platform_device *pdev)static const struct wcss_data wcss_ipq8074_res_init = { .firmware_name ="IPQ8074/q6_fw.mdt" , .crash_reason_smem =WCSS_CRASH_REASON , + .aon_reset_required = true, + .wcss_q6_reset_required = true, + .ops = &q6v5_wcss_ipq8074_ops, + .requires_force_stop = true, +}; + +static const struct wcss_data wcss_qcs404_res_init = { + .crash_reason_smem =WCSS_CRASH_REASON , + .firmware_name ="wcnss.mdt" , + .version =WCSS_QCS404 , + .aon_reset_required = false, + .wcss_q6_reset_required = false, + .ssr_name ="mpss" , + .sysmon_name ="wcnss" , + .ssctl_id =0x12 , + .ops = &q6v5_wcss_qcs404_ops, + .requires_force_stop = false, };static const struct of_device_id q6v5_wcss_of_match[] = { { .compatible ="qcom,ipq8074-wcss-pil" , .data = &wcss_ipq8074_res_init }, + { .compatible ="qcom,qcs404-wcss-pil" , .data = &wcss_qcs404_res_init }, { }, };
Signature · 1 line
2.7.4
PATCH v7 4/4 remoteproc: qcom: wcss: explicitly request exclusive reset control
In reply to Gokul Sriram PalanisamyFrom: Govind Singh <[email protected]>
Use request exclusive reset control for wcss reset controls.
Signed-off-by Govind Singh <[email protected]>
--- drivers/remoteproc/qcom_q6v5_wcss.c | 6 +++--- 1 file changed, 3 insertions(+), 3 deletions(-)
drivers/remoteproc/qcom_q6v5_wcss.c +3 -3
@@ -781,21 +781,21 @@ static int q6v5_wcss_init_reset(struct q6v5_wcss *wcss,struct device *dev = wcss->dev;if (desc->aon_reset_required) { - wcss->wcss_aon_reset =devm_reset_control_get (dev,"wcss_aon_reset" ); + wcss->wcss_aon_reset =devm_reset_control_get_exclusive (dev,"wcss_aon_reset" );if (IS_ERR (wcss->wcss_aon_reset)) {dev_err (wcss->dev,"fail to acquire wcss_aon_reset\n" );return PTR_ERR (wcss->wcss_aon_reset); } } - wcss->wcss_reset =devm_reset_control_get (dev,"wcss_reset" ); + wcss->wcss_reset =devm_reset_control_get_exclusive (dev,"wcss_reset" );if (IS_ERR (wcss->wcss_reset)) {dev_err (wcss->dev,"unable to acquire wcss_reset\n" );return PTR_ERR (wcss->wcss_reset); }if (desc->wcss_q6_reset_required) { - wcss->wcss_q6_reset =devm_reset_control_get (dev,"wcss_q6_reset" ); + wcss->wcss_q6_reset =devm_reset_control_get_exclusive (dev,"wcss_q6_reset" );if (IS_ERR (wcss->wcss_q6_reset)) {dev_err (wcss->dev,"unable to acquire wcss_q6_reset\n" );return PTR_ERR (wcss->wcss_q6_reset);
Signature · 1 line
2.7.4
Stephen Boyd
maintainerQuoting Gokul Sriram Palanisamy (2020-07-03 01:58:38)
Quoted 2 lines
Changes since v6:
Removed duplicate structure entry added during rebase in v5
Please stop sending this as a reply to the previous series. Please see point 15 in Documentation/process/submitting-patches.rst
https://www.kernel.org/doc/html/latest/process/submitting-patches.html#explicit-in-reply-to-headers