DMA_ATTR_WRITE_COMBINE on mips
[I hope the imgtec address still works, but maybe the mips folks know if it moved to mips]
Hi Alex,
you added DMA_ATTR_WRITE_COMBINE support in dma_mmap_attrs to mips in commit 8c172467be36f7c9591e59b647e4cd342ce2ef41
("MIPS: Add implementation of dma_map_ops.mmap()"), but that commit only added the support in mmap, not in dma_alloc_attrs. This means the memory is now used in kernel space through KSEG1, and thus uncached, while for userspace mappings through dma_mmap_* pgprot_writebombine is used, which creates a write combine mapping, which on some MIPS CPUs sets the _CACHE_UNCACHED_ACCELERATED pte bit instead of the _CACHE_UNCACHED one. I know at least on arm, powerpc and x86 such mixed page cachability attributes can cause pretty severe problems. Are they ok on mips? Or was the DMA_ATTR_WRITE_COMBINE supported unintended and not correct and we should remove it?
Hi Christoph,
Quoted 2 lines
[I hope the imgtec address still works, but maybe the mips folks know if it moved to mips]
Alex left Imagination long before the transition to the interim MIPS
company.
Quoted 11 lines
you added
DMA_ATTR_WRITE_COMBINEsupport indma_mmap_attrsto mips in commit8c172467be36f7c9591e59b647e4cd342ce2ef41
("MIPS: Add implementation ofdma_map_ops.mmap()"), but that commit only added the support in mmap, not indma_alloc_attrs. This means the memory is now used in kernel space through KSEG1, and thus uncached, while for userspace mappings through dma_mmap_*pgprot_writebombineis used, which creates a write combine mapping, which on some MIPS CPUs sets the_CACHE_UNCACHED_ACCELERATEDpte bit instead of the_CACHE_UNCACHEDone. I know at least on arm, powerpc and x86 such mixed page cachability attributes can cause pretty severe problems. Are they ok on mips?
The uncached accelerated mode is implementation-specific, so you won't
find its definition in the architecture, however the original R10000 implementation explicitly documents[1] interactions between bus accesses using the two modes (essentially a _CACHE_UNCACHED store acts as a barrier for any outstanding _CACHE_UNCACHED_ACCELERATED stores; for loads the modes are equivalent), so that's clearly supported.
I've glanced over the interAptiv manual[2] too and it seems to define the
caching modes similarly.
Quoted 2 lines
Or was the
DMA_ATTR_WRITE_COMBINEsupported
unintended and not correct and we should remove it?
I don't know, so regrettably I can't comment on this.
References:
[1] "MIPS R10000 Microprocessor", Version 2.0, MIPS Technologies, Inc.,
January 29, 1997
<http://techpubs.sgi.com/library/manuals/2000/007-2490-001/pdf/007-2490-001.pdf>[2] "MIPS32 interAptiv Multiprocessing System Software User's Manual", Imagination Technologies Ltd., Document Number: MD00904, Revision 02.01, June 15, 2016
Maciej