Add Global Clock controller (GCC) driver for SC7180
v2 cover Add Global Clock controller (GCC) driver for SC7180
[v2]
* Update the DFS macro for RCG to reflect the hw init similar to clock name.
* Update the Documentation binding of GCC to YAML schemas.
* Add comments for CRITICAL clocks, remove PLL forward declarations and unwanted comments/prints.
[v1]
* Add driver support for Global Clock controller for SC7180 and also update device tree bindings for the various clocks supported in the clock controller.
Taniya Das (3):
clk: qcom: rcg: update the DFS macro for RCG
dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
clk: qcom: Add Global Clock controller (GCC) driver for SC7180
.../devicetree/bindings/clock/qcom,gcc.yaml | 141 + drivers/clk/qcom/Kconfig | 10 +- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/clk-rcg.h | 2 +- drivers/clk/qcom/gcc-sc7180.c | 2497 +++++++++++++++++ drivers/clk/qcom/gcc-sdm845.c | 96 +- include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 + 7 files changed, 2852 insertions(+), 50 deletions(-) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.yaml create mode 100644 drivers/clk/qcom/gcc-sc7180.c create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
PATCH v2 1/3 clk: qcom: rcg: update the DFS macro for RCG
Update the init data name for each of the dynamic frequency switch controlled clock associated with the RCG clock name, so that it can be generated as per the hardware plan. Thus update the macro accordingly.
Signed-off-by Taniya Das <[email protected]>
--- drivers/clk/qcom/clk-rcg.h | 2 +- drivers/clk/qcom/gcc-sdm845.c | 96 +++++++++++++++++------------------ 2 files changed, 49 insertions(+), 49 deletions(-)
drivers/clk/qcom/clk-rcg.h +1 -1
@@ -168,7 +168,7 @@ struct clk_rcg_dfs_data { };#define DEFINE_RCG_DFS (r) \ - { .rcg = &r##_src, .init = &r##_init } + { .rcg = &r, .init = &r##_init } extern int qcom_cc_register_rcg_dfs(struct regmap *regmap, const struct clk_rcg_dfs_data *rcgs,
drivers/clk/qcom/gcc-sdm845.c +48 -48
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PATCH v2 2/3 dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
In reply to Taniya DasThe GCC clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those. Also update the compatible for SC7180 along with example for clocks & clock-names.
Signed-off-by Taniya Das <[email protected]>
--- .../devicetree/bindings/clock/qcom,gcc.yaml | 141 ++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 ++++++++++++++++++ 2 files changed, 296 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +141 -0
@@ -0,0 +1,141 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding + +maintainers: + - Stephen Boyd <[email protected]> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + reg: + maxItems: 1 + description: | + shall contain the base register location and length + + compatible : + enum: + - qcom,gcc-apq8064 + - qcom,gcc-apq8084 + - qcom,gcc-ipq8064 + - qcom,gcc-ipq4019 + - qcom,gcc-ipq8074 + - qcom,gcc-msm8660 + - qcom,gcc-msm8916 + - qcom,gcc-msm8960 + - qcom,gcc-msm8974 + - qcom,gcc-msm8974pro + - qcom,gcc-msm8974pro-ac + - qcom,gcc-msm8994 + - qcom,gcc-msm8996 + - qcom,gcc-msm8998 + - qcom,gcc-mdm9615 + - qcom,gcc-qcs404 + - qcom,gcc-sdm630 + - qcom,gcc-sdm660 + - qcom,gcc-sdm845 + - qcom,gcc-sc7180 + + clocks: + minItems: 1 + maxItems: 2 + items: + - description: Board XO source + - description: Board active XO source + + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: bi_tcxo + - const: bi_tcxo_ao + + nvmem-cells: + $ref: /schemas/types.yaml#/definitions/phandle-array + description: + Qualcomm TSENS (thermal sensor device) on some devices can + be part of GCC and hence the TSENS properties can also be part + of the GCC/clock-controller node. + For more details on the TSENS properties please refer + Documentation/devicetree/bindings/thermal/qcom-tsens.txt + + nvmem-cell-names: + $ref: /schemas/types.yaml#/definitions/string-array + description: + Names for each nvmem-cells specified. + items: + - const: calib + - const: calib_backup + + "#thermal-sensor-cells": + const: 1 + + "#power-domain-cells": + const: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +examples: + - | + clock-controller@900000 { + compatible = "qcom,gcc-msm8960"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + + - | + // Example of GCC with TSENS properties: + clock-controller@900000 { + compatible = "qcom,gcc-apq8064"; + reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #clock-cells = <1>; + #reset-cells = <1>; + #thermal-sensor-cells = <1>; + }; + + - | + //Example of GCC with protected-clocks properties: + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + protected-clocks = <187>, <188>, <189>, <190>, <191>; + }; + + - | + //Example of GCC with clock nodes properties: + clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0x100000 0x1f0000>; + clocks = <&rpmhcc 0>, <&rpmhcc 1>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +...
include/dt-bindings/clock/qcom,gcc-sc7180.h new file +155 -0
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Re: [PATCH v2 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
Quoted 5 lines · Taniya Das
The GCC clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those. Also update the compatible for SC7180 along with example for clocks & clock-names.
Quoted 7 lines
Signed-off-by Taniya Das <[email protected]>--- .../devicetree/bindings/clock/qcom,gcc.yaml | 141 ++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 ++++++++++++++++++ 2 files changed, 296 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc.yaml create mode 100644 include/dt-bindings/clock/qcom,gcc-sc7180.h
You need to remove the old doc.
Quoted 19 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +12
-0@@ -0,0 +1,141 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding + +maintainers: + - Stephen Boyd <[email protected]> + +properties:
Documentation/devicetree/bindings/clock/qcom,gcc.yaml line 22
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +10
-0+ "#clock-cells": + const: 1 + + "#reset-cells": + const: 1 + + reg: + maxItems: 1 + description: | + shall contain the base register location and length
Don't need a description if there's only 1 entry.
Quoted 30 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +30
-0+ + compatible : + enum: + - qcom,gcc-apq8064 + - qcom,gcc-apq8084 + - qcom,gcc-ipq8064 + - qcom,gcc-ipq4019 + - qcom,gcc-ipq8074 + - qcom,gcc-msm8660 + - qcom,gcc-msm8916 + - qcom,gcc-msm8960 + - qcom,gcc-msm8974 + - qcom,gcc-msm8974pro + - qcom,gcc-msm8974pro-ac + - qcom,gcc-msm8994 + - qcom,gcc-msm8996 + - qcom,gcc-msm8998 + - qcom,gcc-mdm9615 + - qcom,gcc-qcs404 + - qcom,gcc-sdm630 + - qcom,gcc-sdm660 + - qcom,gcc-sdm845 + - qcom,gcc-sc7180 + + clocks: + minItems: 1 + maxItems: 2 + items: + - description: Board XO source + - description: Board active XO source
Documentation/devicetree/bindings/clock/qcom,gcc.yaml line 62
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Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +10
-0+ + clock-names: + minItems: 1 + maxItems: 2 + items: + - const: bi_tcxo + - const: bi_tcxo_ao + + nvmem-cells: + $ref: /schemas/types.yaml#/definitions/phandle-array
Standard property, you don't need the type here. What's needed is the size.
Documentation/devicetree/bindings/clock/qcom,gcc.yaml line 71
Quoted 9 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +9
-0+ description: + Qualcomm TSENS (thermal sensor device) on some devices can + be part of GCC and hence the TSENS properties can also be part + of the GCC/clock-controller node. + For more details on the TSENS properties please refer + Documentation/devicetree/bindings/thermal/qcom-tsens.txt + + nvmem-cell-names: + $ref: /schemas/types.yaml#/definitions/string-array
Don't need the type (and this would have to be under an 'allOf' to actually work).
Quoted 235 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +70
-0+ description: + Names for each nvmem-cells specified. + items: + - const: calib + - const: calib_backup + + "#thermal-sensor-cells": + const: 1 + + "#power-domain-cells": + const: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +examples: + - | + clock-controller@900000 { + compatible = "qcom,gcc-msm8960"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + + - | + // Example of GCC with TSENS properties: + clock-controller@900000 { + compatible = "qcom,gcc-apq8064"; + reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #clock-cells = <1>; + #reset-cells = <1>; + #thermal-sensor-cells = <1>; + }; + + - | + //Example of GCC with protected-clocks properties: + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + protected-clocks = <187>, <188>, <189>, <190>, <191>; + }; + + - | + //Example of GCC with clock nodes properties: + clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0x100000 0x1f0000>; + clocks = <&rpmhcc 0>, <&rpmhcc 1>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +...include/dt-bindings/clock/qcom,gcc-sc7180.h new file +155
-1@@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H + +/* GCC clocks */ +#define GCC_GPLL0_MAIN_DIV_CDIV 0 +#define GPLL0 1 +#define GPLL0_OUT_EVEN 2 +#define GPLL1 3 +#define GPLL4 4 +#define GPLL6 5 +#define GPLL7 6 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 7 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8 +#define GCC_BOOT_ROM_AHB_CLK 9 +#define GCC_CAMERA_AHB_CLK 10 +#define GCC_CAMERA_HF_AXI_CLK 11 +#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12 +#define GCC_CAMERA_XO_CLK 13 +#define GCC_CE1_AHB_CLK 14 +#define GCC_CE1_AXI_CLK 15 +#define GCC_CE1_CLK 16 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 +#define GCC_CPUSS_AHB_CLK 18 +#define GCC_CPUSS_AHB_CLK_SRC 19 +#define GCC_CPUSS_GNOC_CLK 20 +#define GCC_CPUSS_RBCPR_CLK 21 +#define GCC_DDRSS_GPU_AXI_CLK 22 +#define GCC_DISP_AHB_CLK 23 +#define GCC_DISP_GPLL0_CLK_SRC 24 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 25 +#define GCC_DISP_HF_AXI_CLK 26 +#define GCC_DISP_THROTTLE_HF_AXI_CLK 27 +#define GCC_DISP_XO_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP1_CLK_SRC 30 +#define GCC_GP2_CLK 31 +#define GCC_GP2_CLK_SRC 32 +#define GCC_GP3_CLK 33 +#define GCC_GP3_CLK_SRC 34 +#define GCC_GPU_CFG_AHB_CLK 35 +#define GCC_GPU_GPLL0_CLK_SRC 36 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 37 +#define GCC_GPU_MEMNOC_GFX_CLK 38 +#define GCC_GPU_SNOC_DVM_GFX_CLK 39 +#define GCC_NPU_AXI_CLK 40 +#define GCC_NPU_BWMON_AXI_CLK 41 +#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42 +#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43 +#define GCC_NPU_CFG_AHB_CLK 44 +#define GCC_NPU_DMA_CLK 45 +#define GCC_NPU_GPLL0_CLK_SRC 46 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 47 +#define GCC_PDM2_CLK 48 +#define GCC_PDM2_CLK_SRC 49 +#define GCC_PDM_AHB_CLK 50 +#define GCC_PDM_XO4_CLK 51 +#define GCC_PRNG_AHB_CLK 52 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53 +#define GCC_QSPI_CORE_CLK 54 +#define GCC_QSPI_CORE_CLK_SRC 55 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56 +#define GCC_QUPV3_WRAP0_CORE_CLK 57 +#define GCC_QUPV3_WRAP0_S0_CLK 58 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59 +#define GCC_QUPV3_WRAP0_S1_CLK 60 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61 +#define GCC_QUPV3_WRAP0_S2_CLK 62 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63 +#define GCC_QUPV3_WRAP0_S3_CLK 64 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65 +#define GCC_QUPV3_WRAP0_S4_CLK 66 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67 +#define GCC_QUPV3_WRAP0_S5_CLK 68 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70 +#define GCC_QUPV3_WRAP1_CORE_CLK 71 +#define GCC_QUPV3_WRAP1_S0_CLK 72 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73 +#define GCC_QUPV3_WRAP1_S1_CLK 74 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75 +#define GCC_QUPV3_WRAP1_S2_CLK 76 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77 +#define GCC_QUPV3_WRAP1_S3_CLK 78 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79 +#define GCC_QUPV3_WRAP1_S4_CLK 80 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81 +#define GCC_QUPV3_WRAP1_S5_CLK 82 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87 +#define GCC_SDCC1_AHB_CLK 88 +#define GCC_SDCC1_APPS_CLK 89 +#define GCC_SDCC1_APPS_CLK_SRC 90 +#define GCC_SDCC1_ICE_CORE_CLK 91 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 92 +#define GCC_SDCC2_AHB_CLK 93 +#define GCC_SDCC2_APPS_CLK 94 +#define GCC_SDCC2_APPS_CLK_SRC 95 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 +#define GCC_UFS_MEM_CLKREF_CLK 97 +#define GCC_UFS_PHY_AHB_CLK 98 +#define GCC_UFS_PHY_AXI_CLK 99 +#define GCC_UFS_PHY_AXI_CLK_SRC 100 +#define GCC_UFS_PHY_ICE_CORE_CLK 101 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 +#define GCC_UFS_PHY_PHY_AUX_CLK 103 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108 +#define GCC_USB30_PRIM_MASTER_CLK 109 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 +#define GCC_USB30_PRIM_SLEEP_CLK 113 +#define GCC_USB3_PRIM_CLKREF_CLK 114 +#define GCC_USB3_PRIM_PHY_AUX_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119 +#define GCC_VIDEO_AHB_CLK 120 +#define GCC_VIDEO_AXI_CLK 121 +#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122 +#define GCC_VIDEO_THROTTLE_AXI_CLK 123 +#define GCC_VIDEO_XO_CLK 124 + +/* GCC resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_PHY_BCR 2 +#define GCC_USB30_PRIM_BCR 3 +#define GCC_USB3_DP_PHY_PRIM_BCR 4 +#define GCC_USB3_DP_PHY_SEC_BCR 5 +#define GCC_USB3_PHY_PRIM_BCR 6 +#define GCC_USB3_PHY_SEC_BCR 7 +#define GCC_USB3PHY_PHY_PRIM_BCR 8 +#define GCC_USB3PHY_PHY_SEC_BCR 9 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10 + +/* GCC GDSCRs */ +#define UFS_PHY_GDSC 0 +#define USB30_PRIM_GDSC 1 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3 + +#endif --Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Re: [PATCH v2 2/3] dt-bindings: clk: qcom: Add YAML schemas for the GCC clock bindings
Hello Rob,
Thank you for your review comments.
Quoted 14 lines · Rob Herring
Quoted 5 lines · Taniya Das
The GCC clock provider have a bunch of generic properties that are needed in a device tree. Add a YAML schemas for those. Also update the compatible for SC7180 along with example for clocks & clock-names.
Quoted 7 lines
Signed-off-by Taniya Das <[email protected]>--- .../devicetree/bindings/clock/qcom,gcc.yaml | 141 ++++++++++++++++ include/dt-bindings/clock/qcom,gcc-sc7180.h | 155 ++++++++++++++++++ 2 files changed, 296 insertions(+)create mode 100644
Documentation/devicetree/bindings/clock/qcom,gcc.yamlcreate mode 100644include/dt-bindings/clock/qcom,gcc-sc7180.h
Quoted 2 lines
You need to remove the old doc.
Would remove it in the next patch.
Quoted 23 lines
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Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +16
-0@@ -0,0 +1,141 @@ +# SPDX-License-Identifier: GPL-2.0 +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/qcom,gcc.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Global Clock & Reset Controller Binding + +maintainers: + - Stephen Boyd <[email protected]> + +properties: + "#clock-cells": + const: 1 + + "#reset-cells":
Quoted 9 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml line 22
Quoted 6 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +6
-0+ const: 1 + + reg: + maxItems: 1 + description: | + shall contain the base register location and lengthDon't need a description if there's only 1 entry.
Thanks, would remove.
Quoted 34 lines
Quoted 34 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +34
-0+ + compatible : + enum: + - qcom,gcc-apq8064 + - qcom,gcc-apq8084 + - qcom,gcc-ipq8064 + - qcom,gcc-ipq4019 + - qcom,gcc-ipq8074 + - qcom,gcc-msm8660 + - qcom,gcc-msm8916 + - qcom,gcc-msm8960 + - qcom,gcc-msm8974 + - qcom,gcc-msm8974pro + - qcom,gcc-msm8974pro-ac + - qcom,gcc-msm8994 + - qcom,gcc-msm8996 + - qcom,gcc-msm8998 + - qcom,gcc-mdm9615 + - qcom,gcc-qcs404 + - qcom,gcc-sdm630 + - qcom,gcc-sdm660 + - qcom,gcc-sdm845 + - qcom,gcc-sc7180 + + clocks: + minItems: 1 + maxItems: 2 + items: + - description: Board XO source + - description: Board active XO source + + clock-names: + minItems: 1 + maxItems: 2
Quoted 9 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml line 62
Quoted 6 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +6
-0+ items: + - const: bi_tcxo + - const: bi_tcxo_ao + + nvmem-cells: + $ref: /schemas/types.yaml#/definitions/phandle-arrayStandard property, you don't need the type here. What's needed is the size.
Would take care of it in the next patch.
Quoted 10 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml line 71
Quoted 9 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +9
-0+ description: + Qualcomm TSENS (thermal sensor device) on some devices can + be part of GCC and hence the TSENS properties can also be part + of the GCC/clock-controller node. + For more details on the TSENS properties please refer + Documentation/devicetree/bindings/thermal/qcom-tsens.txt + + nvmem-cell-names: + $ref: /schemas/types.yaml#/definitions/string-array
Quoted 3 lines
Don't need the type (and this would have to be under an 'allOf' to actually work).
Would take care of it in the next patch.
Quoted 235 lines
Quoted 235 lines
Documentation/devicetree/bindings/clock/qcom,gcc.yaml new file +70
-0+ description: + Names for each nvmem-cells specified. + items: + - const: calib + - const: calib_backup + + "#thermal-sensor-cells": + const: 1 + + "#power-domain-cells": + const: 1 + + protected-clocks: + description: + Protected clock specifier list as per common clock binding + +required: + - "#clock-cells" + - "#reset-cells" + - compatible + - reg + - clocks + - clock-names + +examples: + - | + clock-controller@900000 { + compatible = "qcom,gcc-msm8960"; + reg = <0x900000 0x4000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; + + + - | + // Example of GCC with TSENS properties: + clock-controller@900000 { + compatible = "qcom,gcc-apq8064"; + reg = <0x00900000 0x4000>; + nvmem-cells = <&tsens_calib>, <&tsens_backup>; + nvmem-cell-names = "calib", "calib_backup"; + #clock-cells = <1>; + #reset-cells = <1>; + #thermal-sensor-cells = <1>; + }; + + - | + //Example of GCC with protected-clocks properties: + clock-controller@100000 { + compatible = "qcom,gcc-sdm845"; + reg = <0x100000 0x1f0000>; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + protected-clocks = <187>, <188>, <189>, <190>, <191>; + }; + + - | + //Example of GCC with clock nodes properties: + clock-controller@100000 { + compatible = "qcom,gcc-sc7180"; + reg = <0x100000 0x1f0000>; + clocks = <&rpmhcc 0>, <&rpmhcc 1>; + clock-names = "bi_tcxo", "bi_tcxo_ao"; + #clock-cells = <1>; + #reset-cells = <1>; + #power-domain-cells = <1>; + }; +...include/dt-bindings/clock/qcom,gcc-sc7180.h new file +155
-1@@ -0,0 +1,155 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (c) 2019, The Linux Foundation. All rights reserved. +*/ + +#ifndef _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H +#define _DT_BINDINGS_CLK_QCOM_GCC_SC7180_H + +/* GCC clocks */ +#define GCC_GPLL0_MAIN_DIV_CDIV 0 +#define GPLL0 1 +#define GPLL0_OUT_EVEN 2 +#define GPLL1 3 +#define GPLL4 4 +#define GPLL6 5 +#define GPLL7 6 +#define GCC_AGGRE_UFS_PHY_AXI_CLK 7 +#define GCC_AGGRE_USB3_PRIM_AXI_CLK 8 +#define GCC_BOOT_ROM_AHB_CLK 9 +#define GCC_CAMERA_AHB_CLK 10 +#define GCC_CAMERA_HF_AXI_CLK 11 +#define GCC_CAMERA_THROTTLE_HF_AXI_CLK 12 +#define GCC_CAMERA_XO_CLK 13 +#define GCC_CE1_AHB_CLK 14 +#define GCC_CE1_AXI_CLK 15 +#define GCC_CE1_CLK 16 +#define GCC_CFG_NOC_USB3_PRIM_AXI_CLK 17 +#define GCC_CPUSS_AHB_CLK 18 +#define GCC_CPUSS_AHB_CLK_SRC 19 +#define GCC_CPUSS_GNOC_CLK 20 +#define GCC_CPUSS_RBCPR_CLK 21 +#define GCC_DDRSS_GPU_AXI_CLK 22 +#define GCC_DISP_AHB_CLK 23 +#define GCC_DISP_GPLL0_CLK_SRC 24 +#define GCC_DISP_GPLL0_DIV_CLK_SRC 25 +#define GCC_DISP_HF_AXI_CLK 26 +#define GCC_DISP_THROTTLE_HF_AXI_CLK 27 +#define GCC_DISP_XO_CLK 28 +#define GCC_GP1_CLK 29 +#define GCC_GP1_CLK_SRC 30 +#define GCC_GP2_CLK 31 +#define GCC_GP2_CLK_SRC 32 +#define GCC_GP3_CLK 33 +#define GCC_GP3_CLK_SRC 34 +#define GCC_GPU_CFG_AHB_CLK 35 +#define GCC_GPU_GPLL0_CLK_SRC 36 +#define GCC_GPU_GPLL0_DIV_CLK_SRC 37 +#define GCC_GPU_MEMNOC_GFX_CLK 38 +#define GCC_GPU_SNOC_DVM_GFX_CLK 39 +#define GCC_NPU_AXI_CLK 40 +#define GCC_NPU_BWMON_AXI_CLK 41 +#define GCC_NPU_BWMON_DMA_CFG_AHB_CLK 42 +#define GCC_NPU_BWMON_DSP_CFG_AHB_CLK 43 +#define GCC_NPU_CFG_AHB_CLK 44 +#define GCC_NPU_DMA_CLK 45 +#define GCC_NPU_GPLL0_CLK_SRC 46 +#define GCC_NPU_GPLL0_DIV_CLK_SRC 47 +#define GCC_PDM2_CLK 48 +#define GCC_PDM2_CLK_SRC 49 +#define GCC_PDM_AHB_CLK 50 +#define GCC_PDM_XO4_CLK 51 +#define GCC_PRNG_AHB_CLK 52 +#define GCC_QSPI_CNOC_PERIPH_AHB_CLK 53 +#define GCC_QSPI_CORE_CLK 54 +#define GCC_QSPI_CORE_CLK_SRC 55 +#define GCC_QUPV3_WRAP0_CORE_2X_CLK 56 +#define GCC_QUPV3_WRAP0_CORE_CLK 57 +#define GCC_QUPV3_WRAP0_S0_CLK 58 +#define GCC_QUPV3_WRAP0_S0_CLK_SRC 59 +#define GCC_QUPV3_WRAP0_S1_CLK 60 +#define GCC_QUPV3_WRAP0_S1_CLK_SRC 61 +#define GCC_QUPV3_WRAP0_S2_CLK 62 +#define GCC_QUPV3_WRAP0_S2_CLK_SRC 63 +#define GCC_QUPV3_WRAP0_S3_CLK 64 +#define GCC_QUPV3_WRAP0_S3_CLK_SRC 65 +#define GCC_QUPV3_WRAP0_S4_CLK 66 +#define GCC_QUPV3_WRAP0_S4_CLK_SRC 67 +#define GCC_QUPV3_WRAP0_S5_CLK 68 +#define GCC_QUPV3_WRAP0_S5_CLK_SRC 69 +#define GCC_QUPV3_WRAP1_CORE_2X_CLK 70 +#define GCC_QUPV3_WRAP1_CORE_CLK 71 +#define GCC_QUPV3_WRAP1_S0_CLK 72 +#define GCC_QUPV3_WRAP1_S0_CLK_SRC 73 +#define GCC_QUPV3_WRAP1_S1_CLK 74 +#define GCC_QUPV3_WRAP1_S1_CLK_SRC 75 +#define GCC_QUPV3_WRAP1_S2_CLK 76 +#define GCC_QUPV3_WRAP1_S2_CLK_SRC 77 +#define GCC_QUPV3_WRAP1_S3_CLK 78 +#define GCC_QUPV3_WRAP1_S3_CLK_SRC 79 +#define GCC_QUPV3_WRAP1_S4_CLK 80 +#define GCC_QUPV3_WRAP1_S4_CLK_SRC 81 +#define GCC_QUPV3_WRAP1_S5_CLK 82 +#define GCC_QUPV3_WRAP1_S5_CLK_SRC 83 +#define GCC_QUPV3_WRAP_0_M_AHB_CLK 84 +#define GCC_QUPV3_WRAP_0_S_AHB_CLK 85 +#define GCC_QUPV3_WRAP_1_M_AHB_CLK 86 +#define GCC_QUPV3_WRAP_1_S_AHB_CLK 87 +#define GCC_SDCC1_AHB_CLK 88 +#define GCC_SDCC1_APPS_CLK 89 +#define GCC_SDCC1_APPS_CLK_SRC 90 +#define GCC_SDCC1_ICE_CORE_CLK 91 +#define GCC_SDCC1_ICE_CORE_CLK_SRC 92 +#define GCC_SDCC2_AHB_CLK 93 +#define GCC_SDCC2_APPS_CLK 94 +#define GCC_SDCC2_APPS_CLK_SRC 95 +#define GCC_SYS_NOC_CPUSS_AHB_CLK 96 +#define GCC_UFS_MEM_CLKREF_CLK 97 +#define GCC_UFS_PHY_AHB_CLK 98 +#define GCC_UFS_PHY_AXI_CLK 99 +#define GCC_UFS_PHY_AXI_CLK_SRC 100 +#define GCC_UFS_PHY_ICE_CORE_CLK 101 +#define GCC_UFS_PHY_ICE_CORE_CLK_SRC 102 +#define GCC_UFS_PHY_PHY_AUX_CLK 103 +#define GCC_UFS_PHY_PHY_AUX_CLK_SRC 104 +#define GCC_UFS_PHY_RX_SYMBOL_0_CLK 105 +#define GCC_UFS_PHY_TX_SYMBOL_0_CLK 106 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK 107 +#define GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC 108 +#define GCC_USB30_PRIM_MASTER_CLK 109 +#define GCC_USB30_PRIM_MASTER_CLK_SRC 110 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK 111 +#define GCC_USB30_PRIM_MOCK_UTMI_CLK_SRC 112 +#define GCC_USB30_PRIM_SLEEP_CLK 113 +#define GCC_USB3_PRIM_CLKREF_CLK 114 +#define GCC_USB3_PRIM_PHY_AUX_CLK 115 +#define GCC_USB3_PRIM_PHY_AUX_CLK_SRC 116 +#define GCC_USB3_PRIM_PHY_COM_AUX_CLK 117 +#define GCC_USB3_PRIM_PHY_PIPE_CLK 118 +#define GCC_USB_PHY_CFG_AHB2PHY_CLK 119 +#define GCC_VIDEO_AHB_CLK 120 +#define GCC_VIDEO_AXI_CLK 121 +#define GCC_VIDEO_GPLL0_DIV_CLK_SRC 122 +#define GCC_VIDEO_THROTTLE_AXI_CLK 123 +#define GCC_VIDEO_XO_CLK 124 + +/* GCC resets */ +#define GCC_QUSB2PHY_PRIM_BCR 0 +#define GCC_QUSB2PHY_SEC_BCR 1 +#define GCC_UFS_PHY_BCR 2 +#define GCC_USB30_PRIM_BCR 3 +#define GCC_USB3_DP_PHY_PRIM_BCR 4 +#define GCC_USB3_DP_PHY_SEC_BCR 5 +#define GCC_USB3_PHY_PRIM_BCR 6 +#define GCC_USB3_PHY_SEC_BCR 7 +#define GCC_USB3PHY_PHY_PRIM_BCR 8 +#define GCC_USB3PHY_PHY_SEC_BCR 9 +#define GCC_USB_PHY_CFG_AHB2PHY_BCR 10 + +/* GCC GDSCRs */ +#define UFS_PHY_GDSC 0 +#define USB30_PRIM_GDSC 1 +#define HLOS1_VOTE_MMNOC_MMU_TBU_HF0_GDSC 2 +#define HLOS1_VOTE_MMNOC_MMU_TBU_SF_GDSC 3 + +#endif --Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --
PATCH v2 3/3 clk: qcom: Add Global Clock controller (GCC) driver for SC7180
In reply to Taniya DasAdd support for the global clock controller found on SC7180 based devices. This should allow most non-multimedia device drivers to probe and control their clocks.
Signed-off-by Taniya Das <[email protected]>
--- drivers/clk/qcom/Kconfig | 10 +- drivers/clk/qcom/Makefile | 1 + drivers/clk/qcom/gcc-sc7180.c | 2497 +++++++++++++++++++++++++++++++++ 3 files changed, 2507 insertions(+), 1 deletion(-) create mode 100644 drivers/clk/qcom/gcc-sc7180.c
drivers/clk/qcom/Kconfig +9 -1
@@ -229,6 +229,15 @@ config QCS_GCC_404 Say Y if you want to use multimedia devices or peripheral devices such as UART, SPI, I2C, USB, SD/eMMC, PCIe etc. +config SC_GCC_7180 + tristate "SC7180 Global Clock Controller" + select QCOM_GDSC + depends on COMMON_CLK_QCOM + help + Support for the global clock controller on SC7180 devices. + Say Y if you want to use peripheral devices such as UART, SPI, + I2C, USB, UFS, SDCC, etc. + config SDM_CAMCC_845 tristate "SDM845 Camera Clock Controller" select SDM_GCC_845
@@ -322,5 +331,4 @@ config KRAITCC help Support for the Krait CPU clocks on Qualcomm devices. Say Y if you want to support CPU frequency scaling. - endif
drivers/clk/qcom/Makefile +1 -0
@@ -43,6 +43,7 @@ obj-$(CONFIG_QCOM_CLK_RPMH) += clk-rpmh.o obj-$(CONFIG_QCOM_CLK_SMD_RPM) += clk-smd-rpm.o obj-$(CONFIG_QCS_GCC_404) += gcc-qcs404.o obj-$(CONFIG_QCS_TURING_404) += turingcc-qcs404.o +obj-$(CONFIG_SC_GCC_7180) += gcc-sc7180.o obj-$(CONFIG_SDM_CAMCC_845) += camcc-sdm845.o obj-$(CONFIG_SDM_DISPCC_845) += dispcc-sdm845.o obj-$(CONFIG_SDM_GCC_660) += gcc-sdm660.o
drivers/clk/qcom/gcc-sc7180.c new file +2497 -0
2,497 lines not on this page · raw message
--
Qualcomm INDIA, on behalf of Qualcomm Innovation Center, Inc.is a member of the Code Aurora Forum, hosted by the Linux Foundation.
Stephen Boyd
maintainerRe: [PATCH v2 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
Quoting Taniya Das (2019-08-19 09:37:48)
drivers/clk/qcom/Kconfig config KRAITCC · line 334
Quoted 10 lines
drivers/clk/qcom/Kconfig +0
-1@@ -322,5 +331,4 @@ config KRAITCC help Support for the Krait CPU clocks on Qualcomm devices. Say Y if you want to support CPU frequency scaling. - endif
Please remove this hunk
Quoted 5 lines
drivers/clk/qcom/gcc-sc7180.c new file +0
-0
[...]
drivers/clk/qcom/gcc-sc7180.c line 875
Quoted 4 lines
drivers/clk/qcom/gcc-sc7180.c new file +4
-0+ }, +}; + +/* Camera Subsystem requires always ON. */
Yes, but why? This comment is useful unless it explains why.
Quoted 22 lines
drivers/clk/qcom/gcc-sc7180.c new file +22
-0+static struct clk_branch gcc_camera_ahb_clk = { + .halt_reg =0xb008 , + .halt_check =BRANCH_HALT , + .hwcg_reg =0xb008 , + .hwcg_bit =1 , + .clkr = { + .enable_reg =0xb008 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_camera_ahb_clk" , + .flags =CLK_IS_CRITICAL , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_hf_axi_clk = { + .halt_reg =0xb020 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0xb020 , + .enable_mask =BIT (0 ),
Re: [PATCH v2 3/3] clk: qcom: Add Global Clock controller (GCC) driver for SC7180
Hi Stephen,
Thanks for your review.
Quoted 14 lines · Stephen Boyd
Quoting Taniya Das (2019-08-19 09:37:48)
drivers/clk/qcom/Kconfig config KRAITCC · line 334
Quoted 10 lines
drivers/clk/qcom/Kconfig +0
-1@@ -322,5 +331,4 @@ config KRAITCC help Support for the Krait CPU clocks on Qualcomm devices. Say Y if you want to support CPU frequency scaling. - endifPlease remove this hunk
Would remove this.
Quoted 6 lines
Quoted 5 lines
drivers/clk/qcom/gcc-sc7180.c new file +0
-0[...]
Quoted 7 lines
drivers/clk/qcom/gcc-sc7180.c line 875
Quoted 4 lines
drivers/clk/qcom/gcc-sc7180.c new file +4
-0+ }, +}; + +/* Camera Subsystem requires always ON. */ Yes, but why? This comment is useful unless it explains why.
Next patch would take care.
Quoted 22 lines
Quoted 22 lines
drivers/clk/qcom/gcc-sc7180.c new file +22
-0+static struct clk_branch gcc_camera_ahb_clk = { + .halt_reg =0xb008 , + .halt_check =BRANCH_HALT , + .hwcg_reg =0xb008 , + .hwcg_bit =1 , + .clkr = { + .enable_reg =0xb008 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_camera_ahb_clk" , + .flags =CLK_IS_CRITICAL , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_camera_hf_axi_clk = { + .halt_reg =0xb020 , + .halt_check =BRANCH_HALT , + .clkr = { + .enable_reg =0xb020 , + .enable_mask =BIT (0 ),
Signature · 4 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation. --