Add OSM L3 Interconnect Provider
Subsystems (3)
v2 cover Add OSM L3 Interconnect Provider
This patch series aims to add Operating State Manager (OSM) L3 interconnect provider support on SDM845 SoCs to handle bandwidth requests from CPU to scale L3 caches.
v2:
* addressed review comments from Evan
* dropped unused gpu icc node on SDM845 SoC
Sibi Sankar (2):
dt-bindings: interconnect: Add OSM L3 DT bindings
interconnect: qcom: Add OSM L3 interconnect provider support
.../bindings/interconnect/qcom,osm-l3.yaml | 56 ++++ drivers/interconnect/qcom/Kconfig | 7 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/osm-l3.c | 284 ++++++++++++++++++ .../dt-bindings/interconnect/qcom,osm-l3.h | 12 + 5 files changed, 361 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml create mode 100644 drivers/interconnect/qcom/osm-l3.c create mode 100644 include/dt-bindings/interconnect/qcom,osm-l3.h
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
PATCH v2 1/2 dt-bindings: interconnect: Add OSM L3 DT bindings
Add bindings for Operating State Manager (OSM) L3 interconnect provider on SDM845 SoCs.
Signed-off-by Sibi Sankar <[email protected]>
--- .../bindings/interconnect/qcom,osm-l3.yaml | 56 +++++++++++++++++++ .../dt-bindings/interconnect/qcom,osm-l3.h | 12 ++++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml create mode 100644 include/dt-bindings/interconnect/qcom,osm-l3.h
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +56 -0
@@ -0,0 +1,56 @@ +# SPDX-License-Identifier: BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider + +maintainers: + - Sibi Sankar <[email protected]> + +description: + L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. + The OSM L3 interconnect provider aggregates the L3 bandwidth requests + from CPU/GPU and relays it to the OSM. + +properties: + compatible: + const: "qcom,sdm845-osm-l3" + + reg: + maxItems: 1 + + clocks: + items: + - description: xo clock + - description: alternate clock + + clock-names: + items: + - const: xo + - const: alternate + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm845-osm-l3"; + reg = <0x17d41000 0x1400>; + + clocks = <&rpmhcc 0>, <&gcc 165>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + };
include/dt-bindings/interconnect/qcom,osm-l3.h new file +12 -0
@@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (C) 2019 The Linux Foundation. All rights reserved. +*/ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H + +#define MASTER_OSM_L3_APPS 0 +#define SLAVE_OSM_L3 1 + +#endif
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v2 1/2] dt-bindings: interconnect: Add OSM L3 DT bindings
Quoted 18 lines · Sibi Sankar
Add bindings for Operating State Manager (OSM) L3 interconnect provider on SDM845 SoCs.
Signed-off-by Sibi Sankar <[email protected]>--- .../bindings/interconnect/qcom,osm-l3.yaml | 56 +++++++++++++++++++ .../dt-bindings/interconnect/qcom,osm-l3.h | 12 ++++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml create mode 100644 include/dt-bindings/interconnect/qcom,osm-l3.hDocumentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +0
-0
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml line 1
Quoted 1 line
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +1
-0@@ -0,0 +1,56 @@ +# SPDX-License-Identifier: BSD-2-Clause
(GPL-2.0-only OR BSD-2-Clause) for new bindings please.
Quoted 77 lines
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +55
-0+%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider + +maintainers: + - Sibi Sankar <[email protected]> + +description: + L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. + The OSM L3 interconnect provider aggregates the L3 bandwidth requests + from CPU/GPU and relays it to the OSM. + +properties: + compatible: + const: "qcom,sdm845-osm-l3" + + reg: + maxItems: 1 + + clocks: + items: + - description: xo clock + - description: alternate clock + + clock-names: + items: + - const: xo + - const: alternate + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm845-osm-l3"; + reg = <0x17d41000 0x1400>; + + clocks = <&rpmhcc 0>, <&gcc 165>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + };include/dt-bindings/interconnect/qcom,osm-l3.h new file +12
-1@@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (C) 2019 The Linux Foundation. All rights reserved. +*/ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H + +#define MASTER_OSM_L3_APPS 0 +#define SLAVE_OSM_L3 1 + +#endif --The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project
Re: [PATCH v2 1/2] dt-bindings: interconnect: Add OSM L3 DT bindings
In reply to Sibi SankarHi Sibi,
Quoted 63 lines · Sibi Sankar
Add bindings for Operating State Manager (OSM) L3 interconnect provider on SDM845 SoCs.
Signed-off-by Sibi Sankar <[email protected]>--- .../bindings/interconnect/qcom,osm-l3.yaml | 56 +++++++++++++++++++ .../dt-bindings/interconnect/qcom,osm-l3.h | 12 ++++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml create mode 100644 include/dt-bindings/interconnect/qcom,osm-l3.hDocumentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +46
-0@@ -0,0 +1,56 @@ +# SPDX-License-Identifier: BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider + +maintainers: + - Sibi Sankar <[email protected]> + +description: + L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM. + The OSM L3 interconnect provider aggregates the L3 bandwidth requests + from CPU/GPU and relays it to the OSM. + +properties: + compatible: + const: "qcom,sdm845-osm-l3" + + reg: + maxItems: 1 + + clocks: + items: + - description: xo clock + - description: alternate clock + + clock-names: + items: + - const: xo + - const: alternate + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#interconnect-cells' + +additionalProperties: false + +examples:
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml line 56
Quoted 10 lines
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +10
-0+ - | + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm845-osm-l3"; + reg = <0x17d41000 0x1400>; + + clocks = <&rpmhcc 0>, <&gcc 165>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + };
Are we going to do the bandwidth scaling from some cpufreq driver? Under which DT node will we put the "interconnects" property?
Thanks,
Georgi
Quoted 19 lines
include/dt-bindings/interconnect/qcom,osm-l3.h new file +12
-0@@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (C) 2019 The Linux Foundation. All rights reserved. +*/ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H + +#define MASTER_OSM_L3_APPS 0 +#define SLAVE_OSM_L3 1 + +#endif
Re: [PATCH v2 1/2] dt-bindings: interconnect: Add OSM L3 DT bindings
Hey Georgi,
Quoted 76 lines · Georgi Djakov
Hi Sibi,
Quoted 73 lines · Sibi Sankar
Add bindings for Operating State Manager (OSM) L3 interconnect provider on SDM845 SoCs.
Signed-off-by Sibi Sankar <[email protected]>--- .../bindings/interconnect/qcom,osm-l3.yaml | 56 +++++++++++++++++++ .../dt-bindings/interconnect/qcom,osm-l3.h | 12 ++++ 2 files changed, 68 insertions(+) create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml create mode 100644 include/dt-bindings/interconnect/qcom,osm-l3.hDocumentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +7
-0@@ -0,0 +1,56 @@ +# SPDX-License-Identifier: BSD-2-Clause +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm Operating State Manager (OSM) L3 InterconnectProvider
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +6
-0+ +maintainers: + - Sibi Sankar <[email protected]> + +description: + L3 cache bandwidth requirements on Qualcomm SoCs is serviced by theOSM.
+ The OSM L3 interconnect provider aggregates the L3 bandwidth requestsDocumentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +37
-0+ from CPU/GPU and relays it to the OSM. + +properties: + compatible: + const: "qcom,sdm845-osm-l3" + + reg: + maxItems: 1 + + clocks: + items: + - description: xo clock + - description: alternate clock + + clock-names: + items: + - const: xo + - const: alternate + + '#interconnect-cells': + const: 1 + +required: + - compatible + - reg + - clocks + - clock-names + - '#interconnect-cells' + +additionalProperties: false + +examples: + - | + osm_l3: interconnect@17d41000 { + compatible = "qcom,sdm845-osm-l3"; + reg = <0x17d41000 0x1400>; +
Quoted 8 lines
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml line 56
Quoted 5 lines
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +5
-0+ clocks = <&rpmhcc 0>, <&gcc 165>; + clock-names = "xo", "alternate"; + + #interconnect-cells = <1>; + };Are we going to do the bandwidth scaling from some cpufreq driver? Under which DT node will we put the "interconnects" property?
Its still undecided :( unfortunately.
Using Saravana's series means that
bandwidth scaling will be done from
the cpufreq driver. The property
will be a part of the cpu-nodes. But
the part of adding the bw opp-tables
also to cpufreq driver or nodes doesn't
seem correct to me.
Quoted 23 lines
Thanks,
GeorgiQuoted 19 lines
include/dt-bindings/interconnect/qcom,osm-l3.h new file +12
-0@@ -0,0 +1,12 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +/* +* Copyright (C) 2019 The Linux Foundation. All rights reserved. +*/ + +#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H +#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H + +#define MASTER_OSM_L3_APPS 0 +#define SLAVE_OSM_L3 1 + +#endif
Signature · 3 lines
-- Sibi Sankar -- Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, a Linux Foundation Collaborative Project.
PATCH v2 2/2 interconnect: qcom: Add OSM L3 interconnect provider support
In reply to Sibi SankarOn some Qualcomm SoCs, Operating State Manager (OSM) controls the resources of scaling L3 caches. Add a driver to handle bandwidth requests to OSM L3 from CPU/GPU.
Signed-off-by Sibi Sankar <[email protected]>
--- drivers/interconnect/qcom/Kconfig | 7 + drivers/interconnect/qcom/Makefile | 2 + drivers/interconnect/qcom/osm-l3.c | 284 +++++++++++++++++++++++++++++ 3 files changed, 293 insertions(+) create mode 100644 drivers/interconnect/qcom/osm-l3.c
drivers/interconnect/qcom/Kconfig +7 -0
@@ -5,6 +5,13 @@ config INTERCONNECT_QCOM help Support for Qualcomm's Network-on-Chip interconnect hardware. +config INTERCONNECT_QCOM_OSM_L3 + tristate "Qualcomm OSM L3 interconnect driver" + depends on INTERCONNECT_QCOM || COMPILE_TEST + help + Say y here to support the Operating State Manager (OSM) interconnect + driver which controls the scaling of L3 caches on Qualcomm SoCs. + config INTERCONNECT_QCOM_SDM845 tristate "Qualcomm SDM845 interconnect driver" depends on INTERCONNECT_QCOM
drivers/interconnect/qcom/Makefile +2 -0
@@ -1,5 +1,7 @@ # SPDX-License-Identifier: GPL-2.0 +icc-osm-l3-objs := osm-l3.o qnoc-sdm845-objs := sdm845.o +obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o obj-$(CONFIG_INTERCONNECT_QCOM_SDM845) += qnoc-sdm845.o
drivers/interconnect/qcom/osm-l3.c new file +284 -0
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Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, a Linux Foundation Collaborative Project