mlx5: Report ODP capabilities for DC transport
PATCH 1/1 mlx5: Report ODP capabilities for DC transport
From: Michael Guralnik <[email protected]>
Report ODP capabilities for DC through mlx5dv_query_device.
Signed-off-by Michael Guralnik <[email protected]>
Signed-off-by Yishai Hadas <[email protected]>
Signed-off-by Leon Romanovsky <[email protected]>
---
PR: https://github.com/linux-rdma/rdma-core/pull/570
Kernel: https://lore.kernel.org/linux-rdma/[email protected]
--- providers/mlx5/man/mlx5dv_query_device.3 | 5 +++ providers/mlx5/mlx5.c | 42 ++++++++++++++++++++++++ providers/mlx5/mlx5_ifc.h | 33 +++++++++++++++++++ providers/mlx5/mlx5dv.h | 2 ++ 4 files changed, 82 insertions(+)
providers/mlx5/man/mlx5dv_query_device.3 +5 -0
@@ -49,6 +49,9 @@ struct mlx5dv_cqe_comp_caps cqe_comp_caps; struct mlx5dv_sw_parsing_caps sw_parsing_caps; uint32_t tunnel_offloads_caps; uint32_t max_dynamic_bfregs /* max blue-flame registers that can be dynamiclly allocated */ +uint64_t max_clock_info_update_nsec; +uint32_t flow_action_flags; /* use enum mlx5dv_flow_action_cap_flags */ +uint32_t dc_odp_caps; /* use enum ibv_odp_transport_cap_bits */ .in -8 };
@@ -77,6 +80,8 @@ MLX5DV_CONTEXT_MASK_STRIDING_RQ = 1 << 2, MLX5DV_CONTEXT_MASK_TUNNEL_OFFLOADS = 1 << 3, MLX5DV_CONTEXT_MASK_DYN_BFREGS = 1 << 4, MLX5DV_CONTEXT_MASK_CLOCK_INFO_UPDATE = 1 << 5, +MLX5DV_CONTEXT_MASK_FLOW_ACTION_FLAGS = 1 << 6, +MLX5DV_CONTEXT_MASK_DC_ODP_CAPS = 1 << 7, .in -8 };
providers/mlx5/mlx5.c +42 -0
60 lines not on this page · raw message
providers/mlx5/mlx5_ifc.h +33 -0
@@ -972,12 +972,44 @@ struct mlx5_ifc_flow_table_eswitch_cap_bits {u8 reserved_at_1900[0x6700 ]; }; +struct mlx5_ifc_odp_per_transport_service_cap_bits { +u8 send[0x1 ]; +u8 receive[0x1 ]; +u8 write[0x1 ]; +u8 read[0x1 ]; +u8 atomic[0x1 ]; +u8 srq_receive[0x1 ]; +u8 reserved_at_6[0x1a ]; +}; + +struct mlx5_ifc_odp_cap_bits { +u8 reserved_at_0[0x40 ]; + +u8 sig[0x1 ]; +u8 reserved_at_41[0x1f ]; + +u8 reserved_at_60[0x20 ]; + +struct mlx5_ifc_odp_per_transport_service_cap_bits rc_odp_caps; + +struct mlx5_ifc_odp_per_transport_service_cap_bits uc_odp_caps; + +struct mlx5_ifc_odp_per_transport_service_cap_bits ud_odp_caps; + +struct mlx5_ifc_odp_per_transport_service_cap_bits xrc_odp_caps; + +struct mlx5_ifc_odp_per_transport_service_cap_bits dc_odp_caps; + +u8 reserved_at_120[0x6e0 ]; +}; +union mlx5_ifc_hca_cap_union_bits {struct mlx5_ifc_atomic_caps_bits atomic_caps;struct mlx5_ifc_cmd_hca_cap_bits cmd_hca_cap;struct mlx5_ifc_flow_table_nic_cap_bits flow_table_nic_cap;struct mlx5_ifc_flow_table_eswitch_cap_bits flow_table_eswitch_cap;struct mlx5_ifc_device_mem_cap_bits device_mem_cap; +struct mlx5_ifc_odp_cap_bits odp_cap;u8 reserved_at_0[0x8000 ]; };
@@ -1007,6 +1039,7 @@ struct mlx5_ifc_query_hca_cap_in_bits { };enum mlx5_cap_type { +MLX5_CAP_ODP =2 ,MLX5_CAP_ATOMIC =3 , };
providers/mlx5/mlx5dv.h +2 -0
@@ -72,6 +72,7 @@ enum mlx5dv_context_comp_mask {MLX5DV_CONTEXT_MASK_DYN_BFREGS =1 <<4 ,MLX5DV_CONTEXT_MASK_CLOCK_INFO_UPDATE =1 <<5 ,MLX5DV_CONTEXT_MASK_FLOW_ACTION_FLAGS =1 <<6 , + MLX5DV_CONTEXT_MASK_DC_ODP_CAPS = 1 << 7, }; struct mlx5dv_cqe_comp_caps {
@@ -122,6 +123,7 @@ struct mlx5dv_context {uint32_t max_dynamic_bfregs;uint64_t max_clock_info_update_nsec;uint32_t flow_action_flags;/* use enum mlx5dv_flow_action_cap_flags */ +uint32_t dc_odp_caps;/* use enum ibv_odp_transport_cap_bits */ };enum mlx5dv_context_flags {
--
2.20.1