Skip to contentSkip to conversation

New Intel CPU model numbers

PATCH New Tony Luck 1 participant 5 messages Sep 5, 2019

Subsystems (2)
x86 Intel CPU family model numbers
lore
Share & tools
lore

Tony Luck

author maintainer
#0 lore raw

cover New Intel CPU model numbers

I'm going to be more aggressive about pushing new CPU model numbers into <asm/intel-family.h>. Basically as soon as Intel talks publicly about some new model and I have the model number, then I'll post the update.

Changes to the rest of the kernel will follow at the pace of the various groups that have model specific code ready to be made public.

This series has just the model numbers for Tiger Lake and Elkhart Lake. The new Airmont variant also comes with a patch of other spots in the kernel that need updates.

Gayatri Kammela (2):
x86/cpu: Add Tiger Lake to Intel family
x86/cpu: Add Elkhart Lake to Intel family

Rahul Tanwar (2):
x86/cpu: Add new Airmont variant to Intel family x86/cpu: Update init data for new Airmont CPU model

 arch/x86/include/asm/intel-family.h | 5 +++++
 arch/x86/kernel/cpu/common.c        | 1 +
 arch/x86/kernel/cpu/intel.c         | 1 +
 arch/x86/kernel/tsc_msr.c           | 5 +++++
 4 files changed, 12 insertions(+)
Signature · 1 line
2.20.1
author maintainer
#1 lore raw

PATCH 1/4 x86/cpu: Add Tiger Lake to Intel family

From: Gayatri Kammela <[email protected]>

Add the model numbers/CPUIDs of Tiger Lake mobile and desktop to the Intel family.

Cc Peter Zijlstra <[email protected]>
Cc Tony Luck <[email protected]>
Cc Andy Shevchenko <[email protected]>
Cc Kan Liang <[email protected]>
Cc David E. Box <[email protected]>
Cc Rajneesh Bhardwaj <[email protected]>
Suggested-by Tony Luck <[email protected]>
Reviewed-by Tony Luck <[email protected]>
Signed-off-by Gayatri Kammela <[email protected]>
Signed-off-by Tony Luck <[email protected]>
---
 arch/x86/include/asm/intel-family.h | 3 +++
 1 file changed, 3 insertions(+)
arch/x86/include/asm/intel-family.h +3 -0
index 5c05b2d389c3..7c2ef2e883d5 100644
@@ -80,6 +80,9 @@
 #define INTEL_FAM6_ICELAKE_L		0x7E
 #define INTEL_FAM6_ICELAKE_NNPI		0x9D
 
+#define INTEL_FAM6_TIGERLAKE_L		0x8C
+#define INTEL_FAM6_TIGERLAKE		0x8D
+
 /* "Small Core" Processors (Atom) */
 
 #define INTEL_FAM6_ATOM_BONNELL		0x1C /* Diamondville, Pineview */
Signature · 1 line
2.20.1
author maintainer
#2 lore raw

PATCH 2/4 x86/cpu: Add Elkhart Lake to Intel family

In reply to Tony Luck

From: Gayatri Kammela <[email protected]>

Add the model number/CPUID of atom based Elkhart Lake to the Intel family.

Cc Peter Zijlstra <[email protected]>
Cc Tony Luck <[email protected]>
Cc Andy Shevchenko <[email protected]>
Cc Kan Liang <[email protected]>
Cc David E. Box <[email protected]>
Cc Rajneesh Bhardwaj <[email protected]>
Signed-off-by Gayatri Kammela <[email protected]>
Signed-off-by Tony Luck <[email protected]>
---
 arch/x86/include/asm/intel-family.h | 1 +
 1 file changed, 1 insertion(+)
arch/x86/include/asm/intel-family.h +1 -0
index 7c2ef2e883d5..55568afe798a 100644
@@ -106,6 +106,7 @@
 #define INTEL_FAM6_ATOM_GOLDMONT_PLUS	0x7A /* Gemini Lake */
 
 #define INTEL_FAM6_ATOM_TREMONT_D	0x86 /* Jacobsville */
+#define INTEL_FAM6_ATOM_TREMONT		0x96 /* Elkhart Lake */
 
 /* Xeon Phi */
Signature · 1 line
2.20.1
author maintainer
#3 lore raw

PATCH 3/4 x86/cpu: Add new Airmont variant to Intel family

In reply to Tony Luck

From: Rahul Tanwar <[email protected]>

Add new Airmont variant CPU model to Intel family.

Signed-off-by Rahul Tanwar <[email protected]>
Signed-off-by Tony Luck <[email protected]>
---
 arch/x86/include/asm/intel-family.h | 1 +
 1 file changed, 1 insertion(+)
arch/x86/include/asm/intel-family.h +1 -0
index 55568afe798a..f04622500da3 100644
@@ -98,6 +98,7 @@
 
 #define INTEL_FAM6_ATOM_AIRMONT		0x4C /* Cherry Trail, Braswell */
 #define INTEL_FAM6_ATOM_AIRMONT_MID	0x5A /* Moorefield */
+#define INTEL_FAM6_ATOM_AIRMONT_NP	0x75 /* Lightning Mountain */
 
 #define INTEL_FAM6_ATOM_GOLDMONT	0x5C /* Apollo Lake */
 #define INTEL_FAM6_ATOM_GOLDMONT_D	0x5F /* Denverton */
Signature · 1 line
2.20.1
author maintainer
#4 lore raw

PATCH 4/4 x86/cpu: Update init data for new Airmont CPU model

In reply to Tony Luck

From: Rahul Tanwar <[email protected]>

Update properties for newly added Airmont CPU variant.

Signed-off-by Rahul Tanwar <[email protected]>
Signed-off-by Tony Luck <[email protected]>
---
 arch/x86/kernel/cpu/common.c | 1 +
 arch/x86/kernel/cpu/intel.c  | 1 +
 arch/x86/kernel/tsc_msr.c    | 5 +++++
 3 files changed, 7 insertions(+)
arch/x86/kernel/cpu/common.c +1 -0
index 5cedb679215e..9ae7d1bcd4f4 100644
@@ -1059,6 +1059,7 @@ static const __initconst struct x86_cpu_id cpu_vuln_whitelist[] = {
 	VULNWL_INTEL(CORE_YONAH,		NO_SSB),
 
 	VULNWL_INTEL(ATOM_AIRMONT_MID,		NO_L1TF | MSBDS_ONLY | NO_SWAPGS),
+	VULNWL_INTEL(ATOM_AIRMONT_NP,		NO_L1TF | NO_SWAPGS),
 
 	VULNWL_INTEL(ATOM_GOLDMONT,		NO_MDS | NO_L1TF | NO_SWAPGS),
 	VULNWL_INTEL(ATOM_GOLDMONT_D,		NO_MDS | NO_L1TF | NO_SWAPGS),
arch/x86/kernel/cpu/intel.c +1 -0
index e2082ccccf13..c2fdc00df163 100644
@@ -268,6 +268,7 @@ static void early_init_intel(struct cpuinfo_x86 *c)
 		case INTEL_FAM6_ATOM_SALTWELL_MID:
 		case INTEL_FAM6_ATOM_SALTWELL_TABLET:
 		case INTEL_FAM6_ATOM_SILVERMONT_MID:
+		case INTEL_FAM6_ATOM_AIRMONT_NP:
 			set_cpu_cap(c, X86_FEATURE_NONSTOP_TSC_S3);
 			break;
 		default:
arch/x86/kernel/tsc_msr.c +5 -0
index 067858fe4db8..e0cbe4f2af49 100644
@@ -58,6 +58,10 @@ static const struct freq_desc freq_desc_ann = {
 	1, { 83300, 100000, 133300, 100000, 0, 0, 0, 0 }
 };
 
+static const struct freq_desc freq_desc_lgm = {
+	1, { 78000, 78000, 78000, 78000, 78000, 78000, 78000, 78000 }
+};
+
 static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
 	INTEL_CPU_FAM6(ATOM_SALTWELL_MID,	freq_desc_pnw),
 	INTEL_CPU_FAM6(ATOM_SALTWELL_TABLET,	freq_desc_clv),

@@ -65,6 +69,7 @@ static const struct x86_cpu_id tsc_msr_cpu_ids[] = {
 	INTEL_CPU_FAM6(ATOM_SILVERMONT_MID,	freq_desc_tng),
 	INTEL_CPU_FAM6(ATOM_AIRMONT,		freq_desc_cht),
 	INTEL_CPU_FAM6(ATOM_AIRMONT_MID,	freq_desc_ann),
+	INTEL_CPU_FAM6(ATOM_AIRMONT_NP,		freq_desc_lgm),
 	{}
 };
Signature · 1 line
2.20.1