Enable Sub-page Write Protection Support
Subsystems (4)
v5 cover Enable Sub-page Write Protection Support
EPT-Based Sub-Page write Protection(SPP)is a HW capability which allows Virtual Machine Monitor(VMM) to specify write-permission for guest physical memory at a sub-page(128 byte) granularity. When this capability is enabled, the CPU enforces write-access check for sub-pages within a 4KB page.
The feature is targeted to provide fine-grained memory protection for usages such as device virtualization, memory check-point and VM introspection etc.
SPP is active when the "sub-page write protection" (bit 23) is 1 in Secondary VM-Execution Controls. The feature is backed with a Sub-Page Permission Table(SPPT), SPPT is referenced via a 64-bit control field called Sub-Page Permission Table Pointer (SPPTP) which contains a 4K-aligned physical address.
To enable SPP for certain physical page, the gfn should be first mapped to a 4KB entry, then set bit 61 of the corresponding EPT leaf entry. While HW walks EPT, if bit 61 is set, it traverses SPPT with the guset physical address to find out the sub-page permissions at the leaf entry. If the corresponding bit is set, write to sub-page is permitted, otherwise, SPP induced EPT violation is generated.
This patch serial passed SPP function test and selftest on Ice-Lake platform.
Please refer to the SPP introduction document in this patch set and Intel SDM for details:
Intel SDM:
https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
SPP selftest patch:
https://lkml.org/lkml/2019/6/18/1197
Previous patch:
https://lkml.org/lkml/2019/8/14/97
Patch 1: Introduction to SPP.
Patch 2: Add SPP related flags and control bits. Patch 3: Functions for SPPT setup.
Patch 4: Add SPP access bitmaps for memslots. Patch 5: Introduce SPP {init,set,get} functions Patch 6: Implement User space access IOCTLs. Patch 7: Set up SPP paging table at vm-entry/exit. Patch 8: Enable lazy mode SPPT setup.
Patch 9: Handle SPP protected pages when VM memory changes
Change logs:
V5 -> V4:
1. Enable SPP support for Hugepage(1GB/2MB) to extend application.
2. Make SPP miss vm-exit handler as the unified place to set up SPPT.
3. If SPP protected pages are access-tracked or dirty-page-tracked, store SPP flag in reserved address bit, restore it in fast_page_fault() handler.
4. Move SPP specific functions to vmx/spp.c and vmx/spp.h
5. Rebased code to kernel v5.3
6. Other change suggested by KVM community.
V3 -> V4:
1. Modified documentation to make it consistent with patches.
2. Allocated SPPT root page in init_spp() instead of vmx_set_cr3() to avoid SPPT miss error.
3. Added back co-developers and sign-offs.
V2 -> V3:
1. Rebased patches to kernel 5.1 release
2. Deferred SPPT setup to EPT fault handler if the page is not available while set_subpage() is being called.
3. Added init IOCTL to reduce extra cost if SPP is not used.
4. Refactored patch structure, cleaned up cross referenced functions.
5. Added code to deal with memory swapping/migration/shrinker cases.
V2 -> V1:
1. Rebased to 4.20-rc1
2. Move VMCS change to a separated patch.
3. Code refine and Bug fix
Yang Weijiang (9):
Documentation: Introduce EPT based Subpage Protection
vmx: spp: Add control flags for Sub-Page Protection(SPP)
mmu: spp: Add SPP Table setup functions
mmu: spp: Add functions to create/destroy SPP bitmap block
mmu: spp: Introduce SPP {init,set,get} functions
x86: spp: Introduce user-space SPP IOCTLs
vmx: spp: Set up SPP paging table at vm-entry/exit
mmu: spp: Enable Lazy mode SPP protection
mmu: spp: Handle SPP protected pages when VM memory changes
Documentation/virtual/kvm/spp_kvm.txt | 178 +++++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/kvm_host.h | 10 +- arch/x86/include/asm/vmx.h | 10 + arch/x86/include/uapi/asm/vmx.h | 2 + arch/x86/kernel/cpu/intel.c | 4 + arch/x86/kvm/mmu.c | 78 ++- arch/x86/kvm/mmu.h | 2 + arch/x86/kvm/vmx/capabilities.h | 5 + arch/x86/kvm/vmx/spp.c | 651 ++++++++++++++++++++++++++ arch/x86/kvm/vmx/spp.h | 27 ++ arch/x86/kvm/vmx/vmx.c | 99 ++++ arch/x86/kvm/x86.c | 51 ++ include/uapi/linux/kvm.h | 17 + 14 files changed, 1133 insertions(+), 2 deletions(-) create mode 100644 Documentation/virtual/kvm/spp_kvm.txt create mode 100644 arch/x86/kvm/vmx/spp.c create mode 100644 arch/x86/kvm/vmx/spp.h
Signature · 1 line
2.17.2
PATCH v5 1/9 Documentation: Introduce EPT based Subpage Protection
--- Documentation/virtual/kvm/spp_kvm.txt | 178 ++++++++++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/virtual/kvm/spp_kvm.txt
Documentation/virtual/kvm/spp_kvm.txt new file +178 -0
@@ -0,0 +1,178 @@ +EPT-Based Sub-Page Protection (SPP) for KVM +==================================================== + +1.Overview + EPT-based Sub-Page Protection(SPP) allows VMM to specify + fine-grained(128byte per sub-page) write-protection for guest physical + memory. When it's enabled, the CPU enforces write-access permission + for the sub-pages within a 4KB page, if corresponding bit is set in + permission vector, write to sub-page region is allowed, otherwise, + it's prevented with a EPT violation. + + *Note*: In current implementation, SPP is exclusive with nested flag, + if it's on, SPP feature won't work. + +2.SPP Operation + Sub-Page Protection Table (SPPT) is introduced to manage sub-page + write-access permission. + + It is active when: + a) nested flag is turned off. + b) "sub-page write protection" VM-execution control is 1. + c) SPP is initialized with KVM_INIT_SPP ioctl. + d) Sub-page permissions are set with KVM_SUBPAGES_SET_ACCESS ioctl. + see below sections for details. + + __________________________________________________________________________ + + How SPP hardware works: + __________________________________________________________________________ + + Guest write access --> GPA --> Walk EPT --> EPT leaf entry -----| + |---------------------------------------------------------------| + |-> if VMexec_control.spp && ept_leaf_entry.spp_bit (bit 61) + | + |-> <false> --> EPT legacy behavior + | + | + |-> <true> --> if ept_leaf_entry.writable + | + |-> <true> --> Ignore SPP + | + |-> <false> --> GPA --> Walk SPP 4-level table--| + | + |------------<----------get-the-SPPT-point-from-VMCS-filed-----<------| + | + Walk SPP L4E table + | + |---> if-entry-misconfiguration ------------>-------|-------<---------| + | | | + else | | + | | | + | |------------------SPP VMexit<-----------------| | + | | | + | |-> exit_qualification & sppt_misconfig --> sppt misconfig | + | | | + | |-> exit_qualification & sppt_miss --> sppt miss | + |---| | + | | + walk SPPT L3E--|--> if-entry-misconfiguration------------>------------| + | | + else | + | | + | | + walk SPPT L2E --|--> if-entry-misconfiguration-------->-------| + | | + else | + | | + | | + walk SPPT L1E --|-> if-entry-misconfiguration--->----| + | + else + | + |-> if sub-page writable + |-> <true> allow, write access + |-> <false> disallow, EPT violation + ______________________________________________________________________________ + +3.IOCTL Interfaces + + KVM_INIT_SPP: + Allocate storage for sub-page permission vectors and SPPT root page. + + KVM_SUBPAGES_GET_ACCESS: + Get sub-page write permission vectors for given continuous guest pages. + + KVM_SUBPAGES_SET_ACCESS + Set SPP bit in EPT leaf entries for given continuous guest pages. The + actual SPPT setup is triggered when SPP miss vm-exit is handled. + + /* for KVM_SUBPAGES_GET_ACCESS and KVM_SUBPAGES_SET_ACCESS */ + struct kvm_subpage_info { + __u64 gfn; /* the first page gfn of the continuous pages */ + __u64 npages; /* number of 4K pages */ + __u64 *access_map; /* sub-page write-access bitmap array */ + }; + + #define KVM_SUBPAGES_GET_ACCESS _IOR(KVMIO, 0x49, __u64) + #define KVM_SUBPAGES_SET_ACCESS _IOW(KVMIO, 0x4a, __u64) + #define KVM_INIT_SPP _IOW(KVMIO, 0x4b, __u64) + +4.Set Sub-Page Permission + + * To enable SPP protection, system admin sets sub-page permission via + KVM_SUBPAGES_SET_ACCESS ioctl: + (1) It first stores the access permissions in bitmap array. + + (2) Then, if the target 4KB page is mapped as PT_PAGE_TABLE_LEVEL entry in EPT, + it sets SPP bit of the corresponding entry to mark sub-page protection. + If the 4KB page is mapped as PT_DIRECTORY_LEVEL or PT_PDPE_LEVEL, it + zapps the hugepage entry and let following memroy access to trigger EPT + page fault, there the gfn is check against SPP permission bitmap and + proper level is selected to set up EPT entry. + + + The SPPT paging structure format is as below: + + Format of the SPPT L4E, L3E, L2E: + | Bit | Contents | + | :----- | :------------------------------------------------------------------------| + | 0 | Valid entry when set; indicates whether the entry is present | + | 11:1 | Reserved (0) | + | N-1:12 | Physical address of 4KB aligned SPPT LX-1 Table referenced by this entry | + | 51:N | Reserved (0) | + | 63:52 | Reserved (0) | + Note: N is the physical address width supported by the processor. X is the page level + + Format of the SPPT L1E: + | Bit | Contents | + | :---- | :---------------------------------------------------------------- | + | 0+2i | Write permission for i-th 128 byte sub-page region. | + | 1+2i | Reserved (0). | + Note: 0<=i<=31 + +5.SPPT-induced VM exit + + * SPPT miss and misconfiguration induced VM exit + + A SPPT missing VM exit occurs when walk the SPPT, there is no SPPT + misconfiguration but a paging-structure entry is not + present in any of L4E/L3E/L2E entries. + + A SPPT misconfiguration VM exit occurs when reserved bits or unsupported values + are set in SPPT entry. + + *NOTE* SPPT miss and SPPT misconfigurations can occur only due to an + attempt to write memory with a guest physical address. + + * SPP permission induced VM exit + SPP sub-page permission induced violation is reported as EPT violation + thesefore causes VM exit. + +6.SPPT-induced VM exit handling + + #define EXIT_REASON_SPP 66 + + static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { + ... + [EXIT_REASON_SPP] = handle_spp, + ... + }; + + New exit qualification for SPPT-induced vmexits. + + | Bit | Contents | + | :---- | :---------------------------------------------------------------- | + | 10:0 | Reserved (0). | + | 11 | SPPT VM exit type. Set for SPPT Miss, cleared for SPPT Misconfig. | + | 12 | NMI unblocking due to IRET | + | 63:13 | Reserved (0) | + + In addition to the exit qualification, guest linear address and guest + physical address fields will be reported. + + * SPPT miss and misconfiguration induced VM exit + Set up SPPT entries correctly. + + * SPP permission induced VM exit + This kind of VM exit is left to VMI tool to handle.
Signature · 1 line
2.17.2
Re: [PATCH v5 1/9] Documentation: Introduce EPT based Subpage Protection
Quoted 49 lines · Yang Weijiang
Co-developed-by [email protected]Signed-off-by [email protected]Signed-off-by Yang Weijiang <[email protected]>--- Documentation/virtual/kvm/spp_kvm.txt | 178 ++++++++++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/virtual/kvm/spp_kvm.txtDocumentation/virtual/kvm/spp_kvm.txt new file +34
-0@@ -0,0 +1,178 @@ +EPT-Based Sub-Page Protection (SPP) for KVM +==================================================== + +1.Overview + EPT-based Sub-Page Protection(SPP) allows VMM to specify + fine-grained(128byte per sub-page) write-protection for guest physical + memory. When it's enabled, the CPU enforces write-access permission + for the sub-pages within a 4KB page, if corresponding bit is set in + permission vector, write to sub-page region is allowed, otherwise, + it's prevented with a EPT violation. + + *Note*: In current implementation, SPP is exclusive with nested flag, + if it's on, SPP feature won't work. + +2.SPP Operation + Sub-Page Protection Table (SPPT) is introduced to manage sub-page + write-access permission. + + It is active when: + a) nested flag is turned off. + b) "sub-page write protection" VM-execution control is 1. + c) SPP is initialized with KVM_INIT_SPP ioctl. + d) Sub-page permissions are set with KVM_SUBPAGES_SET_ACCESS ioctl. + see below sections for details. + + __________________________________________________________________________ + + How SPP hardware works: + __________________________________________________________________________ + + Guest write access --> GPA --> Walk EPT --> EPT leaf entry -----| + |---------------------------------------------------------------| + |-> if VMexec_control.spp && ept_leaf_entry.spp_bit (bit 61) + |
Documentation/virtual/kvm/spp_kvm.txt line 44
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Documentation/virtual/kvm/spp_kvm.txt new file +10
-0+ |-> <false> --> EPT legacy behavior + | + | + |-> <true> --> if ept_leaf_entry.writable + | + |-> <true> --> Ignore SPP + | + |-> <false> --> GPA --> Walk SPP 4-level table--| + | + |------------<----------get-the-SPPT-point-from-VMCS-filed-----<------|
/filed/field/
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Documentation/virtual/kvm/spp_kvm.txt new file +30
-0+ | + Walk SPP L4E table + | + |---> if-entry-misconfiguration ------------>-------|-------<---------| + | | | + else | | + | | | + | |------------------SPP VMexit<-----------------| | + | | | + | |-> exit_qualification & sppt_misconfig --> sppt misconfig | + | | | + | |-> exit_qualification & sppt_miss --> sppt miss | + |---| | + | | + walk SPPT L3E--|--> if-entry-misconfiguration------------>------------| + | | + else | + | | + | | + walk SPPT L2E --|--> if-entry-misconfiguration-------->-------| + | | + else | + | | + | | + walk SPPT L1E --|-> if-entry-misconfiguration--->----| + | + else + | + |-> if sub-page writable + |-> <true> allow, write access
Documentation/virtual/kvm/spp_kvm.txt line 84
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Documentation/virtual/kvm/spp_kvm.txt new file +10
-0+ |-> <false> disallow, EPT violation + ______________________________________________________________________________ + +3.IOCTL Interfaces + + KVM_INIT_SPP: + Allocate storage for sub-page permission vectors and SPPT root page. + + KVM_SUBPAGES_GET_ACCESS: + Get sub-page write permission vectors for given continuous guest pages.
/continuous/contiguous/
Documentation/virtual/kvm/spp_kvm.txt line 87
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Documentation/virtual/kvm/spp_kvm.txt new file +3
-0+ + KVM_SUBPAGES_SET_ACCESS + Set SPP bit in EPT leaf entries for given continuous guest pages. The
/continuous/contiguous/
Documentation/virtual/kvm/spp_kvm.txt line 92
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Documentation/virtual/kvm/spp_kvm.txt new file +5
-0+ actual SPPT setup is triggered when SPP miss vm-exit is handled. + + /* for KVM_SUBPAGES_GET_ACCESS and KVM_SUBPAGES_SET_ACCESS */ + struct kvm_subpage_info { + __u64 gfn; /* the first page gfn of the continuous pages */
/continuous/contiguous/
Documentation/virtual/kvm/spp_kvm.txt line 99
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Documentation/virtual/kvm/spp_kvm.txt new file +7
-0+ __u64 npages; /* number of 4K pages */ + __u64 *access_map; /* sub-page write-access bitmap array */ + }; + + #define KVM_SUBPAGES_GET_ACCESS _IOR(KVMIO, 0x49, __u64) + #define KVM_SUBPAGES_SET_ACCESS _IOW(KVMIO, 0x4a, __u64) + #define KVM_INIT_SPP _IOW(KVMIO, 0x4b, __u64)
The ioctls should be documented in api.txt.
Documentation/virtual/kvm/spp_kvm.txt line 103
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Documentation/virtual/kvm/spp_kvm.txt new file +3
-0+4.Set Sub-Page Permission + + * To enable SPP protection, system admin sets sub-page permission via
Why system admin? Can't any kvm user do this?
Documentation/virtual/kvm/spp_kvm.txt line 107
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Documentation/virtual/kvm/spp_kvm.txt new file +4
-0+ KVM_SUBPAGES_SET_ACCESS ioctl: + (1) It first stores the access permissions in bitmap array. + + (2) Then, if the target 4KB page is mapped as PT_PAGE_TABLE_LEVEL entry in EPT,
/page is/pages are/
Documentation/virtual/kvm/spp_kvm.txt line 109
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Documentation/virtual/kvm/spp_kvm.txt new file +2
-0+ it sets SPP bit of the corresponding entry to mark sub-page protection. + If the 4KB page is mapped as PT_DIRECTORY_LEVEL or PT_PDPE_LEVEL, it
/page is/pages are/
Documentation/virtual/kvm/spp_kvm.txt line 110
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Documentation/virtual/kvm/spp_kvm.txt new file +1
-0+ zapps the hugepage entry and let following memroy access to trigger EPT
/zapps/zaps/, /entry/enttries/, /memroy/memory/
Documentation/virtual/kvm/spp_kvm.txt line 111
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Documentation/virtual/kvm/spp_kvm.txt new file +1
-0+ page fault, there the gfn is check against SPP permission bitmap and
/page fault/violation/
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Documentation/virtual/kvm/spp_kvm.txt new file +25
-0+ proper level is selected to set up EPT entry. + + + The SPPT paging structure format is as below: + + Format of the SPPT L4E, L3E, L2E: + | Bit | Contents | + | :----- | :------------------------------------------------------------------------| + | 0 | Valid entry when set; indicates whether the entry is present | + | 11:1 | Reserved (0) | + | N-1:12 | Physical address of 4KB aligned SPPT LX-1 Table referenced by this entry | + | 51:N | Reserved (0) | + | 63:52 | Reserved (0) | + Note: N is the physical address width supported by the processor. X is the page level + + Format of the SPPT L1E: + | Bit | Contents | + | :---- | :---------------------------------------------------------------- | + | 0+2i | Write permission for i-th 128 byte sub-page region. | + | 1+2i | Reserved (0). | + Note: 0<=i<=31 + +5.SPPT-induced VM exit + + * SPPT miss and misconfiguration induced VM exit
Documentation/virtual/kvm/spp_kvm.txt line 146
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Documentation/virtual/kvm/spp_kvm.txt new file +10
-0+ + A SPPT missing VM exit occurs when walk the SPPT, there is no SPPT + misconfiguration but a paging-structure entry is not + present in any of L4E/L3E/L2E entries. + + A SPPT misconfiguration VM exit occurs when reserved bits or unsupported values + are set in SPPT entry. + + *NOTE* SPPT miss and SPPT misconfigurations can occur only due to an + attempt to write memory with a guest physical address.
Can you clarify what this means? For instance, setting an A or D bit in a PTE is an attempt to "write memory with a guest physical address," but per the SDM, it is not an operation that is eligible for sub-page write permissions.
Documentation/virtual/kvm/spp_kvm.txt line 150
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Documentation/virtual/kvm/spp_kvm.txt new file +3
-0+ * SPP permission induced VM exit + SPP sub-page permission induced violation is reported as EPT violation + thesefore causes VM exit.
/thesefore/therefore/
Quoted 31 lines
Documentation/virtual/kvm/spp_kvm.txt new file +28
-1+ +6.SPPT-induced VM exit handling + + #define EXIT_REASON_SPP 66 + + static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { + ... + [EXIT_REASON_SPP] = handle_spp, + ... + }; + + New exit qualification for SPPT-induced vmexits. + + | Bit | Contents | + | :---- | :---------------------------------------------------------------- | + | 10:0 | Reserved (0). | + | 11 | SPPT VM exit type. Set for SPPT Miss, cleared for SPPT Misconfig. | + | 12 | NMI unblocking due to IRET | + | 63:13 | Reserved (0) | + + In addition to the exit qualification, guest linear address and guest + physical address fields will be reported. + + * SPPT miss and misconfiguration induced VM exit + Set up SPPT entries correctly. + + * SPP permission induced VM exit + This kind of VM exit is left to VMI tool to handle. --2.17.2
Re: [PATCH v5 1/9] Documentation: Introduce EPT based Subpage Protection
Quoted 94 lines · Jim Mattson
Quoted 49 lines · Yang Weijiang
Co-developed-by [email protected]Signed-off-by [email protected]Signed-off-by Yang Weijiang <[email protected]>--- Documentation/virtual/kvm/spp_kvm.txt | 178 ++++++++++++++++++++++++++ 1 file changed, 178 insertions(+) create mode 100644 Documentation/virtual/kvm/spp_kvm.txtDocumentation/virtual/kvm/spp_kvm.txt new file +34
-0@@ -0,0 +1,178 @@ +EPT-Based Sub-Page Protection (SPP) for KVM +==================================================== + +1.Overview + EPT-based Sub-Page Protection(SPP) allows VMM to specify + fine-grained(128byte per sub-page) write-protection for guest physical + memory. When it's enabled, the CPU enforces write-access permission + for the sub-pages within a 4KB page, if corresponding bit is set in + permission vector, write to sub-page region is allowed, otherwise, + it's prevented with a EPT violation. + + *Note*: In current implementation, SPP is exclusive with nested flag, + if it's on, SPP feature won't work. + +2.SPP Operation + Sub-Page Protection Table (SPPT) is introduced to manage sub-page + write-access permission. + + It is active when: + a) nested flag is turned off. + b) "sub-page write protection" VM-execution control is 1. + c) SPP is initialized with KVM_INIT_SPP ioctl. + d) Sub-page permissions are set with KVM_SUBPAGES_SET_ACCESS ioctl. + see below sections for details. + + __________________________________________________________________________ + + How SPP hardware works: + __________________________________________________________________________ + + Guest write access --> GPA --> Walk EPT --> EPT leaf entry -----| + |---------------------------------------------------------------| + |-> if VMexec_control.spp && ept_leaf_entry.spp_bit (bit 61) + |Documentation/virtual/kvm/spp_kvm.txt line 44
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Documentation/virtual/kvm/spp_kvm.txt new file +10
-0+ |-> <false> --> EPT legacy behavior + | + | + |-> <true> --> if ept_leaf_entry.writable + | + |-> <true> --> Ignore SPP + | + |-> <false> --> GPA --> Walk SPP 4-level table--| + | + |------------<----------get-the-SPPT-point-from-VMCS-filed-----<------|/filed/field/
Quoted 33 lines
Documentation/virtual/kvm/spp_kvm.txt new file +33
-0+ | + Walk SPP L4E table + | + |---> if-entry-misconfiguration ------------>-------|-------<---------| + | | | + else | | + | | | + | |------------------SPP VMexit<-----------------| | + | | | + | |-> exit_qualification & sppt_misconfig --> sppt misconfig | + | | | + | |-> exit_qualification & sppt_miss --> sppt miss | + |---| | + | | + walk SPPT L3E--|--> if-entry-misconfiguration------------>------------| + | | + else | + | | + | | + walk SPPT L2E --|--> if-entry-misconfiguration-------->-------| + | | + else | + | | + | | + walk SPPT L1E --|-> if-entry-misconfiguration--->----| + | + else + | + |-> if sub-page writable + |-> <true> allow, write access + |-> <false> disallow, EPT violation + ______________________________________________________________________________ +
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Documentation/virtual/kvm/spp_kvm.txt line 84
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Documentation/virtual/kvm/spp_kvm.txt new file +7
-0+3.IOCTL Interfaces + + KVM_INIT_SPP: + Allocate storage for sub-page permission vectors and SPPT root page. + + KVM_SUBPAGES_GET_ACCESS: + Get sub-page write permission vectors for given continuous guest pages./continuous/contiguous/
Thanks for all the corrections.
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Documentation/virtual/kvm/spp_kvm.txt line 87
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Documentation/virtual/kvm/spp_kvm.txt new file +3
-0+ + KVM_SUBPAGES_SET_ACCESS + Set SPP bit in EPT leaf entries for given continuous guest pages. The/continuous/contiguous/
Documentation/virtual/kvm/spp_kvm.txt line 92
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Documentation/virtual/kvm/spp_kvm.txt new file +5
-0+ actual SPPT setup is triggered when SPP miss vm-exit is handled. + + /* for KVM_SUBPAGES_GET_ACCESS and KVM_SUBPAGES_SET_ACCESS */ + struct kvm_subpage_info { + __u64 gfn; /* the first page gfn of the continuous pages *//continuous/contiguous/
Documentation/virtual/kvm/spp_kvm.txt line 99
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Documentation/virtual/kvm/spp_kvm.txt new file +7
-0+ __u64 npages; /* number of 4K pages */ + __u64 *access_map; /* sub-page write-access bitmap array */ + }; + + #define KVM_SUBPAGES_GET_ACCESS _IOR(KVMIO, 0x49, __u64) + #define KVM_SUBPAGES_SET_ACCESS _IOW(KVMIO, 0x4a, __u64) + #define KVM_INIT_SPP _IOW(KVMIO, 0x4b, __u64)
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The ioctls should be documented in api.txt.
Sure, will do it.
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Documentation/virtual/kvm/spp_kvm.txt line 103
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Documentation/virtual/kvm/spp_kvm.txt new file +3
-0+4.Set Sub-Page Permission + + * To enable SPP protection, system admin sets sub-page permission viaWhy system admin? Can't any kvm user do this?
Oops, will change it.
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Documentation/virtual/kvm/spp_kvm.txt line 107
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Documentation/virtual/kvm/spp_kvm.txt new file +4
-0+ KVM_SUBPAGES_SET_ACCESS ioctl: + (1) It first stores the access permissions in bitmap array. + + (2) Then, if the target 4KB page is mapped as PT_PAGE_TABLE_LEVEL entry in EPT,/page is/pages are/
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Documentation/virtual/kvm/spp_kvm.txt new file +2
-0+ it sets SPP bit of the corresponding entry to mark sub-page protection. + If the 4KB page is mapped as PT_DIRECTORY_LEVEL or PT_PDPE_LEVEL, it/page is/pages are/
Documentation/virtual/kvm/spp_kvm.txt line 110
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Documentation/virtual/kvm/spp_kvm.txt new file +1
-0+ zapps the hugepage entry and let following memroy access to trigger EPT/zapps/zaps/, /entry/enttries/, /memroy/memory/
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-0+ page fault, there the gfn is check against SPP permission bitmap and/page fault/violation/
Quoted 32 lines
Documentation/virtual/kvm/spp_kvm.txt new file +32
-0+ proper level is selected to set up EPT entry. + + + The SPPT paging structure format is as below: + + Format of the SPPT L4E, L3E, L2E: + | Bit | Contents | + | :----- | :------------------------------------------------------------------------| + | 0 | Valid entry when set; indicates whether the entry is present | + | 11:1 | Reserved (0) | + | N-1:12 | Physical address of 4KB aligned SPPT LX-1 Table referenced by this entry | + | 51:N | Reserved (0) | + | 63:52 | Reserved (0) | + Note: N is the physical address width supported by the processor. X is the page level + + Format of the SPPT L1E: + | Bit | Contents | + | :---- | :---------------------------------------------------------------- | + | 0+2i | Write permission for i-th 128 byte sub-page region. | + | 1+2i | Reserved (0). | + Note: 0<=i<=31 + +5.SPPT-induced VM exit + + * SPPT miss and misconfiguration induced VM exit + + A SPPT missing VM exit occurs when walk the SPPT, there is no SPPT + misconfiguration but a paging-structure entry is not + present in any of L4E/L3E/L2E entries. + + A SPPT misconfiguration VM exit occurs when reserved bits or unsupported values + are set in SPPT entry.
Quoted 8 lines
Documentation/virtual/kvm/spp_kvm.txt line 146
Quoted 3 lines
Documentation/virtual/kvm/spp_kvm.txt new file +3
-0+ + *NOTE* SPPT miss and SPPT misconfigurations can occur only due to an + attempt to write memory with a guest physical address.Can you clarify what this means? For instance, setting an A or D bit in a PTE is an attempt to "write memory with a guest physical address," but per the SDM, it is not an operation that is eligible for sub-page write permissions.
Yep, should be "memory write mapped by EPT leaf entry and guarded by SPP". thanks!
Quoted 37 lines
Documentation/virtual/kvm/spp_kvm.txt line 150
Quoted 4 lines
Documentation/virtual/kvm/spp_kvm.txt new file +3
-0+ * SPP permission induced VM exit + SPP sub-page permission induced violation is reported as EPT violation + thesefore causes VM exit./thesefore/therefore/
Quoted 31 lines
Documentation/virtual/kvm/spp_kvm.txt new file +28
-1+ +6.SPPT-induced VM exit handling + + #define EXIT_REASON_SPP 66 + + static int (*const kvm_vmx_exit_handlers[])(struct kvm_vcpu *vcpu) = { + ... + [EXIT_REASON_SPP] = handle_spp, + ... + }; + + New exit qualification for SPPT-induced vmexits. + + | Bit | Contents | + | :---- | :---------------------------------------------------------------- | + | 10:0 | Reserved (0). | + | 11 | SPPT VM exit type. Set for SPPT Miss, cleared for SPPT Misconfig. | + | 12 | NMI unblocking due to IRET | + | 63:13 | Reserved (0) | + + In addition to the exit qualification, guest linear address and guest + physical address fields will be reported. + + * SPPT miss and misconfiguration induced VM exit + Set up SPPT entries correctly. + + * SPP permission induced VM exit + This kind of VM exit is left to VMI tool to handle. --2.17.2
PATCH v5 2/9 vmx: spp: Add control flags for Sub-Page Protection(SPP)
In reply to Yang WeijiangCheck SPP capability in MSR_IA32_VMX_PROCBASED_CTLS2, its 23-bit indicates SPP capability. Enable SPP feature bit in CPU capabilities bitmap if it's supported.
--- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/vmx.h | 1 + arch/x86/kernel/cpu/intel.c | 4 ++++ arch/x86/kvm/mmu.h | 2 ++ arch/x86/kvm/vmx/capabilities.h | 5 +++++ arch/x86/kvm/vmx/vmx.c | 10 ++++++++++ 6 files changed, 23 insertions(+)
arch/x86/include/asm/cpufeatures.h +1 -0
@@ -228,6 +228,7 @@#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2)/* Intel FlexPriority */ #define X86_FEATURE_EPT ( 8*32+ 3)/* Intel Extended Page Table */ #define X86_FEATURE_VPID ( 8*32+ 4)/* Intel Virtual Processor ID */ +#define X86_FEATURE_SPP ( 8*32+ 5)/* Intel EPT-based Sub-Page Write Protection */ #define X86_FEATURE_VMMCALL ( 8*32+15)/* Prefer VMMCALL to VMCALL */ #define X86_FEATURE_XENPV ( 8*32+16)/* "" Xen paravirtual guest */
arch/x86/include/asm/vmx.h +1 -0
@@ -68,6 +68,7 @@#define SECONDARY_EXEC_XSAVES 0x00100000#define SECONDARY_EXEC_PT_USE_GPA 0x01000000#define SECONDARY_EXEC_MODE_BASED_EPT_EXEC 0x00400000 +#define SECONDARY_EXEC_ENABLE_SPP 0x00800000#define SECONDARY_EXEC_TSC_SCALING 0x02000000#define PIN_BASED_EXT_INTR_MASK 0x00000001
arch/x86/kernel/cpu/intel.c +4 -0
@@ -503,6 +503,7 @@ static void detect_vmx_virtcap(struct cpuinfo_x86 *c)#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020#define x86_VMX_FEATURE_EPT_CAP_AD 0x00200000 +#define X86_VMX_FEATURE_PROC_CTLS2_SPP 0x00800000u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;u32 msr_vpid_cap, msr_ept_cap;
@@ -513,6 +514,7 @@ static void detect_vmx_virtcap(struct cpuinfo_x86 *c)clear_cpu_cap (c,X86_FEATURE_EPT );clear_cpu_cap (c,X86_FEATURE_VPID );clear_cpu_cap (c,X86_FEATURE_EPT_AD ); +clear_cpu_cap (c,X86_FEATURE_SPP );rdmsr (MSR_IA32_VMX_PROCBASED_CTLS , vmx_msr_low, vmx_msr_high); msr_ctl = vmx_msr_high | vmx_msr_low;
@@ -536,6 +538,8 @@ static void detect_vmx_virtcap(struct cpuinfo_x86 *c) }if (msr_ctl2 &X86_VMX_FEATURE_PROC_CTLS2_VPID )set_cpu_cap (c,X86_FEATURE_VPID ); +if (msr_ctl2 &X86_VMX_FEATURE_PROC_CTLS2_SPP ) +set_cpu_cap (c,X86_FEATURE_SPP ); } }
arch/x86/kvm/mmu.h +2 -0
@@ -26,6 +26,8 @@#define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)#define PT_PAT_MASK (1ULL << 7)#define PT_GLOBAL_MASK (1ULL << 8) +#define PT_SPP_SHIFT 61 +#define PT_SPP_MASK (1ULL << PT_SPP_SHIFT)#define PT64_NX_SHIFT 63#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)
arch/x86/kvm/vmx/capabilities.h +5 -0
@@ -241,6 +241,11 @@ static inline bool cpu_has_vmx_pml(void)return vmcs_config.cpu_based_2nd_exec_ctrl &SECONDARY_EXEC_ENABLE_PML ; } +static inline bool cpu_has_vmx_ept_spp (void ) +{ +return vmcs_config.cpu_based_2nd_exec_ctrl &SECONDARY_EXEC_ENABLE_SPP ; +} +static inline bool vmx_xsaves_supported (void ) { return vmcs_config.cpu_based_2nd_exec_ctrl &
arch/x86/kvm/vmx/vmx.c +10 -0
@@ -60,6 +60,7 @@#include "vmcs12.h" #include "vmx.h" #include "x86.h" +#include "spp.h" MODULE_AUTHOR ("Qumranet" );MODULE_LICENSE ("GPL" );
@@ -113,6 +114,7 @@ module_param_named(pml, enable_pml, bool, S_IRUGO);static bool __read_mostly dump_invalid_vmcs =0 ;module_param (dump_invalid_vmcs, bool,0644 ); +static bool __read_mostly spp_supported =0 ;#define MSR_BITMAP_MODE_X2APIC 1#define MSR_BITMAP_MODE_X2APIC_APICV 2
@@ -2279,6 +2281,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,SECONDARY_EXEC_RDSEED_EXITING |SECONDARY_EXEC_RDRAND_EXITING |SECONDARY_EXEC_ENABLE_PML | +SECONDARY_EXEC_ENABLE_SPP |SECONDARY_EXEC_TSC_SCALING |SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX |
@@ -3931,6 +3934,9 @@ static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)if (!enable_pml) exec_control &= ~SECONDARY_EXEC_ENABLE_PML ; +if (!spp_supported) + exec_control &= ~SECONDARY_EXEC_ENABLE_SPP ; +if (vmx_xsaves_supported ()) {/* Exposing XSAVES only when XSAVE is exposed */ bool xsaves_enabled =
@@ -7521,6 +7527,10 @@ static __init int hardware_setup(void)if (!cpu_has_vmx_flexpriority ()) flexpriority_enabled =0 ; +if (cpu_has_vmx_ept_spp () && enable_ept && +boot_cpu_has (X86_FEATURE_SPP )) + spp_supported =1 ; +if (!cpu_has_virtual_nmis ()) enable_vnmi =0 ;
Signature · 1 line
2.17.2
Re: [PATCH v5 2/9] vmx: spp: Add control flags for Sub-Page Protection(SPP)
Quoted 64 lines · Yang Weijiang
Check SPP capability in
MSR_IA32_VMX_PROCBASED_CTLS2, its 23-bit indicates SPP capability. Enable SPP feature bit in CPU capabilities bitmap if it's supported.Co-developed-by He Chen <[email protected]>Signed-off-by He Chen <[email protected]>Co-developed-by Zhang Yi <[email protected]>Signed-off-by Zhang Yi <[email protected]>Signed-off-by Yang Weijiang <[email protected]>--- arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/vmx.h | 1 + arch/x86/kernel/cpu/intel.c | 4 ++++ arch/x86/kvm/mmu.h | 2 ++ arch/x86/kvm/vmx/capabilities.h | 5 +++++ arch/x86/kvm/vmx/vmx.c | 10 ++++++++++ 6 files changed, 23 insertions(+)arch/x86/include/asm/cpufeatures.h +1
-0@@ -228,6 +228,7 @@#define X86_FEATURE_FLEXPRIORITY ( 8*32+ 2)/* Intel FlexPriority */ #define X86_FEATURE_EPT ( 8*32+ 3)/* Intel Extended Page Table */ #define X86_FEATURE_VPID ( 8*32+ 4)/* Intel Virtual Processor ID */ +#define X86_FEATURE_SPP ( 8*32+ 5)/* Intel EPT-based Sub-Page Write Protection */ #define X86_FEATURE_VMMCALL ( 8*32+15)/* Prefer VMMCALL to VMCALL */ #define X86_FEATURE_XENPV ( 8*32+16)/* "" Xen paravirtual guest */ arch/x86/include/asm/vmx.h +1
-0@@ -68,6 +68,7 @@#define SECONDARY_EXEC_XSAVES 0x00100000#define SECONDARY_EXEC_PT_USE_GPA 0x01000000#define SECONDARY_EXEC_MODE_BASED_EPT_EXEC 0x00400000 +#define SECONDARY_EXEC_ENABLE_SPP 0x00800000#define SECONDARY_EXEC_TSC_SCALING 0x02000000#define PIN_BASED_EXT_INTR_MASK 0x00000001arch/x86/kernel/cpu/intel.c +2
-0@@ -503,6 +503,7 @@ static void detect_vmx_virtcap(struct cpuinfo_x86 *c)#define X86_VMX_FEATURE_PROC_CTLS2_EPT 0x00000002#define X86_VMX_FEATURE_PROC_CTLS2_VPID 0x00000020#define x86_VMX_FEATURE_EPT_CAP_AD 0x00200000 +#define X86_VMX_FEATURE_PROC_CTLS2_SPP 0x00800000u32 vmx_msr_low, vmx_msr_high, msr_ctl, msr_ctl2;u32 msr_vpid_cap, msr_ept_cap;@@ -513,6 +514,7 @@ static void detect_vmx_virtcap(struct cpuinfo_x86 *c)clear_cpu_cap (c,X86_FEATURE_EPT );clear_cpu_cap (c,X86_FEATURE_VPID );clear_cpu_cap (c,X86_FEATURE_EPT_AD ); +clear_cpu_cap (c,X86_FEATURE_SPP );rdmsr (MSR_IA32_VMX_PROCBASED_CTLS , vmx_msr_low, vmx_msr_high); msr_ctl = vmx_msr_high | vmx_msr_low;
arch/x86/kernel/cpu/intel.c static void detect_vmx_virtcap(struct cpuinfo_x86 *c) · line 542
Quoted 5 lines
arch/x86/kernel/cpu/intel.c +2
-0@@ -536,6 +538,8 @@ static void detect_vmx_virtcap(struct cpuinfo_x86 *c) }if (msr_ctl2 &X86_VMX_FEATURE_PROC_CTLS2_VPID )set_cpu_cap (c,X86_FEATURE_VPID ); +if (msr_ctl2 &X86_VMX_FEATURE_PROC_CTLS2_SPP ) +set_cpu_cap (c,X86_FEATURE_SPP );
SPP requires EPT, so this could be moved up next to the EPT_AD check. In fact, I would suggest changing 'SPP' to 'EPT_SPP' to make it clear that this feature is *EPT* sub-page permissions.
arch/x86/kvm/mmu.h line 30
Quoted 13 lines
arch/x86/kernel/cpu/intel.c +0
-0} }arch/x86/kvm/mmu.h +2
-0@@ -26,6 +26,8 @@#define PT_PAGE_SIZE_MASK (1ULL << PT_PAGE_SIZE_SHIFT)#define PT_PAT_MASK (1ULL << 7)#define PT_GLOBAL_MASK (1ULL << 8) +#define PT_SPP_SHIFT 61 +#define PT_SPP_MASK (1ULL << PT_SPP_SHIFT)
Since these constants are only applicable to EPT, would it be more appropriate to define them in paging_tmpl.h, under '#elif PTTYPE == PTTYPE_EPT'? If not, it seems that they should at least be renamed to PT64_SPP_* for consistency with the other macros here.
Quoted 58 lines
arch/x86/kvm/mmu.h +0
-0#define PT64_NX_SHIFT 63#define PT64_NX_MASK (1ULL << PT64_NX_SHIFT)arch/x86/kvm/vmx/capabilities.h +5
-0@@ -241,6 +241,11 @@ static inline bool cpu_has_vmx_pml(void)return vmcs_config.cpu_based_2nd_exec_ctrl &SECONDARY_EXEC_ENABLE_PML ; } +static inline bool cpu_has_vmx_ept_spp (void ) +{ +return vmcs_config.cpu_based_2nd_exec_ctrl &SECONDARY_EXEC_ENABLE_SPP ; +} +static inline bool vmx_xsaves_supported (void ) { return vmcs_config.cpu_based_2nd_exec_ctrl &arch/x86/kvm/vmx/vmx.c +6
-0@@ -60,6 +60,7 @@#include "vmcs12.h" #include "vmx.h" #include "x86.h" +#include "spp.h" MODULE_AUTHOR ("Qumranet" );MODULE_LICENSE ("GPL" );@@ -113,6 +114,7 @@ module_param_named(pml, enable_pml, bool, S_IRUGO);static bool __read_mostly dump_invalid_vmcs =0 ;module_param (dump_invalid_vmcs, bool,0644 ); +static bool __read_mostly spp_supported =0 ;#define MSR_BITMAP_MODE_X2APIC 1#define MSR_BITMAP_MODE_X2APIC_APICV 2@@ -2279,6 +2281,7 @@ static __init int setup_vmcs_config(struct vmcs_config *vmcs_conf,SECONDARY_EXEC_RDSEED_EXITING |SECONDARY_EXEC_RDRAND_EXITING |SECONDARY_EXEC_ENABLE_PML | +SECONDARY_EXEC_ENABLE_SPP |SECONDARY_EXEC_TSC_SCALING |SECONDARY_EXEC_PT_USE_GPA | SECONDARY_EXEC_PT_CONCEAL_VMX |@@ -3931,6 +3934,9 @@ static void vmx_compute_secondary_exec_control(struct vcpu_vmx *vmx)if (!enable_pml) exec_control &= ~SECONDARY_EXEC_ENABLE_PML ; +if (!spp_supported) + exec_control &= ~SECONDARY_EXEC_ENABLE_SPP ; +if (vmx_xsaves_supported ()) {/* Exposing XSAVES only when XSAVE is exposed */ bool xsaves_enabled =
arch/x86/kvm/vmx/vmx.c static __init int hardware_setup(void) · line 7532
Quoted 6 lines
arch/x86/kvm/vmx/vmx.c +3
-0@@ -7521,6 +7527,10 @@ static __init int hardware_setup(void)if (!cpu_has_vmx_flexpriority ()) flexpriority_enabled =0 ; +if (cpu_has_vmx_ept_spp () && enable_ept && +boot_cpu_has (X86_FEATURE_SPP )) + spp_supported =1 ;
Don't cpu_has_vmx_ept_spp() and boot_cpu_has(X86_FEATURE_SPP) test exactly the same thing?
Quoted 6 lines
arch/x86/kvm/vmx/vmx.c +0
-1if (!cpu_has_virtual_nmis ()) enable_vnmi =0 ; --2.17.2
Re: [PATCH v5 2/9] vmx: spp: Add control flags for Sub-Page Protection(SPP)
Quoted 11 lines · Jim Mattson
arch/x86/kvm/vmx/vmx.c static __init int hardware_setup(void) · line 7532
Quoted 7 lines · Yang Weijiang
arch/x86/kvm/vmx/vmx.c +3
-0@@ -7521,6 +7527,10 @@ static __init int hardware_setup(void)if (!cpu_has_vmx_flexpriority ()) flexpriority_enabled =0 ; +if (cpu_has_vmx_ept_spp () && enable_ept && +boot_cpu_has (X86_FEATURE_SPP )) + spp_supported =1 ;Don't
cpu_has_vmx_ept_spp()andboot_cpu_has(X86_FEATURE_SPP)test exactly the same thing?
More or less. I'm about to hit 'send' on a series to eliminate the synthetic VMX features flags. If that goes through, the X86_FEATURE_SPP flag can also go away.
Re: [PATCH v5 2/9] vmx: spp: Add control flags for Sub-Page Protection(SPP)
Quoted 13 lines · Sean Christopherson
Quoted 11 lines · Jim Mattson
arch/x86/kvm/vmx/vmx.c static __init int hardware_setup(void) · line 7532
Quoted 7 lines · Yang Weijiang
arch/x86/kvm/vmx/vmx.c +3
-0@@ -7521,6 +7527,10 @@ static __init int hardware_setup(void)if (!cpu_has_vmx_flexpriority ()) flexpriority_enabled =0 ; +if (cpu_has_vmx_ept_spp () && enable_ept && +boot_cpu_has (X86_FEATURE_SPP )) + spp_supported =1 ;Don't
cpu_has_vmx_ept_spp()andboot_cpu_has(X86_FEATURE_SPP)test exactly the same thing?
Quoted 3 lines
More or less. I'm about to hit 'send' on a series to eliminate the synthetic VMX features flags. If that goes through, the
X86_FEATURE_SPPflag can also go away.
Thank you, these two are synonyms. I'll remove one next time.
PATCH v5 3/9 mmu: spp: Add SPP Table setup functions
In reply to Yang WeijiangSPPT is a 4-level paging structure similar to EPT, when SPP is armed for target physical page, bit 61 of the corresponding EPT entry is flaged, then SPPT is traversed with the gfn, the leaf entry of SPPT contains the access bitmap of subpages inside the target 4KB physical page, one bit per 128-byte subpage.
--- arch/x86/include/asm/kvm_host.h | 4 +- arch/x86/kvm/vmx/spp.c | 236 ++++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/spp.h | 10 ++ 3 files changed, 249 insertions(+), 1 deletion(-) create mode 100644 arch/x86/kvm/vmx/spp.c create mode 100644 arch/x86/kvm/vmx/spp.h
arch/x86/include/asm/kvm_host.h +3 -1
@@ -270,7 +270,8 @@ union kvm_mmu_page_role { unsigned smap_andnot_wp:1; unsigned ad_disabled:1; unsigned guest_mode:1; - unsigned :6; + unsigned spp:1; + unsigned reserved:5;/* * This is left at the top of the word so that
@@ -399,6 +400,7 @@ struct kvm_mmu { u64 *spte, const void *pte);hpa_t root_hpa;gpa_t root_cr3; +hpa_t sppt_root;union kvm_mmu_role mmu_role;u8 root_level;u8 shadow_root_level;
arch/x86/kvm/vmx/spp.c new file +236 -0
236 lines not on this page · raw message
arch/x86/kvm/vmx/spp.h new file +10 -0
@@ -0,0 +1,10 @@ +/* SPDX-License-Identifier: GPL-2.0 */ +#ifndef __KVM_X86_VMX_SPP_H +#define __KVM_X86_VMX_SPP_H + +bool is_spp_spte (struct kvm_mmu_page *sp); +inline u64 construct_spptp (unsigned long root_hpa); +int kvm_spp_setup_structure (struct kvm_vcpu *vcpu, +u32 access_map,gfn_t gfn); + +#endif /* __KVM_X86_VMX_SPP_H */
Signature · 1 line
2.17.2
PATCH v5 4/9 mmu: spp: Add functions to create/destroy SPP bitmap block
In reply to Yang WeijiangCreate access bitmap for SPP subpages, the bitmap can be accessed with a gfn. The initial access bitmap for each physical page is 0xFFFFFFFF, meaning SPP is not enabled for the subpages.
--- arch/x86/include/asm/kvm_host.h | 1 + arch/x86/kvm/vmx/spp.c | 59 +++++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/spp.h | 1 + 3 files changed, 61 insertions(+)
arch/x86/include/asm/kvm_host.h +1 -0
@@ -799,6 +799,7 @@ struct kvm_lpage_info {struct kvm_arch_memory_slot {struct kvm_rmap_head *rmap[KVM_NR_PAGE_SIZES ]; +u32 *subpage_wp_info;struct kvm_lpage_info *lpage_info[KVM_NR_PAGE_SIZES -1 ];unsigned short *gfn_track[KVM_PAGE_TRACK_MAX ]; };
arch/x86/kvm/vmx/spp.c +59 -0
71 lines not on this page · raw message
arch/x86/kvm/vmx/spp.h +1 -0
@@ -2,6 +2,7 @@#ifndef __KVM_X86_VMX_SPP_H#define __KVM_X86_VMX_SPP_H +#define FULL_SPP_ACCESS ((u32)((1ULL << 32) - 1))bool is_spp_spte (struct kvm_mmu_page *sp);inline u64 construct_spptp (unsigned long root_hpa); int kvm_spp_setup_structure(struct kvm_vcpu *vcpu,
Signature · 1 line
2.17.2
PATCH v5 5/9 mmu: spp: Introduce SPP {init,set,get} functions
In reply to Yang Weijiangspp_init() must be called before any {get, set}_subpage functions, it creates subpage access bitmaps for VM memory space then sets up SPPT root pages.
kvm_spp_set_permission() is to enable SPP bit in EPT leaf page. If the gfn range covers hugepage, then it zapps the hugepage entries in EPT, this induces following memory access to cause EPT page fault. The mmu_lock must be held before above operation.
kvm_spp_get_permission() is used to query access bitmap for protected page, it's also used in EPT fault handler to check whether the fault EPT page is SPP protected as well.
--- arch/x86/include/asm/kvm_host.h | 2 + arch/x86/kvm/vmx/spp.c | 242 ++++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/spp.h | 5 + include/uapi/linux/kvm.h | 9 ++ 4 files changed, 258 insertions(+)
arch/x86/include/asm/kvm_host.h +2 -0
@@ -940,6 +940,8 @@ struct kvm_arch {bool exception_payload_enabled;struct kvm_pmu_event_filter *pmu_event_filter; +bool spp_active; + };struct kvm_vm_stat {
arch/x86/kvm/vmx/spp.c +242 -0
260 lines not on this page · raw message
arch/x86/kvm/vmx/spp.h +5 -0
@@ -3,9 +3,14 @@#define __KVM_X86_VMX_SPP_H#define FULL_SPP_ACCESS ((u32)((1ULL << 32) - 1)) +bool is_spp_spte (struct kvm_mmu_page *sp);inline u64 construct_spptp (unsigned long root_hpa);int kvm_spp_setup_structure (struct kvm_vcpu *vcpu,u32 access_map,gfn_t gfn); +int vmx_spp_flush_sppt (struct kvm *kvm,struct kvm_subpage *spp_info); +void kvm_spp_free_memslot (struct kvm_memory_slot *free, +struct kvm_memory_slot *dont); +int vmx_spp_init (struct kvm *kvm);#endif /* __KVM_X86_VMX_SPP_H */
include/uapi/linux/kvm.h +9 -0
@@ -102,6 +102,15 @@ struct kvm_userspace_memory_region {__u64 userspace_addr;/* start of the userspace allocated memory */ }; +/* for KVM_SUBPAGES_GET_ACCESS and KVM_SUBPAGES_SET_ACCESS */ +#define SUBPAGE_MAX_BITMAP 64 +struct kvm_subpage { +__u64 base_gfn; +__u64 npages; +/* sub-page write-access bitmap array */ +__u32 access_map[SUBPAGE_MAX_BITMAP ]; +}; +/* * The bit 0 ~ bit 15 of kvm_memory_region::flags are visible for userspace, * other bits are reserved for kvm internal use which are defined in
Signature · 1 line
2.17.2
PATCH v5 6/9 x86: spp: Introduce user-space SPP IOCTLs
In reply to Yang WeijiangUser application, e.g., QEMU or VMI, must initialize SPP before gets/sets SPP subpages, the dynamic initialization is to reduce the extra storage cost if the SPP feature is not not used.
--- arch/x86/include/asm/kvm_host.h | 3 ++ arch/x86/kvm/vmx/spp.c | 54 +++++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/spp.h | 5 +++ arch/x86/kvm/vmx/vmx.c | 8 +++++ arch/x86/kvm/x86.c | 49 ++++++++++++++++++++++++++++++ include/uapi/linux/kvm.h | 3 ++ 6 files changed, 122 insertions(+)
arch/x86/include/asm/kvm_host.h +3 -0
@@ -1216,6 +1216,9 @@ struct kvm_x86_ops {uint16_t (*nested_get_evmcs_version)(struct kvm_vcpu *vcpu);bool (*need_emulation_on_page_fault)(struct kvm_vcpu *vcpu); + +int (*init_spp)(struct kvm *kvm); +int (*flush_subpages)(struct kvm *kvm,struct kvm_subpage *spp_info); };struct kvm_arch_async_pf {
arch/x86/kvm/vmx/spp.c +54 -0
57 lines not on this page · raw message
arch/x86/kvm/vmx/spp.h +5 -0
@@ -6,6 +6,11 @@bool is_spp_spte (struct kvm_mmu_page *sp);inline u64 construct_spptp (unsigned long root_hpa); +int kvm_vm_ioctl_get_subpages (struct kvm *kvm, +struct kvm_subpage *spp_info); +int kvm_vm_ioctl_set_subpages (struct kvm *kvm, +struct kvm_subpage *spp_info); +int kvm_vm_ioctl_init_spp (struct kvm *kvm);int kvm_spp_setup_structure (struct kvm_vcpu *vcpu,u32 access_map,gfn_t gfn);int vmx_spp_flush_sppt (struct kvm *kvm,struct kvm_subpage *spp_info);
arch/x86/kvm/vmx/vmx.c +8 -0
@@ -7597,6 +7597,11 @@ static __init int hardware_setup(void) kvm_x86_ops->enable_log_dirty_pt_masked =NULL ; } +if (!spp_supported) { + kvm_x86_ops->flush_subpages =NULL ; + kvm_x86_ops->init_spp =NULL ; + } +if (!cpu_has_vmx_preemption_timer ()) enable_preemption_timer = false;
@@ -7809,6 +7814,9 @@ static struct kvm_x86_ops vmx_x86_ops __ro_after_init = { .nested_enable_evmcs = NULL, .nested_get_evmcs_version = NULL, .need_emulation_on_page_fault = vmx_need_emulation_on_page_fault, + + .flush_subpages = vmx_spp_flush_sppt, + .init_spp = vmx_spp_init, };static void vmx_cleanup_l1d_flush (void )
arch/x86/kvm/x86.c +49 -0
61 lines not on this page · raw message
include/uapi/linux/kvm.h +3 -0
@@ -1257,6 +1257,9 @@ struct kvm_vfio_spapr_tce { struct kvm_userspace_memory_region)#define KVM_SET_TSS_ADDR _IO(KVMIO, 0x47)#define KVM_SET_IDENTITY_MAP_ADDR _IOW(KVMIO, 0x48, __u64) +#define KVM_SUBPAGES_GET_ACCESS _IOR(KVMIO, 0x49, __u64) +#define KVM_SUBPAGES_SET_ACCESS _IOW(KVMIO, 0x4a, __u64) +#define KVM_INIT_SPP _IOW(KVMIO, 0x4b, __u64)/* enable ucontrol for s390 */ struct kvm_s390_ucas_mapping {
Signature · 1 line
2.17.2
PATCH v5 7/9 vmx: spp: Set up SPP paging table at vm-entry/exit
In reply to Yang WeijiangIf write to subpage is not allowed, EPT violation generates and it's handled in fast_page_fault().
In current implementation, SPPT setup is only handled in handle_spp() vm-exit handler, it's triggered when SPP bit is set in EPT leaf entry while SPPT entries are not ready.
A SPP specific bit(11) is added to exit_qualification and a new exit reason(66) is introduced for SPP.
--- arch/x86/include/asm/vmx.h | 9 ++++ arch/x86/include/uapi/asm/vmx.h | 2 + arch/x86/kvm/mmu.c | 42 ++++++++++++++++- arch/x86/kvm/vmx/spp.c | 12 +++++ arch/x86/kvm/vmx/spp.h | 2 + arch/x86/kvm/vmx/vmx.c | 81 +++++++++++++++++++++++++++++++++ arch/x86/kvm/x86.c | 2 + include/uapi/linux/kvm.h | 5 ++ 8 files changed, 154 insertions(+), 1 deletion(-)
arch/x86/include/asm/vmx.h +9 -0
@@ -211,6 +211,8 @@ enum vmcs_field {XSS_EXIT_BITMAP_HIGH =0x0000202D ,ENCLS_EXITING_BITMAP =0x0000202E ,ENCLS_EXITING_BITMAP_HIGH =0x0000202F , +SPPT_POINTER =0x00002030 , +SPPT_POINTER_HIGH =0x00002031 ,TSC_MULTIPLIER =0x00002032 ,TSC_MULTIPLIER_HIGH =0x00002033 , GUEST_PHYSICAL_ADDRESS = 0x00002400,
@@ -532,6 +534,13 @@ struct vmx_msr_entry {#define EPT_VIOLATION_EXECUTABLE (1 << EPT_VIOLATION_EXECUTABLE_BIT)#define EPT_VIOLATION_GVA_TRANSLATED (1 << EPT_VIOLATION_GVA_TRANSLATED_BIT) +/* +* Exit Qualifications for SPPT-Induced vmexits +*/ +#define SPPT_INDUCED_EXIT_TYPE_BIT 11 +#define SPPT_INDUCED_EXIT_TYPE (1 << SPPT_INDUCED_EXIT_TYPE_BIT) +#define SPPT_INTR_INFO_UNBLOCK_NMI INTR_INFO_UNBLOCK_NMI +/* * VM-instruction error numbers */
arch/x86/include/uapi/asm/vmx.h +2 -0
@@ -85,6 +85,7 @@#define EXIT_REASON_PML_FULL 62#define EXIT_REASON_XSAVES 63#define EXIT_REASON_XRSTORS 64 +#define EXIT_REASON_SPP 66#define VMX_EXIT_REASONS \ { EXIT_REASON_EXCEPTION_NMI, "EXCEPTION_NMI" }, \
@@ -141,6 +142,7 @@ { EXIT_REASON_ENCLS, "ENCLS" }, \ { EXIT_REASON_RDSEED, "RDSEED" }, \ { EXIT_REASON_PML_FULL, "PML_FULL" }, \ + { EXIT_REASON_SPP, "SPP" }, \ { EXIT_REASON_XSAVES, "XSAVES" }, \ { EXIT_REASON_XRSTORS, "XRSTORS" }
arch/x86/kvm/mmu.c +41 -1
99 lines not on this page · raw message
arch/x86/kvm/vmx/spp.c +12 -0
@@ -17,6 +17,18 @@ static void shadow_spp_walk_init(struct kvm_shadow_walk_iterator *iterator, iterator->level =PT64_ROOT_4LEVEL ; } +/* Restore an spp armed PTE */ +void restore_spp_bit (u64 *spte) +{ + *spte &= ~PT64_SPP_SAVED_BIT ; + *spte |=PT_SPP_MASK ; +} + +bool was_spp_armed (u64 spte) +{ +return !!(spte &PT64_SPP_SAVED_BIT ); +} +static int is_spp_shadow_present (u64 pte) {return pte &PT_PRESENT_MASK ;
arch/x86/kvm/vmx/spp.h +2 -0
@@ -5,6 +5,8 @@#define FULL_SPP_ACCESS ((u32)((1ULL << 32) - 1))bool is_spp_spte (struct kvm_mmu_page *sp); +void restore_spp_bit (u64 *spte); +bool was_spp_armed (u64 spte);inline u64 construct_spptp (unsigned long root_hpa);int kvm_vm_ioctl_get_subpages (struct kvm *kvm,struct kvm_subpage *spp_info);
arch/x86/kvm/vmx/vmx.c +81 -0
111 lines not on this page · raw message
arch/x86/kvm/x86.c +2 -0
@@ -9523,6 +9523,8 @@ void kvm_arch_free_memslot(struct kvm *kvm, struct kvm_memory_slot *free, }kvm_page_track_free_memslot (free, dont); +if (kvm->arch.spp_active) +kvm_spp_free_memslot (free, dont); } int kvm_arch_create_memslot(struct kvm *kvm, struct kvm_memory_slot *slot,
include/uapi/linux/kvm.h +5 -0
@@ -244,6 +244,7 @@ struct kvm_hyperv_exit {#define KVM_EXIT_S390_STSI 25#define KVM_EXIT_IOAPIC_EOI 26#define KVM_EXIT_HYPERV 27 +#define KVM_EXIT_SPP 28/* For KVM_EXIT_INTERNAL_ERROR */ /* Emulate instruction failed. */
@@ -399,6 +400,10 @@ struct kvm_run {struct {__u8 vector; } eoi; +/* KVM_EXIT_SPP */ +struct { +__u64 addr; + } spp;/* KVM_EXIT_HYPERV */ struct kvm_hyperv_exit hyperv;/* Fix the size of the union. */
Signature · 1 line
2.17.2
kbuild test robot
build botRe: [PATCH v5 7/9] vmx: spp: Set up SPP paging table at vm-entry/exit
Thank you for the patch! Yet something to improve:
Hi Yang,
Thank you for the patch! Yet something to improve:
[auto build test ERROR on linus/master]
[cannot apply to v5.3 next-20190916]
[if your patch is applied to the wrong git tree, please drop us a note to help improve the system]
url: https://github.com/0day-ci/linux/commits/Yang-Weijiang/Enable-Sub-page-Write-Protection-Support/20190917-165718
config: x86_64-lkp (attached as .config)
compiler: gcc-7 (Debian 7.4.0-11) 7.4.0
reproduce:
# save the attached .config to linux build tree
make ARCH=x86_64 If you fix the issue, kindly add following tag
All errors (new ones prefixed by >>):
arch/x86/kvm/vmx/vmx.c: In function 'handle_spp':
arch/x86/kvm/vmx/vmx.c:5389:9: error: implicit declaration of function 'kvm_spp_get_permission'; did you mean 'kvm_apic_set_version'? [-Werror=implicit-function-declaration]
ret = kvm_spp_get_permission(vcpu->kvm, &spp_info);
^~~~~~~~~~~~~~~~~~~~~~
kvm_apic_set_version
In file included from arch/x86/kvm/vmx/vmx.c:63:0:
arch/x86/kvm/vmx/vmx.c: In function 'vmx_set_cr3':
>> arch/x86/kvm/vmx/spp.h:10:12: error: inlining failed in call to always_inline 'construct_spptp': function body not available
inline u64 construct_spptp(unsigned long root_hpa);
^~~~~~~~~~~~~~~
arch/x86/kvm/vmx/vmx.c:2918:9: note: called from here
spptp = construct_spptp(vcpu->arch.mmu->sppt_root);
~~~~~~^~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~cc1: some warnings being treated as errors
vim +/construct_spptp +10 arch/x86/kvm/vmx/spp.h
ded814173c867b Yang Weijiang 2019-09-17 6 d8d20dcdd099e5 Yang Weijiang 2019-09-17 7 bool is_spp_spte(struct kvm_mmu_page *sp); 45c11debf177b5 Yang Weijiang 2019-09-17 8 void restore_spp_bit(u64 *spte); 45c11debf177b5 Yang Weijiang 2019-09-17 9 bool was_spp_armed(u64 spte); d8d20dcdd099e5 Yang Weijiang 2019-09-17 @10 inline u64 construct_spptp(unsigned long root_hpa); 5b98f4f41c5e1f Yang Weijiang 2019-09-17 11 int kvm_vm_ioctl_get_subpages(struct kvm *kvm, 5b98f4f41c5e1f Yang Weijiang 2019-09-17 12 struct kvm_subpage *spp_info); 5b98f4f41c5e1f Yang Weijiang 2019-09-17 13 int kvm_vm_ioctl_set_subpages(struct kvm *kvm, 5b98f4f41c5e1f Yang Weijiang 2019-09-17 14 struct kvm_subpage *spp_info); 5b98f4f41c5e1f Yang Weijiang 2019-09-17 15 int kvm_vm_ioctl_init_spp(struct kvm *kvm); d8d20dcdd099e5 Yang Weijiang 2019-09-17 16 int kvm_spp_setup_structure(struct kvm_vcpu *vcpu, d8d20dcdd099e5 Yang Weijiang 2019-09-17 17 u32 access_map, gfn_t gfn); ded814173c867b Yang Weijiang 2019-09-17 18 int vmx_spp_flush_sppt(struct kvm *kvm, struct kvm_subpage *spp_info); ded814173c867b Yang Weijiang 2019-09-17 19 void kvm_spp_free_memslot(struct kvm_memory_slot *free, ded814173c867b Yang Weijiang 2019-09-17 20 struct kvm_memory_slot *dont); ded814173c867b Yang Weijiang 2019-09-17 21 int vmx_spp_init(struct kvm *kvm);
d8d20dcdd099e5 Yang Weijiang 2019-09-17 22
:::::: The code at line 10 was first introduced by commit
:::::: d8d20dcdd099e58254195f4b083a76c3e39331de mmu: spp: Add SPP Table setup functions
:::::: TO: Yang Weijiang <[email protected]> :::::: CC: 0day robot <[email protected]>
---
0-DAY kernel test infrastructure Open Source Technology Center
https://lists.01.org/pipermail/kbuild-all Intel Corporation
PATCH v5 8/9 mmu: spp: Enable Lazy mode SPP protection
In reply to Yang WeijiangTo deal with SPP protected 4KB pages within hugepage(2MB,1GB etc), the hugepage entry is first zapped when set subpage permission, then in tdp_page_fault(), it checks whether the gfn should be mapped to PT_PAGE_TABLE_LEVEL or PT_DIRECTORY_LEVEL level depending on gfn inclusion of SPP protected page range.
--- arch/x86/kvm/mmu.c | 14 ++++++++++++ arch/x86/kvm/vmx/spp.c | 48 ++++++++++++++++++++++++++++++++++++++++++ arch/x86/kvm/vmx/spp.h | 4 ++++ 3 files changed, 66 insertions(+)
arch/x86/kvm/mmu.c +14 -0
@@ -3240,6 +3240,17 @@ static int __direct_map(struct kvm_vcpu *vcpu, gpa_t gpa, int write, map_writable);direct_pte_prefetch (vcpu, it.sptep); ++vcpu->stat.pf_fixed; +if (level ==PT_PAGE_TABLE_LEVEL ) { +struct kvm_subpage sbp = {0 }; +int pages; + + sbp.base_gfn = gfn; + sbp.npages =1 ; + pages =kvm_spp_get_permission (vcpu->kvm, &sbp); +if (pages ==1 && sbp.access_map[0 ] !=FULL_SPP_ACCESS ) +kvm_spp_mark_protection (vcpu->kvm, &sbp); + } +return ret; }
@@ -4183,6 +4194,9 @@ static int tdp_page_fault(struct kvm_vcpu *vcpu, gva_t gpa, u32 error_code,if (level >PT_DIRECTORY_LEVEL && !check_hugepage_cache_consistency (vcpu, gfn, level)) level =PT_DIRECTORY_LEVEL ; + +check_spp_protection (vcpu, gfn, &force_pt_level,&level); + gfn &= ~(KVM_PAGES_PER_HPAGE (level) -1 ); }
arch/x86/kvm/vmx/spp.c +48 -0
54 lines not on this page · raw message
arch/x86/kvm/vmx/spp.h +4 -0
@@ -4,9 +4,13 @@#define FULL_SPP_ACCESS ((u32)((1ULL << 32) - 1)) +int kvm_spp_get_permission (struct kvm *kvm,struct kvm_subpage *spp_info); +int kvm_spp_mark_protection (struct kvm *kvm,struct kvm_subpage *spp_info);bool is_spp_spte (struct kvm_mmu_page *sp);void restore_spp_bit (u64 *spte);bool was_spp_armed (u64 spte); +bool check_spp_protection (struct kvm_vcpu *vcpu,gfn_t gfn, +bool *force_pt_level,int *level);inline u64 construct_spptp (unsigned long root_hpa);int kvm_vm_ioctl_get_subpages (struct kvm *kvm,struct kvm_subpage *spp_info);
Signature · 1 line
2.17.2
PATCH v5 9/9 mmu: spp: Handle SPP protected pages when VM memory changes
In reply to Yang WeijiangHost page swapping/migration may change the translation in EPT leaf entry, if the target page is SPP protected, re-enable SPP protection in MMU notifier. If SPPT shadow page is reclaimed, the level1 pages don't have rmap to clear.
--- arch/x86/kvm/mmu.c | 22 ++++++++++++++++++++++ 1 file changed, 22 insertions(+)
arch/x86/kvm/mmu.c +22 -0
@@ -1828,6 +1828,24 @@ static int kvm_set_pte_rmapp(struct kvm *kvm, struct kvm_rmap_head *rmap_head, new_spte &= ~PT_WRITABLE_MASK ; new_spte &= ~SPTE_HOST_WRITEABLE ; +/* +* if it's EPT leaf entry and the physical page is +* SPP protected, then re-enable SPP protection for +* the page. +*/ +if (kvm->arch.spp_active && + level ==PT_PAGE_TABLE_LEVEL ) { +struct kvm_subpage spp_info = {0 }; +int i; + + spp_info.base_gfn = gfn; + spp_info.npages =1 ; + i =kvm_spp_get_permission (kvm, &spp_info); +if (i ==1 && + spp_info.access_map[0 ] !=FULL_SPP_ACCESS ) + new_spte |=PT_SPP_MASK ; + } + new_spte =mark_spte_for_access_track (new_spte);mmu_spte_clear_track_bits (sptep);
@@ -2677,6 +2695,10 @@ static bool mmu_page_zap_pte(struct kvm *kvm, struct kvm_mmu_page *sp, pte = *spte;if (is_shadow_present_pte (pte)) {if (is_last_spte (pte, sp->role.level)) { +/* SPPT leaf entries don't have rmaps*/ +if (sp->role.level ==PT_PAGE_TABLE_LEVEL && +is_spp_spte (sp)) +return true;drop_spte (kvm, spte);if (is_large_pte (pte)) --kvm->stat.lpages;
Signature · 1 line
2.17.2
Quoted 28 lines · Yang Weijiang
EPT-Based Sub-Page write Protection(SPP)is a HW capability which allows Virtual Machine Monitor(VMM) to specify write-permission for guest physical memory at a sub-page(128 byte) granularity. When this capability is enabled, the CPU enforces write-access check for sub-pages within a 4KB page.
The feature is targeted to provide fine-grained memory protection for usages such as device virtualization, memory check-point and VM introspection etc.
SPP is active when the "sub-page write protection" (bit 23) is 1 in Secondary VM-Execution Controls. The feature is backed with a Sub-Page Permission Table(SPPT), SPPT is referenced via a 64-bit control field called Sub-Page Permission Table Pointer (SPPTP) which contains a 4K-aligned physical address.
To enable SPP for certain physical page, the gfn should be first mapped to a 4KB entry, then set bit 61 of the corresponding EPT leaf entry. While HW walks EPT, if bit 61 is set, it traverses SPPT with the guset physical address to find out the sub-page permissions at the leaf entry. If the corresponding bit is set, write to sub-page is permitted, otherwise, SPP induced EPT violation is generated.
This patch serial passed SPP function test and selftest on Ice-Lake platform.
Please refer to the SPP introduction document in this patch set and Intel SDM for details:
Quoted 8 lines
Intel SDM:
https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdfSPP selftest patch:
https://lkml.org/lkml/2019/6/18/1197Previous patch:
https://lkml.org/lkml/2019/8/14/97
I saw the patches as part of the introspection patch-set. Are you all working together on this?
Would it be possible for some of the bitdefender folks who depend on this to provide Tested-by adn could they also take the time to review this patch-set?
Thanks.
Quoted 32 lines · Konrad Rzeszutek Wilk
Quoted 31 lines · Yang Weijiang
EPT-Based Sub-Page write Protection(SPP)is a HW capability which allows Virtual Machine Monitor(VMM) to specify write-permission for guest physical memory at a sub-page(128 byte) granularity. When this capability is enabled, the CPU enforces write-access check for sub-pages within a 4KB page.
The feature is targeted to provide fine-grained memory protection for usages such as device virtualization, memory check-point and VM introspection etc.
SPP is active when the "sub-page write protection" (bit 23) is 1 in Secondary VM-Execution Controls. The feature is backed with a Sub-Page Permission Table(SPPT), SPPT is referenced via a 64-bit control field called Sub-Page Permission Table Pointer (SPPTP) which contains a 4K-aligned physical address.
To enable SPP for certain physical page, the gfn should be first mapped to a 4KB entry, then set bit 61 of the corresponding EPT leaf entry. While HW walks EPT, if bit 61 is set, it traverses SPPT with the guset physical address to find out the sub-page permissions at the leaf entry. If the corresponding bit is set, write to sub-page is permitted, otherwise, SPP induced EPT violation is generated.
This patch serial passed SPP function test and selftest on Ice-Lake platform.
Please refer to the SPP introduction document in this patch set and Intel SDM for details:
Intel SDM:
https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdf
Quoted 8 lines
Quoted 5 lines
SPP selftest patch:
https://lkml.org/lkml/2019/6/18/1197Previous patch:
https://lkml.org/lkml/2019/8/14/97I saw the patches as part of the introspection patch-set. Are you all working together on this?
Weijiang helped us to start using the SPP feature with the introspection API and tested the integration when we didn't had the hardware available. I've included the SPP patches in the introspection patch series in order to "show the full picture".
Quoted 2 lines
Would it be possible for some of the bitdefender folks who depend on this to provide Tested-by adn could they also take the time to review this patch-set?
Sure. Once we rebase the introspection patches on 5.3, we'll replace the previous version this new one in our tree and test it.
On Tue, Sep 17, 2019 at 04:52:55PM +0800, Yang, Weijiang wrote:
Hi, Paolo,
Could you review this v5 patch at your convenience? Thanks a lot!
Quoted 112 lines
EPT-Based Sub-Page write Protection(SPP)is a HW capability which allows Virtual Machine Monitor(VMM) to specify write-permission for guest physical memory at a sub-page(128 byte) granularity. When this capability is enabled, the CPU enforces write-access check for sub-pages within a 4KB page.
The feature is targeted to provide fine-grained memory protection for usages such as device virtualization, memory check-point and VM introspection etc.
SPP is active when the "sub-page write protection" (bit 23) is 1 in Secondary VM-Execution Controls. The feature is backed with a Sub-Page Permission Table(SPPT), SPPT is referenced via a 64-bit control field called Sub-Page Permission Table Pointer (SPPTP) which contains a 4K-aligned physical address.
To enable SPP for certain physical page, the gfn should be first mapped to a 4KB entry, then set bit 61 of the corresponding EPT leaf entry. While HW walks EPT, if bit 61 is set, it traverses SPPT with the guset physical address to find out the sub-page permissions at the leaf entry. If the corresponding bit is set, write to sub-page is permitted, otherwise, SPP induced EPT violation is generated.
This patch serial passed SPP function test and selftest on Ice-Lake platform.
Please refer to the SPP introduction document in this patch set and Intel SDM for details:
Intel SDM:
https://software.intel.com/sites/default/files/managed/39/c5/325462-sdm-vol-1-2abcd-3abcd.pdfSPP selftest patch:
https://lkml.org/lkml/2019/6/18/1197Previous patch:
https://lkml.org/lkml/2019/8/14/97Patch 1: Introduction to SPP.
Patch 2: Add SPP related flags and control bits. Patch 3: Functions for SPPT setup.
Patch 4: Add SPP access bitmaps for memslots. Patch 5: Introduce SPP {init,set,get} functions Patch 6: Implement User space access IOCTLs. Patch 7: Set up SPP paging table at vm-entry/exit. Patch 8: Enable lazy mode SPPT setup.
Patch 9: Handle SPP protected pages when VM memory changesChange logs:
V5 -> V4:
1. Enable SPP support for Hugepage(1GB/2MB) to extend application.
2. Make SPP miss vm-exit handler as the unified place to set up SPPT.
3. If SPP protected pages are access-tracked or dirty-page-tracked, store SPP flag in reserved address bit, restore it infast_page_fault()handler.
4. Move SPP specific functions tovmx/spp.candvmx/spp.h
5. Rebased code to kernel v5.3
6. Other change suggested by KVM community.V3 -> V4:
1. Modified documentation to make it consistent with patches.
2. Allocated SPPT root page ininit_spp()instead ofvmx_set_cr3()to avoid SPPT miss error.
3. Added back co-developers and sign-offs.V2 -> V3:
1. Rebased patches to kernel 5.1 release
2. Deferred SPPT setup to EPT fault handler if the page is not available whileset_subpage()is being called.
3. Added init IOCTL to reduce extra cost if SPP is not used.
4. Refactored patch structure, cleaned up cross referenced functions.
5. Added code to deal with memory swapping/migration/shrinker cases.V2 -> V1:
1. Rebased to 4.20-rc1
2. Move VMCS change to a separated patch.
3. Code refine and Bug fixYang Weijiang (9):
Documentation: Introduce EPT based Subpage Protection
vmx: spp: Add control flags for Sub-Page Protection(SPP)
mmu: spp: Add SPP Table setup functions
mmu: spp: Add functions to create/destroy SPP bitmap block
mmu: spp: Introduce SPP {init,set,get} functions
x86: spp: Introduce user-space SPP IOCTLs
vmx: spp: Set up SPP paging table at vm-entry/exit
mmu: spp: Enable Lazy mode SPP protection
mmu: spp: Handle SPP protected pages when VM memory changesDocumentation/virtual/kvm/spp_kvm.txt | 178 +++++++ arch/x86/include/asm/cpufeatures.h | 1 + arch/x86/include/asm/kvm_host.h | 10 +- arch/x86/include/asm/vmx.h | 10 + arch/x86/include/uapi/asm/vmx.h | 2 + arch/x86/kernel/cpu/intel.c | 4 + arch/x86/kvm/mmu.c | 78 ++- arch/x86/kvm/mmu.h | 2 + arch/x86/kvm/vmx/capabilities.h | 5 + arch/x86/kvm/vmx/spp.c | 651 ++++++++++++++++++++++++++ arch/x86/kvm/vmx/spp.h | 27 ++ arch/x86/kvm/vmx/vmx.c | 99 ++++ arch/x86/kvm/x86.c | 51 ++ include/uapi/linux/kvm.h | 17 + 14 files changed, 1133 insertions(+), 2 deletions(-) create mode 100644 Documentation/virtual/kvm/spp_kvm.txt create mode 100644 arch/x86/kvm/vmx/spp.c create mode 100644 arch/x86/kvm/vmx/spp.hSignature · 1 line
2.17.2
Quoted 17 lines · Yang Weijiang
EPT-Based Sub-Page write Protection(SPP)is a HW capability which allows Virtual Machine Monitor(VMM) to specify write-permission for guest physical memory at a sub-page(128 byte) granularity. When this capability is enabled, the CPU enforces write-access check for sub-pages within a 4KB page.
The feature is targeted to provide fine-grained memory protection for usages such as device virtualization, memory check-point and VM introspection etc.
SPP is active when the "sub-page write protection" (bit 23) is 1 in Secondary VM-Execution Controls. The feature is backed with a Sub-Page Permission Table(SPPT), SPPT is referenced via a 64-bit control field called Sub-Page Permission Table Pointer (SPPTP) which contains a 4K-aligned physical address.
Quoted 6 lines
To enable SPP for certain physical page, the gfn should be first mapped to a 4KB entry, then set bit 61 of the corresponding EPT leaf entry. While HW walks EPT, if bit 61 is set, it traverses SPPT with the guset physical address to find out the sub-page permissions at the leaf entry. If the corresponding bit is set, write to sub-page is permitted, otherwise, SPP induced EPT violation is generated.
How do you handle sub-page permissions for instructions emulated by kvm?
Quoted 18 lines · Jim Mattson
Quoted 17 lines · Yang Weijiang
EPT-Based Sub-Page write Protection(SPP)is a HW capability which allows Virtual Machine Monitor(VMM) to specify write-permission for guest physical memory at a sub-page(128 byte) granularity. When this capability is enabled, the CPU enforces write-access check for sub-pages within a 4KB page.
The feature is targeted to provide fine-grained memory protection for usages such as device virtualization, memory check-point and VM introspection etc.
SPP is active when the "sub-page write protection" (bit 23) is 1 in Secondary VM-Execution Controls. The feature is backed with a Sub-Page Permission Table(SPPT), SPPT is referenced via a 64-bit control field called Sub-Page Permission Table Pointer (SPPTP) which contains a 4K-aligned physical address.
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To enable SPP for certain physical page, the gfn should be first mapped to a 4KB entry, then set bit 61 of the corresponding EPT leaf entry. While HW walks EPT, if bit 61 is set, it traverses SPPT with the guset physical address to find out the sub-page permissions at the leaf entry. If the corresponding bit is set, write to sub-page is permitted, otherwise, SPP induced EPT violation is generated.
How do you handle sub-page permissions for instructions emulated by kvm?
How about checking if the gpa is SPP protected, if it is, inject some exception to guest?
Quoted 27 lines · Yang Weijiang
Quoted 25 lines · Jim Mattson
Quoted 23 lines · Yang Weijiang
EPT-Based Sub-Page write Protection(SPP)is a HW capability which allows Virtual Machine Monitor(VMM) to specify write-permission for guest physical memory at a sub-page(128 byte) granularity. When this capability is enabled, the CPU enforces write-access check for sub-pages within a 4KB page.
The feature is targeted to provide fine-grained memory protection for usages such as device virtualization, memory check-point and VM introspection etc.
SPP is active when the "sub-page write protection" (bit 23) is 1 in Secondary VM-Execution Controls. The feature is backed with a Sub-Page Permission Table(SPPT), SPPT is referenced via a 64-bit control field called Sub-Page Permission Table Pointer (SPPTP) which contains a 4K-aligned physical address.
To enable SPP for certain physical page, the gfn should be first mapped to a 4KB entry, then set bit 61 of the corresponding EPT leaf entry. While HW walks EPT, if bit 61 is set, it traverses SPPT with the guset physical address to find out the sub-page permissions at the leaf entry. If the corresponding bit is set, write to sub-page is permitted, otherwise, SPP induced EPT violation is generated.
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How do you handle sub-page permissions for instructions emulated by kvm?
How about checking if the gpa is SPP protected, if it is, inject some exception to guest?
The SPP semantics are well-defined. If a kvm-emulated instruction tries to write to a sub-page that is write-protected, then an SPP-induced EPT violation should be synthesized.
Quoted 28 lines · Jim Mattson
Quoted 27 lines · Yang Weijiang
Quoted 25 lines · Jim Mattson
Quoted 23 lines · Yang Weijiang
EPT-Based Sub-Page write Protection(SPP)is a HW capability which allows Virtual Machine Monitor(VMM) to specify write-permission for guest physical memory at a sub-page(128 byte) granularity. When this capability is enabled, the CPU enforces write-access check for sub-pages within a 4KB page.
The feature is targeted to provide fine-grained memory protection for usages such as device virtualization, memory check-point and VM introspection etc.
SPP is active when the "sub-page write protection" (bit 23) is 1 in Secondary VM-Execution Controls. The feature is backed with a Sub-Page Permission Table(SPPT), SPPT is referenced via a 64-bit control field called Sub-Page Permission Table Pointer (SPPTP) which contains a 4K-aligned physical address.
To enable SPP for certain physical page, the gfn should be first mapped to a 4KB entry, then set bit 61 of the corresponding EPT leaf entry. While HW walks EPT, if bit 61 is set, it traverses SPPT with the guset physical address to find out the sub-page permissions at the leaf entry. If the corresponding bit is set, write to sub-page is permitted, otherwise, SPP induced EPT violation is generated.
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How do you handle sub-page permissions for instructions emulated by kvm?
How about checking if the gpa is SPP protected, if it is, inject some exception to guest?
The SPP semantics are well-defined. If a kvm-emulated instruction tries to write to a sub-page that is write-protected, then an SPP-induced EPT violation should be synthesized.
Hi, Jim,
Regarding the emulated instructions in KVM, there're quite a few instructions can write guest memory, such as MOVS, XCHG, INS etc., check each destination against SPP protected area would be trivial if deals with them individually, and PIO/MMIO induced vmexit/page_fault also can link to a SPP protected page, e.g., a string instruction's the destination is SPP protected memory. Is there a good way to intercept these writes? emulate_ops.write_emulated() is called in most of the emulation cases to check and write guest memory, but not sure it's suitable.
Do you have any suggestion?
Thanks!