clk: qcom: gcc: Add missing clocks in SM8150
Subsystems (3)
PATCH 1/1 clk: qcom: gcc: Add missing clocks in SM8150
The initial upstreaming of SM8150 GCC driver missed few clock so add them up now.
Signed-off-by Vinod Koul <[email protected]>
--- drivers/clk/qcom/gcc-sm8150.c | 172 ++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+)
drivers/clk/qcom/gcc-sm8150.c +172 -0
@@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { }, }; +static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x52004 , + .enable_mask =BIT (15 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_gpu_gpll0_clk_src" , + .parent_hws = (const struct clk_hw *[]){ + &gpll0.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x52004 , + .enable_mask =BIT (16 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_gpu_gpll0_div_clk_src" , + .parent_hws = (const struct clk_hw *[]){ + &gcc_gpu_gpll0_clk_src.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_gpu_iref_clk = { .halt_reg =0x8c010 , .halt_check =BRANCH_HALT ,
@@ -1698,6 +1730,38 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = { }, }; +static struct clk_branch gcc_npu_gpll0_clk_src = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x52004 , + .enable_mask =BIT (18 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_npu_gpll0_clk_src" , + .parent_hws = (const struct clk_hw *[]){ + &gpll0.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_div_clk_src = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x52004 , + .enable_mask =BIT (19 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_npu_gpll0_div_clk_src" , + .parent_hws = (const struct clk_hw *[]){ + &gcc_npu_gpll0_clk_src.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_npu_trig_clk = { .halt_reg =0x4d00c , .halt_check =BRANCH_VOTED ,
@@ -2812,6 +2876,42 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { }, }; +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x7501c , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_ufs_card_rx_symbol_0_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x750ac , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_ufs_card_rx_symbol_1_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x75018 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_ufs_card_tx_symbol_0_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_ufs_card_unipro_core_clk = { .halt_reg =0x75058 , .halt_check =BRANCH_HALT ,
@@ -2992,6 +3092,42 @@ static struct clk_branch gcc_ufs_phy_phy_aux_hw_ctl_clk = { }, }; +static struct clk_branch gcc_ufs_phy_rx_symbol_0_clk = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x7701c , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_ufs_phy_rx_symbol_0_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_rx_symbol_1_clk = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x770ac , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_ufs_phy_rx_symbol_1_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_phy_tx_symbol_0_clk = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x77018 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_ufs_phy_tx_symbol_0_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_ufs_phy_unipro_core_clk = { .halt_reg =0x77058 , .halt_check =BRANCH_HALT ,
@@ -3171,6 +3307,18 @@ static struct clk_branch gcc_usb3_prim_phy_com_aux_clk = { }, }; +static struct clk_branch gcc_usb3_prim_phy_pipe_clk = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0xf058 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_usb3_prim_phy_pipe_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_usb3_sec_clkref_clk = { .halt_reg =0x8c028 , .halt_check =BRANCH_HALT ,
@@ -3201,6 +3349,18 @@ static struct clk_branch gcc_usb3_sec_phy_aux_clk = { }, }; +static struct clk_branch gcc_usb3_sec_phy_pipe_clk = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x10058 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_usb3_sec_phy_pipe_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_usb3_sec_phy_com_aux_clk = { .halt_reg =0x10054 , .halt_check =BRANCH_HALT ,
@@ -3332,12 +3492,16 @@ static struct clk_regmap *gcc_sm8150_clocks[] = { [GCC_GP3_CLK] = &gcc_gp3_clk.clkr, [GCC_GP3_CLK_SRC] = &gcc_gp3_clk_src.clkr, [GCC_GPU_CFG_AHB_CLK] = &gcc_gpu_cfg_ahb_clk.clkr, + [GCC_GPU_GPLL0_CLK_SRC] = &gcc_gpu_gpll0_clk_src.clkr, + [GCC_GPU_GPLL0_DIV_CLK_SRC] = &gcc_gpu_gpll0_div_clk_src.clkr, [GCC_GPU_IREF_CLK] = &gcc_gpu_iref_clk.clkr, [GCC_GPU_MEMNOC_GFX_CLK] = &gcc_gpu_memnoc_gfx_clk.clkr, [GCC_GPU_SNOC_DVM_GFX_CLK] = &gcc_gpu_snoc_dvm_gfx_clk.clkr, [GCC_NPU_AT_CLK] = &gcc_npu_at_clk.clkr, [GCC_NPU_AXI_CLK] = &gcc_npu_axi_clk.clkr, [GCC_NPU_CFG_AHB_CLK] = &gcc_npu_cfg_ahb_clk.clkr, + [GCC_NPU_GPLL0_CLK_SRC] = &gcc_npu_gpll0_clk_src.clkr, + [GCC_NPU_GPLL0_DIV_CLK_SRC] = &gcc_npu_gpll0_div_clk_src.clkr, [GCC_NPU_TRIG_CLK] = &gcc_npu_trig_clk.clkr, [GCC_PCIE0_PHY_REFGEN_CLK] = &gcc_pcie0_phy_refgen_clk.clkr, [GCC_PCIE1_PHY_REFGEN_CLK] = &gcc_pcie1_phy_refgen_clk.clkr,
@@ -3442,6 +3606,9 @@ static struct clk_regmap *gcc_sm8150_clocks[] = { [GCC_UFS_CARD_PHY_AUX_CLK_SRC] = &gcc_ufs_card_phy_aux_clk_src.clkr, [GCC_UFS_CARD_PHY_AUX_HW_CTL_CLK ] = &gcc_ufs_card_phy_aux_hw_ctl_clk.clkr, + [GCC_UFS_CARD_RX_SYMBOL_0_CLK] = &gcc_ufs_card_rx_symbol_0_clk.clkr, + [GCC_UFS_CARD_RX_SYMBOL_1_CLK] = &gcc_ufs_card_rx_symbol_1_clk.clkr, + [GCC_UFS_CARD_TX_SYMBOL_0_CLK] = &gcc_ufs_card_tx_symbol_0_clk.clkr, [GCC_UFS_CARD_UNIPRO_CORE_CLK] = &gcc_ufs_card_unipro_core_clk.clkr, [GCC_UFS_CARD_UNIPRO_CORE_CLK_SRC ] = &gcc_ufs_card_unipro_core_clk_src.clkr,
@@ -3459,6 +3626,9 @@ static struct clk_regmap *gcc_sm8150_clocks[] = { [GCC_UFS_PHY_PHY_AUX_CLK] = &gcc_ufs_phy_phy_aux_clk.clkr, [GCC_UFS_PHY_PHY_AUX_CLK_SRC] = &gcc_ufs_phy_phy_aux_clk_src.clkr, [GCC_UFS_PHY_PHY_AUX_HW_CTL_CLK] = &gcc_ufs_phy_phy_aux_hw_ctl_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_0_CLK] = &gcc_ufs_phy_rx_symbol_0_clk.clkr, + [GCC_UFS_PHY_RX_SYMBOL_1_CLK] = &gcc_ufs_phy_rx_symbol_1_clk.clkr, + [GCC_UFS_PHY_TX_SYMBOL_0_CLK] = &gcc_ufs_phy_tx_symbol_0_clk.clkr, [GCC_UFS_PHY_UNIPRO_CORE_CLK] = &gcc_ufs_phy_unipro_core_clk.clkr, [GCC_UFS_PHY_UNIPRO_CORE_CLK_SRC ] = &gcc_ufs_phy_unipro_core_clk_src.clkr,
@@ -3480,10 +3650,12 @@ static struct clk_regmap *gcc_sm8150_clocks[] = { [GCC_USB3_PRIM_PHY_AUX_CLK] = &gcc_usb3_prim_phy_aux_clk.clkr, [GCC_USB3_PRIM_PHY_AUX_CLK_SRC] = &gcc_usb3_prim_phy_aux_clk_src.clkr, [GCC_USB3_PRIM_PHY_COM_AUX_CLK] = &gcc_usb3_prim_phy_com_aux_clk.clkr, + [GCC_USB3_PRIM_PHY_PIPE_CLK] = &gcc_usb3_prim_phy_pipe_clk.clkr, [GCC_USB3_SEC_CLKREF_CLK] = &gcc_usb3_sec_clkref_clk.clkr, [GCC_USB3_SEC_PHY_AUX_CLK] = &gcc_usb3_sec_phy_aux_clk.clkr, [GCC_USB3_SEC_PHY_AUX_CLK_SRC] = &gcc_usb3_sec_phy_aux_clk_src.clkr, [GCC_USB3_SEC_PHY_COM_AUX_CLK] = &gcc_usb3_sec_phy_com_aux_clk.clkr, + [GCC_USB3_SEC_PHY_PIPE_CLK] = &gcc_usb3_sec_phy_pipe_clk.clkr, [GCC_VIDEO_AHB_CLK] = &gcc_video_ahb_clk.clkr, [GCC_VIDEO_AXI0_CLK] = &gcc_video_axi0_clk.clkr, [GCC_VIDEO_AXI1_CLK] = &gcc_video_axi1_clk.clkr,
Signature · 1 line
2.20.1
Stephen Boyd
maintainerQuoting Vinod Koul (2019-09-17 02:16:23)
Quoted 5 lines
The initial upstreaming of SM8150 GCC driver missed few clock so add them up now.
Signed-off-by Vinod Koul <[email protected]>---
Should have some sort of fixes tag?
drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1620
Quoted 13 lines
drivers/clk/qcom/gcc-sm8150.c | 172 ++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+)drivers/clk/qcom/gcc-sm8150.c +2
-0@@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { }, }; +static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,
Why skip?
Quoted 6 lines
drivers/clk/qcom/gcc-sm8150.c +6
-0+ .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw *[]){
drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1636
Quoted 10 lines
drivers/clk/qcom/gcc-sm8150.c +10
-0+ &gpll0.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,
Why skip?
Quoted 57 lines
drivers/clk/qcom/gcc-sm8150.c +46
-0+ .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(16), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_gpu_gpll0_div_clk_src" , + .parent_hws = (const struct clk_hw *[]){ + &gcc_gpu_gpll0_clk_src.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_gpu_iref_clk = { .halt_reg =0x8c010 , .halt_check =BRANCH_HALT ,@@ -1698,6 +1730,38 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = { }, }; +static struct clk_branch gcc_npu_gpll0_clk_src = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x52004 , + .enable_mask =BIT (18 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_npu_gpll0_clk_src" , + .parent_hws = (const struct clk_hw *[]){ + &gpll0.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_div_clk_src = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x52004 , + .enable_mask =BIT (19 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_npu_gpll0_div_clk_src" , + .parent_hws = (const struct clk_hw *[]){ + &gcc_npu_gpll0_clk_src.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_npu_trig_clk = { .halt_reg =0x4d00c , .halt_check =BRANCH_VOTED ,
drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { · line 2880
Quoted 5 lines
drivers/clk/qcom/gcc-sm8150.c +2
-0@@ -2812,6 +2876,42 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { }, }; +static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { + .halt_check =BRANCH_HALT_SKIP ,
Can't we fix the UFS driver to not require this anymore? This is the fourth or fifth time I've asked for this.
Quoted 37 lines
drivers/clk/qcom/gcc-sm8150.c +34
-0+ .clkr = { + .enable_reg = 0x7501c, + .enable_mask = BIT(0), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_ufs_card_rx_symbol_0_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_rx_symbol_1_clk = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x750ac , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_ufs_card_rx_symbol_1_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_ufs_card_tx_symbol_0_clk = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x75018 , + .enable_mask =BIT (0 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_ufs_card_tx_symbol_0_clk" , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_ufs_card_unipro_core_clk = { .halt_reg =0x75058 , .halt_check =BRANCH_HALT ,
Hi Steve,
Looks like I missed replying to this one, apologies!
Quoted 8 lines · Stephen Boyd
Quoting Vinod Koul (2019-09-17 02:16:23)
Quoted 5 lines
The initial upstreaming of SM8150 GCC driver missed few clock so add them up now.
Signed-off-by Vinod Koul <[email protected]>---
Should have some sort of fixes tag?
Not really, the drivers to use these clks are not upstream so we dont miss it yet
Quoted 12 lines
Quoted 12 lines
drivers/clk/qcom/gcc-sm8150.c | 172 ++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+)drivers/clk/qcom/gcc-sm8150.c +0
-0@@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { }, };
Quoted 4 lines
drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1620
Quoted 2 lines
drivers/clk/qcom/gcc-sm8150.c +2
-0+static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,Why skip?
I will explore and add comments for that
Quoted 79 lines
Quoted 6 lines
drivers/clk/qcom/gcc-sm8150.c +6
-0+ .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw *[]){drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1636
Quoted 10 lines
drivers/clk/qcom/gcc-sm8150.c +10
-0+ &gpll0.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,Why skip?
Quoted 60 lines
drivers/clk/qcom/gcc-sm8150.c +46
-0+ .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(16), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_gpu_gpll0_div_clk_src" , + .parent_hws = (const struct clk_hw *[]){ + &gcc_gpu_gpll0_clk_src.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_gpu_iref_clk = { .halt_reg =0x8c010 , .halt_check =BRANCH_HALT ,@@ -1698,6 +1730,38 @@ static struct clk_branch gcc_npu_cfg_ahb_clk = { }, }; +static struct clk_branch gcc_npu_gpll0_clk_src = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x52004 , + .enable_mask =BIT (18 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_npu_gpll0_clk_src" , + .parent_hws = (const struct clk_hw *[]){ + &gpll0.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_npu_gpll0_div_clk_src = { + .halt_check =BRANCH_HALT_SKIP , + .clkr = { + .enable_reg =0x52004 , + .enable_mask =BIT (19 ), + .hw.init = &(struct clk_init_data ){ + .name ="gcc_npu_gpll0_div_clk_src" , + .parent_hws = (const struct clk_hw *[]){ + &gcc_npu_gpll0_clk_src.clkr.hw }, + .num_parents =1 , + .flags =CLK_SET_RATE_PARENT , + .ops = &clk_branch2_ops, + }, + }, +}; +static struct clk_branch gcc_npu_trig_clk = { .halt_reg =0x4d00c , .halt_check =BRANCH_VOTED ,@@ -2812,6 +2876,42 @@ static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { }, };
Quoted 5 lines
drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_ufs_card_phy_aux_hw_ctl_clk = { · line 2880
Quoted 2 lines
drivers/clk/qcom/gcc-sm8150.c +2
-0+static struct clk_branch gcc_ufs_card_rx_symbol_0_clk = { + .halt_check =BRANCH_HALT_SKIP ,Can't we fix the UFS driver to not require this anymore? This is the fourth or fifth time I've asked for this.
yeah Bjorn did tell me that and I think there was some other thread on similar lines. So is this fine by you.
Signature · 1 line
~Vinod
Stephen Boyd
maintainerQuoting Vinod Koul (2019-10-16 05:23:43)
Quoted 9 lines
Hi Steve,
Looks like I missed replying to this one, apologies!
Quoted 4 lines · Stephen Boyd
Quoting Vinod Koul (2019-09-17 02:16:23)
Quoted 3 lines
The initial upstreaming of SM8150 GCC driver missed few clock so add them up now.
Quoted 7 lines
Quoted 4 lines
Quoted 2 lines
Signed-off-by Vinod Koul <[email protected]>---
Should have some sort of fixes tag?
Not really, the drivers to use these clks are not upstream so we dont miss it yet
Ok.
Quoted 13 lines
Quoted 13 lines
Quoted 13 lines
drivers/clk/qcom/gcc-sm8150.c | 172 ++++++++++++++++++++++++++++++++++ 1 file changed, 172 insertions(+)drivers/clk/qcom/gcc-sm8150.c +0
-0@@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { }, };
Quoted 26 lines
Quoted 4 lines
drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1620
Quoted 2 lines
drivers/clk/qcom/gcc-sm8150.c +2
-0+static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,Why skip?
I will explore and add comments for that
Quoted 19 lines
Quoted 6 lines
drivers/clk/qcom/gcc-sm8150.c +6
-0+ .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw *[]){drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1636
Quoted 10 lines
drivers/clk/qcom/gcc-sm8150.c +10
-0+ &gpll0.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,Why skip?
Any answer from the explorations?
Quoted 35 lines · Stephen Boyd
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
drivers/clk/qcom/gcc-sm8150.c +0
-0@@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { }, };Quoted 26 lines
Quoted 4 lines
drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1620
Quoted 2 lines
drivers/clk/qcom/gcc-sm8150.c +2
-0+static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,Why skip?
I will explore and add comments for that
Quoted 19 lines
Quoted 6 lines
drivers/clk/qcom/gcc-sm8150.c +6
-0+ .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw *[]){drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1636
Quoted 10 lines
drivers/clk/qcom/gcc-sm8150.c +10
-0+ &gpll0.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,Why skip?
Quoted 1 line
Any answer from the explorations?
Yeah so asking around the answer I got is that these are external clocks and we need cannot rely on CLK_OFF bit for these clocks
Thanks
Signature · 1 line
~Vinod
Stephen Boyd
maintainerQuoting Vinod Koul (2019-10-21 03:54:35)
Quoted 36 lines · Stephen Boyd
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drivers/clk/qcom/gcc-sm8150.c +0
-0@@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { }, };Quoted 4 lines
drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1620
Quoted 2 lines
drivers/clk/qcom/gcc-sm8150.c +2
-0+static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,Why skip?
I will explore and add comments for that
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drivers/clk/qcom/gcc-sm8150.c +6
-0+ .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw *[]){drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1636
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drivers/clk/qcom/gcc-sm8150.c +10
-0+ &gpll0.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,Why skip?
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Any answer from the explorations?
Yeah so asking around the answer I got is that these are external clocks and we need cannot rely on
CLK_OFFbit for these clocks
The parents are from some other clk controller? Not external to the chip, right? If so, I still don't get it. Please add some sort of comment here in the code.
Quoted 39 lines · Stephen Boyd
Quoting Vinod Koul (2019-10-21 03:54:35)
Quoted 38 lines · Stephen Boyd
Quoted 36 lines
Quoted 8 lines
Quoted 8 lines
Quoted 8 lines
drivers/clk/qcom/gcc-sm8150.c +0
-0@@ -1616,6 +1616,38 @@ static struct clk_branch gcc_gpu_cfg_ahb_clk = { }, };Quoted 26 lines
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drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1620
Quoted 2 lines
drivers/clk/qcom/gcc-sm8150.c +2
-0+static struct clk_branch gcc_gpu_gpll0_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,Why skip?
I will explore and add comments for that
Quoted 19 lines
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drivers/clk/qcom/gcc-sm8150.c +6
-0+ .clkr = { + .enable_reg = 0x52004, + .enable_mask = BIT(15), + .hw.init = &(struct clk_init_data){ + .name = "gcc_gpu_gpll0_clk_src", + .parent_hws = (const struct clk_hw *[]){drivers/clk/qcom/gcc-sm8150.c static struct clk_branch gcc_gpu_cfg_ahb_clk = { · line 1636
Quoted 10 lines
drivers/clk/qcom/gcc-sm8150.c +10
-0+ &gpll0.clkr.hw }, + .num_parents = 1, + .flags = CLK_SET_RATE_PARENT, + .ops = &clk_branch2_ops, + }, + }, +}; + +static struct clk_branch gcc_gpu_gpll0_div_clk_src = { + .halt_check =BRANCH_HALT_SKIP ,Why skip?
Any answer from the explorations?
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Yeah so asking around the answer I got is that these are external clocks and we need cannot rely on
CLK_OFFbit for these clocksThe parents are from some other clk controller? Not external to the chip, right? If so, I still don't get it. Please add some sort of comment here in the code.
Yeah I have added a comment and posted v2 few days back.
Thanks
Signature · 1 line
~Vinod