dt-bindings: riscv: Fix CPU schema errors
Subsystems (2)
Rob Herring
maintainerPATCH v2 1/1 dt-bindings: riscv: Fix CPU schema errors
Fix the errors in the RiscV CPU DT schema:
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required property Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5'] Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too short Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required property
---
v2:
- Add timebase-frequency to simulator example.
.../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-)
Documentation/devicetree/bindings/riscv/cpus.yaml +14 -12
@@ -24,15 +24,17 @@ description: | properties: compatible: - items: - - enum: - - sifive,rocket0 - - sifive,e5 - - sifive,e51 - - sifive,u54-mc - - sifive,u54 - - sifive,u5 - - const: riscv + oneOf: + - items: + - enum: + - sifive,rocket0 + - sifive,e5 + - sifive,e51 + - sifive,u54-mc + - sifive,u54 + - sifive,u5 + - const: riscv + - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set and identifies the type of the hart.
@@ -67,8 +69,6 @@ properties: lowercase to simplify parsing. timebase-frequency: - type: integer - minimum: 1 description: Specifies the clock frequency of the system timer in Hz. This value is common to all harts on a single system image.
@@ -102,9 +102,9 @@ examples: cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <1000000>; cpu@0 { clock-frequency = <0>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>;
@@ -120,6 +120,7 @@ examples: }; cpu@1 { clock-frequency = <0>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>;
@@ -153,6 +154,7 @@ examples: device_type = "cpu"; reg = <0>; compatible = "riscv"; + timebase-frequency = <1000000>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; interrupt-controller {
Signature · 1 line
2.20.1
Quoted 81 lines · On Wed, 25 Sep 2019 06:12:52 PDT (-0700), [email protected] wrote:
Fix the errors in the RiscV CPU DT schema:
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required propertyDocumentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required propertyDocumentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too shortDocumentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required propertyFixes 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")Cc Paul Walmsley <[email protected]>Cc Palmer Dabbelt <[email protected]>Cc Albert Ou <[email protected]>Signed-off-by Rob Herring <[email protected]>---
v2:
- Add timebase-frequency to simulator example..../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-)Documentation/devicetree/bindings/riscv/cpus.yaml +13
-12@@ -24,15 +24,17 @@ description: | properties: compatible: - items: - - enum: - - sifive,rocket0 - - sifive,e5 - - sifive,e51 - - sifive,u54-mc - - sifive,u54 - - sifive,u5 - - const: riscv + oneOf: + - items: + - enum: + - sifive,rocket0 + - sifive,e5 + - sifive,e51 + - sifive,u54-mc + - sifive,u54 + - sifive,u5 + - const: riscv + - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set and identifies the type of the hart.@@ -67,8 +69,6 @@ properties: lowercase to simplify parsing. timebase-frequency: - type: integer - minimum: 1 description: Specifies the clock frequency of the system timer in Hz. This value is common to all harts on a single system image.@@ -102,9 +102,9 @@ examples: cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <1000000>; cpu@0 { clock-frequency = <0>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>;@@ -120,6 +120,7 @@ examples: }; cpu@1 { clock-frequency = <0>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>;
Documentation/devicetree/bindings/riscv/cpus.yaml examples: · line 160
Quoted 7 lines
Documentation/devicetree/bindings/riscv/cpus.yaml +1
-0@@ -153,6 +154,7 @@ examples: device_type = "cpu"; reg = <0>; compatible = "riscv"; + timebase-frequency = <1000000>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; interrupt-controller {
Looking at this spec
section 3.7 says
Properties that have identical values across cpu nodes may be placed in the /cpus node instead. A client program must
first examine a specific cpu node, but if an expected property is not found then it should look at the parent /cpus node.
This results in a less verbose representation of properties which are identical across all CPUs.
I can never figure out if I'm looking at the right DT specifications so it's possible that is defunct, I just bring this up because we've got an outstanding bug in our port where we're not respecting what section 3.7 says and are only looking at /cpus/timebase-frequency instead of /cpus/cpu@*/timebase-frequency, and I'm wondering if the fix should allow for looking at /cpus/timebase-frequency or just not bother.
Rob Herring
maintainerQuoted 95 lines · Palmer Dabbelt
Quoted 81 lines · On Wed, 25 Sep 2019 06:12:52 PDT (-0700), [email protected] wrote:
Fix the errors in the RiscV CPU DT schema:
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required propertyDocumentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required propertyDocumentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too shortDocumentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required propertyFixes 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")Cc Paul Walmsley <[email protected]>Cc Palmer Dabbelt <[email protected]>Cc Albert Ou <[email protected]>Signed-off-by Rob Herring <[email protected]>---
v2:
- Add timebase-frequency to simulator example..../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-)Documentation/devicetree/bindings/riscv/cpus.yaml +13
-12@@ -24,15 +24,17 @@ description: | properties: compatible: - items: - - enum: - - sifive,rocket0 - - sifive,e5 - - sifive,e51 - - sifive,u54-mc - - sifive,u54 - - sifive,u5 - - const: riscv + oneOf: + - items: + - enum: + - sifive,rocket0 + - sifive,e5 + - sifive,e51 + - sifive,u54-mc + - sifive,u54 + - sifive,u5 + - const: riscv + - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set and identifies the type of the hart.@@ -67,8 +69,6 @@ properties: lowercase to simplify parsing. timebase-frequency: - type: integer - minimum: 1 description: Specifies the clock frequency of the system timer in Hz. This value is common to all harts on a single system image.@@ -102,9 +102,9 @@ examples: cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <1000000>; cpu@0 { clock-frequency = <0>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>;@@ -120,6 +120,7 @@ examples: }; cpu@1 { clock-frequency = <0>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>;Documentation/devicetree/bindings/riscv/cpus.yaml examples: · line 160
Quoted 7 lines
Documentation/devicetree/bindings/riscv/cpus.yaml +1
-0@@ -153,6 +154,7 @@ examples: device_type = "cpu"; reg = <0>; compatible = "riscv"; + timebase-frequency = <1000000>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; interrupt-controller {Looking at this spec
Quoted 8 lines
section 3.7 says
Properties that have identical values across cpu nodes may be placed in the /cpus node instead. A client program must
first examine a specific cpu node, but if an expected property is not found then it should look at the parent /cpus node.
This results in a less verbose representation of properties which are identical across all CPUs.
The cpu sections of the spec are certainly not perfect. They are largely from PPC with only the most obviously things wrong fixed...
Quoted 2 lines
I can never figure out if I'm looking at the right DT specifications so it's possible that is defunct,
Why? What's not clear which one to look at? If you start at devicetree.org the above is where you end up.
Quoted 5 lines
I just bring this up because we've got an outstanding
bug in our port where we're not respecting what section 3.7 says and are only looking at /cpus/timebase-frequency instead of /cpus/cpu@*/timebase-frequency, and I'm wondering if the fix should allow for looking at /cpus/timebase-frequency or just not bother.
It's perfectly fine for some deviation for each arch or being more restrictive. For Arm, we've generally gone the direction of everything goes into the cpu nodes. So tell me what you want, I just need the warnings gone.
Rob
Quoted 47 lines · Rob Herring
Quoted 46 lines · Palmer Dabbelt
Quoted 44 lines · On Wed, 25 Sep 2019 06:12:52 PDT (-0700), [email protected] wrote:
Fix the errors in the RiscV CPU DT schema:
Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required propertyDocumentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@1: 'timebase-frequency' is a required propertyDocumentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible:0: 'riscv' is not one of ['sifive,rocket0', 'sifive,e5', 'sifive,e51', 'sifive,u54-mc', 'sifive,u54', 'sifive,u5']Documentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: compatible: ['riscv'] is too shortDocumentation/devicetree/bindings/riscv/cpus.example.dt.yaml: cpu@0: 'timebase-frequency' is a required propertyFixes 4fd669a8c487 ("dt-bindings: riscv: convert cpu binding to json-schema")Cc Paul Walmsley <[email protected]>Cc Palmer Dabbelt <[email protected]>Cc Albert Ou <[email protected]>Signed-off-by Rob Herring <[email protected]>---
v2:
- Add timebase-frequency to simulator example..../devicetree/bindings/riscv/cpus.yaml | 26 ++++++++++--------- 1 file changed, 14 insertions(+), 12 deletions(-)Documentation/devicetree/bindings/riscv/cpus.yaml +6
-9@@ -24,15 +24,17 @@ description: | properties: compatible: - items: - - enum: - - sifive,rocket0 - - sifive,e5 - - sifive,e51 - - sifive,u54-mc - - sifive,u54 - - sifive,u5 - - const: riscv + oneOf: + - items: + - enum: + - sifive,rocket0 + - sifive,e5 + - sifive,e51
Quoted 8 lines
Quoted 8 lines
Documentation/devicetree/bindings/riscv/cpus.yaml description: | · line 40
Quoted 8 lines
Documentation/devicetree/bindings/riscv/cpus.yaml +5
-0+ - sifive,u54-mc + - sifive,u54 + - sifive,u5 + - const: riscv + - const: riscv # Simulator only description: Identifies that the hart uses the RISC-V instruction set and identifies the type of the hart.
The above part of this patch looks fine to me, and please consider that portion of this patch acked.
Quoted 52 lines
Quoted 41 lines
Quoted 29 lines
Documentation/devicetree/bindings/riscv/cpus.yaml +2
-3@@ -67,8 +69,6 @@ properties: lowercase to simplify parsing. timebase-frequency: - type: integer - minimum: 1 description: Specifies the clock frequency of the system timer in Hz. This value is common to all harts on a single system image.@@ -102,9 +102,9 @@ examples: cpus { #address-cells = <1>; #size-cells = <0>; - timebase-frequency = <1000000>; cpu@0 { clock-frequency = <0>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; device_type = "cpu"; i-cache-block-size = <64>;@@ -120,6 +120,7 @@ examples: }; cpu@1 { clock-frequency = <0>; + timebase-frequency = <1000000>; compatible = "sifive,rocket0", "riscv"; d-cache-block-size = <64>; d-cache-sets = <64>;Documentation/devicetree/bindings/riscv/cpus.yaml examples: · line 160
Quoted 7 lines
Documentation/devicetree/bindings/riscv/cpus.yaml +1
-0@@ -153,6 +154,7 @@ examples: device_type = "cpu"; reg = <0>; compatible = "riscv"; + timebase-frequency = <1000000>; riscv,isa = "rv64imafdc"; mmu-type = "riscv,sv48"; interrupt-controller {Looking at this spec
Quoted 8 lines
section 3.7 says
Properties that have identical values across cpu nodes may be placed in the /cpus node instead. A client program must
first examine a specific cpu node, but if an expected property is not found then it should look at the parent /cpus node.
This results in a less verbose representation of properties which are identical across all CPUs.The cpu sections of the spec are certainly not perfect. They are largely from PPC with only the most obviously things wrong fixed...
[ ... ]
Quoted 10 lines
Quoted 5 lines
I just bring this up because we've got an outstanding
bug in our port where we're not respecting what section 3.7 says and are only looking at /cpus/timebase-frequency instead of /cpus/cpu@*/timebase-frequency, and I'm wondering if the fix should allow for looking at /cpus/timebase-frequency or just not bother.It's perfectly fine for some deviation for each arch or being more restrictive. For Arm, we've generally gone the direction of everything goes into the cpu nodes. So tell me what you want, I just need the warnings gone.
We probably should keep the timebase-frequency at the /cpus level, since that's how the current public silicon behaves, and that's how our kernel code currently works. Do you want to patch the schemas for that, or would you like us to?
- Paul