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pinctl: armada-37xx: fix for pins 32+

PATCH In review [email protected] 3 participants 8 messages Jun 18, 2019 – Oct 4, 2019

Subsystems (4)
Stable branch GPIO Pin control Arm/Marvell Kirkwood and Armada 370, 375, 38x, 39x, XP, 3700, 7K/8K, CN9130 SoC support
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#0 lore raw

cover pinctl: armada-37xx: fix for pins 32+

From: Patrick Williams <[email protected]>

The 37xx GPIO config registers are only 32 bits long and span 2 registers for the NB GPIO controller. The function to calculate the offset was missing the increase to the config register.

I have tested both raw gpio access and interrupts using libgpiod utilities on an Espressonbin.

The first patch is a simple rename of a function because the original name implied it was doing IO itself ("update reg"). This patch could be dropped if undesired.

The second patch contains the fix for GPIOs 32+.

Patrick Williams (2):
pinctrl: armada-37xx: rename reg-offset function
pinctrl: armada-37xx: fix control of pins 32 and up

 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 20 ++++++++++----------
 1 file changed, 10 insertions(+), 10 deletions(-)
Signature · 1 line
2.17.2 (Apple Git-113)
author
#1 lore raw

PATCH 1/2 pinctrl: armada-37xx: rename reg-offset function

From: Patrick Williams <[email protected]>

The previously named function 'armada_37xx_update_reg' implies that it updates the hardware register, but it only calculates a register offset. Rename to match functionality.

Signed-off-by Patrick Williams <[email protected]>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 16 ++++++++--------
 1 file changed, 8 insertions(+), 8 deletions(-)
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +8 -8
index 6462d3ca7ceb..00598b6f5c2a 100644
@@ -220,8 +220,8 @@ static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
 	.ngroups = ARRAY_SIZE(armada_37xx_sb_groups),
 };
 
-static inline void armada_37xx_update_reg(unsigned int *reg,
-					  unsigned int offset)
+static inline void armada_37xx_calc_reg_offset(unsigned int *reg,
+					       unsigned int offset)
 {
 	/* We never have more than 2 registers */
 	if (offset >= GPIO_PER_REG) {

@@ -376,7 +376,7 @@ static inline void armada_37xx_irq_update_reg(unsigned int *reg,
 {
 	int offset = irqd_to_hwirq(d);
 
-	armada_37xx_update_reg(reg, offset);
+	armada_37xx_calc_reg_offset(reg, offset);
 }
 
 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,

@@ -386,7 +386,7 @@ static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, offset);
 	mask = BIT(offset);
 
 	return regmap_update_bits(info->regmap, reg, mask, 0);

@@ -399,7 +399,7 @@ static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int val, mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, offset);
 	mask = BIT(offset);
 	regmap_read(info->regmap, reg, &val);
 

@@ -413,7 +413,7 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask, val, ret;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, offset);
 	mask = BIT(offset);
 
 	ret = regmap_update_bits(info->regmap, reg, mask, mask);

@@ -434,7 +434,7 @@ static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
 	unsigned int reg = INPUT_VAL;
 	unsigned int val, mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, offset);
 	mask = BIT(offset);
 
 	regmap_read(info->regmap, reg, &val);

@@ -449,7 +449,7 @@ static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
 	unsigned int reg = OUTPUT_VAL;
 	unsigned int mask, val;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, offset);
 	mask = BIT(offset);
 	val = value ? mask : 0;
Signature · 1 line
2.17.2 (Apple Git-113)
author
#2 lore raw

PATCH 2/2 pinctrl: armada-37xx: fix control of pins 32 and up

In reply to [email protected]

From: Patrick Williams <[email protected]>

The 37xx configuration registers are only 32 bits long, so pins 32-35 spill over into the next register. The calculation for the register address was done, but the bitmask was not, so any configuration to pin 32 or above resulted in a bitmask that overflowed and performed no action.

Fix the register / offset calculation to also adjust the offset.

Signed-off-by Patrick Williams <[email protected]>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +9 -9
index 00598b6f5c2a..82c980c5cccd 100644
@@ -221,11 +221,11 @@ static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
 };
 
 static inline void armada_37xx_calc_reg_offset(unsigned int *reg,
-					       unsigned int offset)
+					       unsigned int *offset)
 {
 	/* We never have more than 2 registers */
-	if (offset >= GPIO_PER_REG) {
-		offset -= GPIO_PER_REG;
+	if (*offset >= GPIO_PER_REG) {
+		*offset -= GPIO_PER_REG;
 		*reg += sizeof(u32);
 	}
 }

@@ -376,7 +376,7 @@ static inline void armada_37xx_irq_update_reg(unsigned int *reg,
 {
 	int offset = irqd_to_hwirq(d);
 
-	armada_37xx_calc_reg_offset(reg, offset);
+	armada_37xx_calc_reg_offset(reg, &offset);
 }
 
 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,

@@ -386,7 +386,7 @@ static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask;
 
-	armada_37xx_calc_reg_offset(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, &offset);
 	mask = BIT(offset);
 
 	return regmap_update_bits(info->regmap, reg, mask, 0);

@@ -399,7 +399,7 @@ static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int val, mask;
 
-	armada_37xx_calc_reg_offset(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, &offset);
 	mask = BIT(offset);
 	regmap_read(info->regmap, reg, &val);
 

@@ -413,7 +413,7 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask, val, ret;
 
-	armada_37xx_calc_reg_offset(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, &offset);
 	mask = BIT(offset);
 
 	ret = regmap_update_bits(info->regmap, reg, mask, mask);

@@ -434,7 +434,7 @@ static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
 	unsigned int reg = INPUT_VAL;
 	unsigned int val, mask;
 
-	armada_37xx_calc_reg_offset(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, &offset);
 	mask = BIT(offset);
 
 	regmap_read(info->regmap, reg, &val);

@@ -449,7 +449,7 @@ static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
 	unsigned int reg = OUTPUT_VAL;
 	unsigned int mask, val;
 
-	armada_37xx_calc_reg_offset(&reg, offset);
+	armada_37xx_calc_reg_offset(&reg, &offset);
 	mask = BIT(offset);
 	val = value ? mask : 0;
Signature · 1 line
2.17.2 (Apple Git-113)
author
#3 lore raw

PATCH v2 1/1 pinctrl: armada-37xx: fix control of pins 32 and up

The 37xx configuration registers are only 32 bits long, so pins 32-35 spill over into the next register. The calculation for the register address was done, but the bitmask was not, so any configuration to pin 32 or above resulted in a bitmask that overflowed and performed no action.

Fix the register / offset calculation to also adjust the offset.

Fixes 5715092a458c ("pinctrl: armada-37xx: Add gpio support")
Signed-off-by Patrick Williams <[email protected]>
Acked-by Gregory CLEMENT <[email protected]>
Cc <[email protected]>
---
 drivers/pinctrl/mvebu/pinctrl-armada-37xx.c | 18 +++++++++---------
 1 file changed, 9 insertions(+), 9 deletions(-)
drivers/pinctrl/mvebu/pinctrl-armada-37xx.c +9 -9
index 6462d3ca7ceb..34c1fee52cbe 100644
@@ -221,11 +221,11 @@ static const struct armada_37xx_pin_data armada_37xx_pin_sb = {
 };
 
 static inline void armada_37xx_update_reg(unsigned int *reg,
-					  unsigned int offset)
+					  unsigned int *offset)
 {
 	/* We never have more than 2 registers */
-	if (offset >= GPIO_PER_REG) {
-		offset -= GPIO_PER_REG;
+	if (*offset >= GPIO_PER_REG) {
+		*offset -= GPIO_PER_REG;
 		*reg += sizeof(u32);
 	}
 }

@@ -376,7 +376,7 @@ static inline void armada_37xx_irq_update_reg(unsigned int *reg,
 {
 	int offset = irqd_to_hwirq(d);
 
-	armada_37xx_update_reg(reg, offset);
+	armada_37xx_update_reg(reg, &offset);
 }
 
 static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,

@@ -386,7 +386,7 @@ static int armada_37xx_gpio_direction_input(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_update_reg(&reg, &offset);
 	mask = BIT(offset);
 
 	return regmap_update_bits(info->regmap, reg, mask, 0);

@@ -399,7 +399,7 @@ static int armada_37xx_gpio_get_direction(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int val, mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_update_reg(&reg, &offset);
 	mask = BIT(offset);
 	regmap_read(info->regmap, reg, &val);
 

@@ -413,7 +413,7 @@ static int armada_37xx_gpio_direction_output(struct gpio_chip *chip,
 	unsigned int reg = OUTPUT_EN;
 	unsigned int mask, val, ret;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_update_reg(&reg, &offset);
 	mask = BIT(offset);
 
 	ret = regmap_update_bits(info->regmap, reg, mask, mask);

@@ -434,7 +434,7 @@ static int armada_37xx_gpio_get(struct gpio_chip *chip, unsigned int offset)
 	unsigned int reg = INPUT_VAL;
 	unsigned int val, mask;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_update_reg(&reg, &offset);
 	mask = BIT(offset);
 
 	regmap_read(info->regmap, reg, &val);

@@ -449,7 +449,7 @@ static void armada_37xx_gpio_set(struct gpio_chip *chip, unsigned int offset,
 	unsigned int reg = OUTPUT_VAL;
 	unsigned int mask, val;
 
-	armada_37xx_update_reg(&reg, offset);
+	armada_37xx_update_reg(&reg, &offset);
 	mask = BIT(offset);
 	val = value ? mask : 0;
Signature · 1 line
2.17.2 (Apple Git-113)
#4 lore raw

Re: [PATCH v2] pinctrl: armada-37xx: fix control of pins 32 and up

Quoted 6 lines · Patrick Williams

The 37xx configuration registers are only 32 bits long, so pins 32-35 spill over into the next register. The calculation for the register address was done, but the bitmask was not, so any configuration to pin 32 or above resulted in a bitmask that overflowed and performed no action.

Quoted 6 lines

Fix the register / offset calculation to also adjust the offset.

Fixes 5715092a458c ("pinctrl: armada-37xx: Add gpio support")
Signed-off-by Patrick Williams <[email protected]>
Acked-by Gregory CLEMENT <[email protected]>
Cc <[email protected]>

Patch applied for fixes.

Yours,
Linus Walleij

#5 lore raw
In reply to [email protected]
Quoted 7 lines · On Tue, Jun 18, 2019 at 6:01 PM <[email protected]> wrote:

From: Patrick Williams <[email protected]>

The 37xx GPIO config registers are only 32 bits long and span 2 registers for the NB GPIO controller. The function to calculate the offset was missing the increase to the config register.

Quoted 8 lines

I have tested both raw gpio access and interrupts using libgpiod utilities on an Espressonbin.

The first patch is a simple rename of a function because the original name implied it was doing IO itself ("update reg"). This patch could be dropped if undesired.

The second patch contains the fix for GPIOs 32+.

This looks good overall. I am waiting for a maintainer review. If nothing happens in a week, poke me and I'll just apply the patches.

Yours,
Linus Walleij

maintainer Acked-by
#6 lore raw

Hi,

Quoted 9 lines · On Tue, Jun 18, 2019 at 6:01 PM <[email protected]> wrote:
Quoted 8 lines

From: Patrick Williams <[email protected]>

The 37xx GPIO config registers are only 32 bits long and span 2 registers for the NB GPIO controller. The function to calculate the offset was missing the increase to the config register.

Quoted 8 lines
Quoted 8 lines

I have tested both raw gpio access and interrupts using libgpiod utilities on an Espressonbin.

The first patch is a simple rename of a function because the original name implied it was doing IO itself ("update reg"). This patch could be dropped if undesired.

The second patch contains the fix for GPIOs 32+.

First you can add my

Acked-by Gregory CLEMENT <[email protected]>

Then as the second patch is a fix, you should add the fix tag: "Fixes:
5715092a458c ("pinctrl: armada-37xx: Add gpio support") " as well as the 'CC: <[email protected]>" tags.

But your change in the first patch made this second patch more difficult to backport.

Actually, when I wrote "_update_reg" I was thinking to the update of the variable, whereas with a function named "_calculate_reg" I am expecting having the result as a return of the function.

However I am not against your change, as I pointed my main concern is about the backport of the patch to the stable branch.

Maybe you could change the order of those 2 patches?

Thanks,

Gregory

Quoted 12 lines

This looks good overall. I am waiting for a maintainer review. If nothing happens in a week, poke me and I'll just apply the patches.

Yours,
Linus Walleij

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Signature · 3 lines
Gregory Clement, Bootlin
Embedded Linux and Kernel engineering
http://bootlin.com
author
#7 lore raw
Quoted 2 lines · Gregory CLEMENT

First you can add my

Acked-by Gregory CLEMENT <[email protected]>

Thanks for the review Gregory.

Quoted 8 lines

Then as the second patch is a fix, you should add the fix tag: "Fixes:
5715092a458c ("pinctrl: armada-37xx: Add gpio support") " as well as the 'CC: <[email protected]>" tags.

But your change in the first patch made this second patch more difficult to backport.
...
Maybe you could change the order of those 2 patches?

Good points. Will do both.

Quoted 3 lines

Actually, when I wrote "_update_reg" I was thinking to the update of the variable, whereas with a function named "_calculate_reg" I am expecting having the result as a return of the function.

Understand. I can see the ambiguity in both names. How about "_update_reg_offset"?

Quoted 4 lines

Thanks,

Gregory

Signature · 1 line
- Patrick