Add a new IGT test to validate DC3CO state.

ontent-Length: 2643

From: Anshuman Gupta <[email protected]>

Add DC3CO IGT validation prerequisites stuff
so we can enable DC3CO IGT test.

v2: Removed psr2_idle_wait_entry and get_psr2_status function.

v3: Changed macro definition and removed extra line.

Signed-off-by Anshuman Gupta <[email protected]>

Signed-off-by Jeevan B <[email protected]>

---
 tests/i915/i915_pm_dc.c | 37 ++++++++++++++++++++++++++++++-------
 1 file changed, 30 insertions(+), 7 deletions(-)

tests/i915/i915_pm_dc.c +3 -2

index ce3319b..0ddd6b3 100644
@@ -34,8 +34,9 @@
 #include "limits.h"
 
 /* DC State Flags */
-#define CHECK_DC5	1
-#define CHECK_DC6	2
+#define CHECK_DC5	(1 << 0)
+#define CHECK_DC6	(1 << 1)
+#define CHECK_DC3CO	(1 << 2)
 
 typedef struct {
 	int drm_fd;

@@ -88,6 +89,19 @@ static bool edp_psr_sink_support(data_t *data)
 	return strstr(buf, "Sink support: yes");
 }

tests/i915/i915_pm_dc.c +14 -3

+
+	return false;
+}
+
 static void cleanup_dc_psr(data_t *data)
 {
 	igt_plane_t *primary;

@@ -141,12 +155,18 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
 		str = strstr(buf, "DC3 -> DC5 count");
 	else if (dc_flag & CHECK_DC6)
 		str = strstr(buf, "DC5 -> DC6 count");
+	else if (dc_flag & CHECK_DC3CO)
+		str = strstr(buf, "DC3CO count");
 
-	/* Check DC5/DC6 counter is available for the platform.
+	/* Check DC counter is available for the platform.
 	 * Skip the test if counter is not available.
 	 */
-	igt_skip_on_f(!str, "DC%d counter is not available\n",
-		      dc_flag & CHECK_DC5 ? 5 : 6);
+	if (dc_flag & CHECK_DC3CO)
+		igt_skip_on_f(!str, "DC3CO counter is not available\n");
+	else
+		igt_skip_on_f(!str, "DC%d counter is not available\n",
+			      dc_flag & CHECK_DC5 ? 5 : 6);
+
 	return get_dc_counter(str);
 }
 

@@ -158,9 +178,12 @@ static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
 
 static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
 {
+	char tmp[64];

Add a subtest for DC3CO video playback case to generate selective frame update and validate that system stays in DC3CO state during execution.

v2: Changed PSR2 idle check to sleep check and addressed cosmetic changes.
v3: Renamed a function and restructured code according to Anshuman’s comments.
v4: Cosmetic changes.
v5: Removed DC5 check, Platform check and a function parameter.
Renamed a function name as per Arek and Imre's Comments.

Signed-off-by Jeevan B <[email protected]>

---
 lib/igt_psr.c           |  10 ++++
 lib/igt_psr.h           |   1 +
 tests/i915/i915_pm_dc.c | 135 +++++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 145 insertions(+), 1 deletion(-)

lib/igt_psr.c +10 -0

index b92ea73..9127a0b 100644
@@ -36,6 +36,16 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
 	return strstr(buf, state);
 }
 
+bool psr2_active_sleep_check(int debugfs_fd)
+{
+	char buf[PSR_STATUS_MAX_LEN];
+	const char *state = "SLEEP";
+
+	igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
+				sizeof(buf));
+	return strstr(buf, state);
+}
+
 static inline const char *psr_active_state_get(enum psr_mode mode)
 {
 	return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";

lib/igt_psr.h +1 -0

index ca38573..a0627dc 100644
@@ -35,6 +35,7 @@ enum psr_mode {
 	PSR_MODE_2
 };
 
+bool psr2_active_sleep_check(int debugfs_fd);
 bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
 bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
 bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);

tests/i915/i915_pm_dc.c +106 -1

index 0ddd6b3..ac6270f 100644
@@ -38,13 +38,20 @@
 #define CHECK_DC6	(1 << 1)
 #define CHECK_DC3CO	(1 << 2)
 
+/*Number of Frames Video Playback*/
+#define VIDEO_FRAMES 130
+
+typedef struct {
+	double r, g, b;
+} color_t;
+
 typedef struct {
 	int drm_fd;
 	int msr_fd;
 	int debugfs_fd;
 	uint32_t devid;
 	igt_display_t display;
-	struct igt_fb fb_white;
+	struct igt_fb fb_white, fb_rgb, fb_rgr;
 	enum psr_mode op_psr_mode;
 	drmModeModeInfo *mode;
 	igt_output_t *output;

@@ -113,6 +120,42 @@ static void cleanup_dc_psr(data_t *data)
 	igt_remove_fb(data->drm_fd, &data->fb_white);
 }
 
+static void cleanup_dc3co(data_t *data)
+{
+	igt_plane_t *primary;
+
+	primary = igt_output_get_plane_type(data->output,
+					   DRM_PLANE_TYPE_PRIMARY);
+	igt_plane_set_fb(primary, NULL);
+	/* Clear Frame Buffers */
+	igt_display_commit(&data->display);
+	igt_remove_fb(data->drm_fd, &data->fb_rgb);
+	igt_remove_fb(data->drm_fd, &data->fb_rgr);
+}
+
+static void paint_rectangles(data_t *data,
+			     drmModeModeInfo *mode,
+			     color_t *colors,
+			     igt_fb_t *fb)
+{
+	cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
+	int i, l = mode->hdisplay / 3;
+	int rows_remaining = mode->hdisplay % 3;
+
+	/* Paint 3 solid rectangles. */
+	for (i = 0 ; i < 3; i++) {
+		igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
+				colors[i].r, colors[i].g, colors[i].b);
+	}
+
+	if (rows_remaining > 0)
+		igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
+				colors[i - 1].r, colors[i - 1].g,
+				colors[i - 1].b);
+
+	igt_put_cairo_ctx(data->drm_fd, fb, cr);
+}
+
 static void setup_primary(data_t *data)
 {
 	igt_plane_t *primary;

@@ -130,6 +173,20 @@ static void setup_primary(data_t *data)
 	igt_display_commit(&data->display);
 }
 
+static void create_color_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
+{
+	int fb_id;
+
+	fb_id = igt_create_fb(data->drm_fd,
+			      data->mode->hdisplay,
+			      data->mode->vdisplay,
+			      DRM_FORMAT_XRGB8888,
+			      LOCAL_DRM_FORMAT_MOD_NONE,
+			      fb);
+	igt_assert(fb_id);
+	paint_rectangles(data, data->mode, fb_color, fb);
+}
+
 static uint32_t get_dc_counter(char *dc_data)
 {
 	char *e;

@@ -170,6 +227,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
 	return get_dc_counter(str);
 }
 
+static bool psr2_wait_sleep_entry(int debugfs_fd)
+{
+	return igt_wait(psr2_active_sleep_check(debugfs_fd), 50, 10);
+}
+
 static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
 {
 	return igt_wait(read_dc_counter(drm_fd, dc_flag) >

@@ -186,6 +248,70 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
 		     "%s state is not achieved\n", tmp);
 }
 
+static void setup_videoplayback(data_t *data)
+{
+	color_t red_green_blue[] = {
+			{ 1.0, 0.0, 0.0 },
+			{ 0.0, 1.0, 0.0 },
+			{ 0.0, 0.0, 1.0 },
+	};
+	color_t red_green_red[] = {
+			{ 1.0, 0.0, 0.0 },
+			{ 0.0, 1.0, 0.0 },
+			{ 1.0, 0.0, 0.0 },
+	};
+
+	create_color_fb(data, &data->fb_rgb, red_green_blue);
+	create_color_fb(data, &data->fb_rgr, red_green_red);
+}
+
+static void check_dc3co_with_videoplayback_like_load(data_t *data)
+{
+	igt_plane_t *primary;
+	uint32_t dc3co_prev_cnt;
+	int i, delay;
+
+	primary = igt_output_get_plane_type(data->output,
+					    DRM_PLANE_TYPE_PRIMARY);
+	igt_plane_set_fb(primary, NULL);
+	dc3co_prev_cnt = read_dc_counter(data->drm_fd, CHECK_DC3CO);
+	/* Calculate delay to generate idle frame in usec*/
+	delay = ((1000 * 1000) / data->mode->vrefresh);
+
+	for (i = 0; i < VIDEO_FRAMES; i++) {
+		if (i % 2 == 0) {
+			igt_plane_set_fb(primary, &data->fb_rgb);
+			igt_display_commit(&data->display);
+		} else {
+			igt_plane_set_fb(primary, &data->fb_rgr);
+			igt_display_commit(&data->display);
+		}
+
+		usleep(delay);
+		igt_assert(psr2_wait_sleep_entry(data->debugfs_fd));
+	}
+

tests/i915/i915_pm_dc.c +18 -0

+}
+
+static void test_dc3co_vpb_simulation(data_t *data)
+{
+	setup_output(data);
+	setup_dc3co(data);
+	setup_videoplayback(data);
+	check_dc3co_with_videoplayback_like_load(data);
+	cleanup_dc3co(data);
+}
+
 static void test_dc_state_psr(data_t *data, int dc_flag)
 {
 	uint32_t dc_counter_before_psr;

@@ -287,6 +413,13 @@ int main(int argc, char *argv[])
 			     "Can't open /dev/cpu/0/msr.\n");
 	}
 
+	igt_describe("This test simulate video playback "
+		     "in order to validate DC3CO state "
+		     "while PSR2 is active and in SLEEP state");
+	igt_subtest("dc3co-vpb-simulation") {
+		test_dc3co_vpb_simulation(&data);
+	}
+
 	igt_describe("This test validates display engine entry to DC5 state "
 		     "while PSR is active");
 	igt_subtest("dc5-psr") {

Signature · 1 line

2.7.4

Add a subtest for DC3CO video playback case to generate selective frame update and validate that system stays in DC3CO state during execution.

v2: Changed PSR2 idle check to sleep check and addressed cosmetic changes.
v3: Renamed a function and restructured code according to Anshuman’s comments.
v4: Cosmetic changes.
v5: Removed DC5 check, Platform check and a function parameter.
Renamed a function name as per Arek and Imre's Comments.

Signed-off-by Jeevan B <[email protected]>

---
 lib/igt_psr.c           |  10 ++++
 lib/igt_psr.h           |   1 +
 tests/i915/i915_pm_dc.c | 135 +++++++++++++++++++++++++++++++++++++++++++++++-
 3 files changed, 145 insertions(+), 1 deletion(-)

lib/igt_psr.c +10 -0

index b92ea73..9127a0b 100644
@@ -36,6 +36,16 @@ static bool psr_active_check(int debugfs_fd, enum psr_mode mode)
 	return strstr(buf, state);
 }
 
+bool psr2_active_sleep_check(int debugfs_fd)
+{
+	char buf[PSR_STATUS_MAX_LEN];
+	const char *state = "SLEEP";
+
+	igt_debugfs_simple_read(debugfs_fd, "i915_edp_psr_status", buf,
+				sizeof(buf));
+	return strstr(buf, state);
+}
+
 static inline const char *psr_active_state_get(enum psr_mode mode)
 {
 	return mode == PSR_MODE_1 ? "SRDENT" : "DEEP_SLEEP";

lib/igt_psr.h +1 -0

index ca38573..a0627dc 100644
@@ -35,6 +35,7 @@ enum psr_mode {
 	PSR_MODE_2
 };
 
+bool psr2_active_sleep_check(int debugfs_fd);
 bool psr_wait_entry(int debugfs_fd, enum psr_mode mode);
 bool psr_wait_update(int debugfs_fd, enum psr_mode mode);
 bool psr_long_wait_update(int debugfs_fd, enum psr_mode mode);

tests/i915/i915_pm_dc.c +84 -1

index 0ddd6b3..ac6270f 100644
@@ -38,13 +38,20 @@
 #define CHECK_DC6	(1 << 1)
 #define CHECK_DC3CO	(1 << 2)
 
+/*Number of Frames Video Playback*/
+#define VIDEO_FRAMES 130
+
+typedef struct {
+	double r, g, b;
+} color_t;
+
 typedef struct {
 	int drm_fd;
 	int msr_fd;
 	int debugfs_fd;
 	uint32_t devid;
 	igt_display_t display;
-	struct igt_fb fb_white;
+	struct igt_fb fb_white, fb_rgb, fb_rgr;
 	enum psr_mode op_psr_mode;
 	drmModeModeInfo *mode;
 	igt_output_t *output;

@@ -113,6 +120,42 @@ static void cleanup_dc_psr(data_t *data)
 	igt_remove_fb(data->drm_fd, &data->fb_white);
 }
 
+static void cleanup_dc3co(data_t *data)
+{
+	igt_plane_t *primary;
+
+	primary = igt_output_get_plane_type(data->output,
+					   DRM_PLANE_TYPE_PRIMARY);
+	igt_plane_set_fb(primary, NULL);
+	/* Clear Frame Buffers */
+	igt_display_commit(&data->display);
+	igt_remove_fb(data->drm_fd, &data->fb_rgb);
+	igt_remove_fb(data->drm_fd, &data->fb_rgr);
+}
+
+static void paint_rectangles(data_t *data,
+			     drmModeModeInfo *mode,
+			     color_t *colors,
+			     igt_fb_t *fb)
+{
+	cairo_t *cr = igt_get_cairo_ctx(data->drm_fd, fb);
+	int i, l = mode->hdisplay / 3;
+	int rows_remaining = mode->hdisplay % 3;
+
+	/* Paint 3 solid rectangles. */
+	for (i = 0 ; i < 3; i++) {
+		igt_paint_color(cr, i * l, 0, l, mode->vdisplay,
+				colors[i].r, colors[i].g, colors[i].b);
+	}
+
+	if (rows_remaining > 0)
+		igt_paint_color(cr, i * l, 0, rows_remaining, mode->vdisplay,
+				colors[i - 1].r, colors[i - 1].g,
+				colors[i - 1].b);
+
+	igt_put_cairo_ctx(data->drm_fd, fb, cr);
+}
+
 static void setup_primary(data_t *data)
 {
 	igt_plane_t *primary;

@@ -130,6 +173,20 @@ static void setup_primary(data_t *data)
 	igt_display_commit(&data->display);
 }
 
+static void create_color_fb(data_t *data, igt_fb_t *fb, color_t *fb_color)
+{
+	int fb_id;
+
+	fb_id = igt_create_fb(data->drm_fd,
+			      data->mode->hdisplay,
+			      data->mode->vdisplay,
+			      DRM_FORMAT_XRGB8888,
+			      LOCAL_DRM_FORMAT_MOD_NONE,
+			      fb);
+	igt_assert(fb_id);
+	paint_rectangles(data, data->mode, fb_color, fb);
+}
+
 static uint32_t get_dc_counter(char *dc_data)
 {
 	char *e;

@@ -170,6 +227,11 @@ static uint32_t read_dc_counter(uint32_t drm_fd, int dc_flag)
 	return get_dc_counter(str);
 }
 
+static bool psr2_wait_sleep_entry(int debugfs_fd)
+{
+	return igt_wait(psr2_active_sleep_check(debugfs_fd), 50, 10);
+}
+
 static bool dc_state_wait_entry(int drm_fd, int dc_flag, int prev_dc_count)
 {
 	return igt_wait(read_dc_counter(drm_fd, dc_flag) >

@@ -186,6 +248,70 @@ static void check_dc_counter(int drm_fd, int dc_flag, uint32_t prev_dc_count)
 		     "%s state is not achieved\n", tmp);
 }
 
+static void setup_videoplayback(data_t *data)
+{
+	color_t red_green_blue[] = {
+			{ 1.0, 0.0, 0.0 },
+			{ 0.0, 1.0, 0.0 },
+			{ 0.0, 0.0, 1.0 },
+	};
+	color_t red_green_red[] = {
+			{ 1.0, 0.0, 0.0 },
+			{ 0.0, 1.0, 0.0 },
+			{ 1.0, 0.0, 0.0 },
+	};
+
+	create_color_fb(data, &data->fb_rgb, red_green_blue);
+	create_color_fb(data, &data->fb_rgr, red_green_red);
+}
+
+static void check_dc3co_with_videoplayback_like_load(data_t *data)
+{
+	igt_plane_t *primary;
+	uint32_t dc3co_prev_cnt;

tests/i915/i915_pm_dc.c +30 -0

+	}
+
+	check_dc_counter(data->drm_fd, CHECK_DC3CO, dc3co_prev_cnt);
+}
+
+static void setup_dc3co(data_t *data)
+{
+	data->op_psr_mode = PSR_MODE_2;
+	psr_enable(data->debugfs_fd, data->op_psr_mode);
+	igt_require_f(edp_psr2_enabled(data),
+		      "PSR2 is not enabled\n");
+	igt_require(read_dc_counter(data->drm_fd, CHECK_DC3CO));
+}
+
+static void test_dc3co_vpb_simulation(data_t *data)
+{
+	setup_output(data);
+	setup_dc3co(data);
+	setup_videoplayback(data);
+	check_dc3co_with_videoplayback_like_load(data);
+	cleanup_dc3co(data);
+}
+
 static void test_dc_state_psr(data_t *data, int dc_flag)
 {
 	uint32_t dc_counter_before_psr;

@@ -287,6 +413,13 @@ int main(int argc, char *argv[])
 			     "Can't open /dev/cpu/0/msr.\n");
 	}
 
+	igt_describe("This test simulate video playback "
+		     "in order to validate DC3CO state "
+		     "while PSR2 is active and in SLEEP state");
+	igt_subtest("dc3co-vpb-simulation") {
+		test_dc3co_vpb_simulation(&data);
+	}
+
 	igt_describe("This test validates display engine entry to DC5 state "
 		     "while PSR is active");
 	igt_subtest("dc5-psr") {

Signature · 1 line

2.7.4