Switch the order of the parameters in report() and report_xfail()

Commit c09c54c66b1df ("lib: use an argument which doesn't require default argument promotion") fixed a warning that occurs with Clang, but introduced a regression: If the "pass" parameter is a value which has only set the condition bits in the upper 32 bits of a 64 bit value, the condition is now false since the value is truncated to "unsigned int" so that the upper bits are simply discarded.

To fix this, it would be best to use "bool" for the "pass" parameter again. But we can not use "bool" if it is the last parameter before the variable argument list, so we have to swap the parameters around and make the format string the last parameter.

This patch (except the changes in lib/libcflat.h and lib/report.c) has basically been created with following coccinelle script (with some manual tweaking of long and disabled lines afterwards):

@@
expression fmt;
expression pass;
expression list args;
@@
report(

(quoted diff) +1 -1

-fmt, pass
+pass, fmt
 , args);

@@
expression fmt;
expression pass;
expression list args;
@@
report_xfail(

(quoted diff) +1 -1

-fmt, xfail, pass
+xfail, pass, fmt
 , args);

Fixes c09c54c66b1d ("lib: use an argument which doesn't require ...")

Signed-off-by Thomas Huth <[email protected]>

---
 arm/gic.c                 |  67 +++--
 arm/pci-test.c            |   4 +-
 arm/pmu.c                 |   9 +-
 arm/psci.c                |  10 +-
 arm/selftest.c            |  14 +-
 arm/spinlock-test.c       |   2 +-
 arm/timer.c               |  16 +-
 lib/libcflat.h            |   8 +-
 lib/report.c              |   8 +-
 lib/s390x/interrupt.c     |   5 +-
 lib/x86/fault_test.c      |   2 +-
 powerpc/emulator.c        |  44 +--
 powerpc/rtas.c            |  32 +-
 powerpc/selftest.c        |   4 +-
 powerpc/spapr_hcall.c     |  30 +-
 powerpc/sprs.c            |   5 +-
 powerpc/tm.c              |   6 +-
 s390x/cpumodel.c          |   2 +-
 s390x/diag288.c           |   2 +-
 s390x/diag308.c           |   4 +-
 s390x/emulator.c          |  18 +-
 s390x/gs.c                |   2 +-
 s390x/intercept.c         |  16 +-
 s390x/pfmf.c              |   9 +-
 s390x/selftest.c          |  23 +-
 s390x/skey.c              |  11 +-
 s390x/skrf.c              |  10 +-
 s390x/smp.c               |  37 +--
 s390x/sthyi.c             |  41 +--
 s390x/stsi.c              |   8 +-
 s390x/vector.c            |   6 +-
 x86/apic.c                | 148 +++++-----
 x86/asyncpf.c             |  11 +-
 x86/cmpxchg8b.c           |   2 +-
 x86/debug.c               |  69 +++--
 x86/emulator.c            | 290 +++++++++---------
 x86/eventinj.c            |  30 +-
 x86/hypercall.c           |   6 +-
 x86/hyperv_clock.c        |   9 +-
 x86/hyperv_connections.c  |  28 +-
 x86/hyperv_stimer.c       |  28 +-
 x86/hyperv_synic.c        |   4 +-
 x86/idt_test.c            |   8 +-
 x86/intel-iommu.c         |  25 +-
 x86/ioapic.c              |  57 ++--
 x86/memory.c              |  17 +-
 x86/msr.c                 |   2 +-
 x86/pcid.c                |  10 +-
 x86/pku.c                 |  20 +-
 x86/pmu.c                 |  25 +-
 x86/rdpru.c               |   2 +-
 x86/smap.c                |  28 +-
 x86/smptest.c             |   2 +-
 x86/svm.c                 |  14 +-
 x86/syscall.c             |   4 +-
 x86/taskswitch2.c         |  26 +-
 x86/tsc.c                 |   4 +-
 x86/tsc_adjust.c          |  22 +-
 x86/tscdeadline_latency.c |   2 +-
 x86/umip.c                |  24 +-
 x86/vmx.c                 | 167 +++++------
 x86/vmx.h                 |   9 +-
 x86/vmx_tests.c           | 599 ++++++++++++++++++++------------------
 x86/xsave.c               |  80 ++---
 64 files changed, 1152 insertions(+), 1075 deletions(-)

arm/gic.c +35 -32

index ed5642e..2e52e0e 100644
@@ -88,7 +88,7 @@ static void check_acked(cpumask_t *mask)
 			}
 		}
 		if (nr_pass == nr_cpus) {
-			report("Completed in %d ms", !bad, ++i * 100);
+			report(!bad, "Completed in %d ms", ++i * 100);
 			return;
 		}
 	}

@@ -105,8 +105,9 @@ static void check_acked(cpumask_t *mask)
 		}
 	}
 
-	report("Timed-out (5s). ACKS: missing=%d extra=%d unexpected=%d",
-	       false, missing, extra, unexpected);
+	report(false,
+	       "Timed-out (5s). ACKS: missing=%d extra=%d unexpected=%d",
+	       missing, extra, unexpected);
 }
 
 static void check_spurious(void)

@@ -350,7 +351,7 @@ static void test_typer_v2(uint32_t reg)
 {
 	int nr_gic_cpus = ((reg >> 5) & 0x7) + 1;
 
-	report("all %d CPUs have interrupts", nr_cpus == nr_gic_cpus,
+	report(nr_cpus == nr_gic_cpus, "all %d CPUs have interrupts",
 	       nr_gic_cpus);
 }
 

@@ -368,15 +369,16 @@ static void test_byte_access(void *base_addr, u32 pattern, u32 mask)
 {
 	u32 reg = readb(base_addr + 1);
 
-	report("byte reads successful (0x%08x => 0x%02x)",
-	       reg == (BYTE(pattern, 1) & (mask >> 8)),
+	report(reg == (BYTE(pattern, 1) & (mask >> 8)),
+	       "byte reads successful (0x%08x => 0x%02x)",
 	       pattern & mask, reg);
 
 	pattern = REPLACE_BYTE(pattern, 2, 0x1f);
 	writeb(BYTE(pattern, 2), base_addr + 2);
 	reg = readl(base_addr);
-	report("byte writes successful (0x%02x => 0x%08x)",
-	       reg == (pattern & mask), BYTE(pattern, 2), reg);
+	report(reg == (pattern & mask),
+	       "byte writes successful (0x%02x => 0x%08x)", BYTE(pattern, 2),
+	       reg);
 }
 
 static void test_priorities(int nr_irqs, void *priptr)

@@ -396,33 +398,33 @@ static void test_priorities(int nr_irqs, void *priptr)
 	pri_mask = readl(first_spi);
 
 	reg = ~pri_mask;
-	report("consistent priority masking (0x%08x)",
-	       (((reg >> 16) == (reg & 0xffff)) &&
-	        ((reg & 0xff) == ((reg >> 8) & 0xff))), pri_mask);
+	report((((reg >> 16) == (reg & 0xffff)) &&
+	       ((reg & 0xff) == ((reg >> 8) & 0xff))),
+	       "consistent priority masking (0x%08x)", pri_mask);
 
 	reg = reg & 0xff;
 	for (pri_bits = 8; reg & 1; reg >>= 1, pri_bits--)
 		;
-	report("implements at least 4 priority bits (%d)",
-	       pri_bits >= 4, pri_bits);
+	report(pri_bits >= 4, "implements at least 4 priority bits (%d)",
+	       pri_bits);
 
 	pattern = 0;
 	writel(pattern, first_spi);
-	report("clearing priorities", readl(first_spi) == pattern);
+	report(readl(first_spi) == pattern, "clearing priorities");
 
 	/* setting all priorities to their max valus was tested above */
 
-	report("accesses beyond limit RAZ/WI",
-	       test_readonly_32(priptr + nr_irqs, true));
+	report(test_readonly_32(priptr + nr_irqs, true),
+	       "accesses beyond limit RAZ/WI");
 
 	writel(pattern, priptr + nr_irqs - 4);
-	report("accessing last SPIs",
-	       readl(priptr + nr_irqs - 4) == (pattern & pri_mask));
+	report(readl(priptr + nr_irqs - 4) == (pattern & pri_mask),
+	       "accessing last SPIs");
 
 	pattern = 0xff7fbf3f;
 	writel(pattern, first_spi);
-	report("priorities are preserved",
-	       readl(first_spi) == (pattern & pri_mask));
+	report(readl(first_spi) == (pattern & pri_mask),
+	       "priorities are preserved");
 
 	/* The PRIORITY registers are byte accessible. */
 	test_byte_access(first_spi, pattern, pri_mask);

@@ -449,21 +451,22 @@ static void test_targets(int nr_irqs)
 	/* Check that bits for non implemented CPUs are RAZ/WI. */
 	if (nr_cpus < 8) {
 		writel(0xffffffff, targetsptr + GIC_FIRST_SPI);
-		report("bits for %d non-existent CPUs masked",
-		       !(readl(targetsptr + GIC_FIRST_SPI) & ~cpu_mask),
+		report(!(readl(targetsptr + GIC_FIRST_SPI) & ~cpu_mask),
+		       "bits for %d non-existent CPUs masked",
 		       8 - nr_cpus);
 	} else {
 		report_skip("CPU masking (all CPUs implemented)");
 	}
 
-	report("accesses beyond limit RAZ/WI",
-	       test_readonly_32(targetsptr + nr_irqs, true));
+	report(test_readonly_32(targetsptr + nr_irqs, true),
+	       "accesses beyond limit RAZ/WI");
 
 	pattern = 0x0103020f;
 	writel(pattern, targetsptr + GIC_FIRST_SPI);
 	reg = readl(targetsptr + GIC_FIRST_SPI);
-	report("register content preserved (%08x => %08x)",
-	       reg == (pattern & cpu_mask), pattern & cpu_mask, reg);
+	report(reg == (pattern & cpu_mask),
+	       "register content preserved (%08x => %08x)",
+	       pattern & cpu_mask, reg);
 
 	/* The TARGETS registers are byte accessible. */
 	test_byte_access(targetsptr + GIC_FIRST_SPI, pattern, cpu_mask);

@@ -496,14 +499,14 @@ static void gic_test_mmio(void)
 
 	report_info("IIDR: 0x%08x", readl(gic_dist_base + GICD_IIDR));
 
-	report("GICD_TYPER is read-only",
-	       test_readonly_32(gic_dist_base + GICD_TYPER, false));
-	report("GICD_IIDR is read-only",
-	       test_readonly_32(gic_dist_base + GICD_IIDR, false));
+	report(test_readonly_32(gic_dist_base + GICD_TYPER, false),
+               "GICD_TYPER is read-only");
+	report(test_readonly_32(gic_dist_base + GICD_IIDR, false),
+               "GICD_IIDR is read-only");
 
 	reg = readl(idreg);
-	report("ICPIDR2 is read-only (0x%08x)",
-	       test_readonly_32(idreg, false),
+	report(test_readonly_32(idreg, false),
+	       "ICPIDR2 is read-only (0x%08x)",
 	       reg);
 
 	test_priorities(nr_irqs, gic_dist_base + GICD_IPRIORITYR);

arm/pci-test.c +2 -2

index cf128ac..879b254 100644
@@ -25,8 +25,8 @@ int main(void)
 	if (ret == -1)
 		report_skip("No PCI test device");
 	else
-		report("PCI test device passed %d/%d tests",
-			ret >= NR_TESTS, ret > 0 ? ret : 0, NR_TESTS);
+		report(ret >= NR_TESTS, "PCI test device passed %d/%d tests",
+		       ret > 0 ? ret : 0, NR_TESTS);
 
 	return report_summary();
 }

arm/pmu.c +5 -4

index 1de7d77..d5a03a6 100644
@@ -268,7 +268,7 @@ static void pmccntr64_test(void)
 	if (pmu_version == 0x3) {
 		if (ERRATA(9e3f7a296940)) {
 			write_sysreg(0xdead, PMCCNTR64);
-			report("pmccntr64", read_sysreg(PMCCNTR64) == 0xdead);
+			report(read_sysreg(PMCCNTR64) == 0xdead, "pmccntr64");
 		} else
 			report_skip("Skipping unsafe pmccntr64 test. Set ERRATA_9e3f7a296940=y to enable.");
 	}

@@ -297,9 +297,10 @@ int main(int argc, char *argv[])
 
 	report_prefix_push("pmu");
 
-	report("Control register", check_pmcr());
-	report("Monotonically increasing cycle count", check_cycles_increase());
-	report("Cycle/instruction ratio", check_cpi(cpi));
+	report(check_pmcr(), "Control register");
+	report(check_cycles_increase(),
+	       "Monotonically increasing cycle count");
+	report(check_cpi(cpi), "Cycle/instruction ratio");
 
 	pmccntr64_test();
 

arm/psci.c +5 -5

index 5cb4d5c..7f47a21 100644
@@ -133,12 +133,12 @@ int main(void)
 
 	report_info("PSCI version %d.%d", PSCI_VERSION_MAJOR(ver),
 					  PSCI_VERSION_MINOR(ver));
-	report("invalid-function", psci_invalid_function());
-	report("affinity-info-on", psci_affinity_info_on());
-	report("affinity-info-off", psci_affinity_info_off());
+	report(psci_invalid_function(), "invalid-function");
+	report(psci_affinity_info_on(), "affinity-info-on");
+	report(psci_affinity_info_off(), "affinity-info-off");
 
 	if (ERRATA(6c7a5dce22b3))
-		report("cpu-on", psci_cpu_on_test());
+		report(psci_cpu_on_test(), "cpu-on");
 	else
 		report_skip("Skipping unsafe cpu-on test. Set ERRATA_6c7a5dce22b3=y to enable.");
 

@@ -146,7 +146,7 @@ done:
 #if 0
 	report_summary();
 	psci_invoke(PSCI_0_2_FN_SYSTEM_OFF, 0, 0, 0);
-	report("system-off", false);
+	report(false, "system-off");
 	return 1; /* only reaches here if system-off fails */
 #else
 	return report_summary();

arm/selftest.c +7 -7

index 28a17f7..8d79b86 100644
@@ -43,13 +43,13 @@ static void check_setup(int argc, char **argv)
 			phys_addr_t memsize = PHYS_END - PHYS_OFFSET;
 			phys_addr_t expected = ((phys_addr_t)val)*1024*1024;
 
-			report("size = %" PRIu64 " MB", memsize == expected,
+			report(memsize == expected, "size = %" PRIu64 " MB",
 							memsize/1024/1024);
 			++nr_tests;
 
 		} else if (strcmp(argv[i], "smp") == 0) {
 
-			report("nr_cpus = %d", nr_cpus == (int)val, nr_cpus);
+			report(nr_cpus == (int)val, "nr_cpus = %d", nr_cpus);
 			++nr_tests;
 		}
 

@@ -291,8 +291,8 @@ static void user_psci_system_off(struct pt_regs *regs, unsigned int esr)
 
 static void check_vectors(void *arg __unused)
 {
-	report("und", check_und());
-	report("svc", check_svc());
+	report(check_und(), "und");
+	report(check_svc(), "svc");
 	if (is_user()) {
 #ifdef __arm__
 		install_exception_handler(EXCPTN_UND, user_psci_system_off);

@@ -338,8 +338,8 @@ static void cpu_report(void *data __unused)
 	uint64_t mpidr = get_mpidr();
 	int cpu = smp_processor_id();
 
-	report("CPU(%3d) mpidr=%010" PRIx64,
-		mpidr_to_cpu(mpidr) == cpu, cpu, mpidr);
+	report(mpidr_to_cpu(mpidr) == cpu, "CPU(%3d) mpidr=%010" PRIx64, cpu,
+	       mpidr);
 }
 
 int main(int argc, char **argv)

@@ -366,7 +366,7 @@ int main(int argc, char **argv)
 
 	} else if (strcmp(argv[1], "smp") == 0) {
 
-		report("PSCI version", psci_check());
+		report(psci_check(), "PSCI version");
 		on_cpus(cpu_report, NULL);
 
 	} else {

arm/spinlock-test.c +1 -1

index d55471b..a63fb41 100644
@@ -67,7 +67,7 @@ static void test_spinlock(void *data __unused)
 
 		lock_ops.unlock(&global_lock);
 	}
-	report("CPU%d: Done - Errors: %d", errors == 0, cpu, errors);
+	report(errors == 0, "CPU%d: Done - Errors: %d", cpu, errors);
 }
 
 int main(int argc, char **argv)

arm/timer.c +8 -8

index f2f6019..68dce46 100644
@@ -222,19 +222,19 @@ static void test_timer(struct timer_info *info)
 	info->write_cval(later);
 	info->write_ctl(ARCH_TIMER_CTL_ENABLE);
 	isb();
-	report("not pending before", !gic_timer_pending(info));
+	report(!gic_timer_pending(info), "not pending before");
 
 	info->write_cval(now - 1);
 	isb();
-	report("interrupt signal pending", gic_timer_pending(info));
+	report(gic_timer_pending(info), "interrupt signal pending");
 
 	/* Disable the timer again and prepare to take interrupts */
 	info->write_ctl(0);
 	set_timer_irq_enabled(info, true);
-	report("interrupt signal no longer pending", !gic_timer_pending(info));
+	report(!gic_timer_pending(info), "interrupt signal no longer pending");
 
-	report("latency within 10 ms", test_cval_10msec(info));
-	report("interrupt received", info->irq_received);
+	report(test_cval_10msec(info), "latency within 10 ms");
+	report(info->irq_received, "interrupt received");
 
 	/* Disable the timer again */
 	info->write_ctl(0);

@@ -248,8 +248,8 @@ static void test_timer(struct timer_info *info)
 	wfi();
 	local_irq_enable();
 	left = info->read_tval();
-	report("interrupt received after TVAL/WFI", info->irq_received);
-	report("timer has expired (%d)", left < 0, left);
+	report(info->irq_received, "interrupt received after TVAL/WFI");
+	report(left < 0, "timer has expired (%d)", left);
 }
 
 static void test_vtimer(void)

@@ -296,7 +296,7 @@ static void test_init(void)
 	if (ptimer_unsupported && !ERRATA(7b6b46311a85)) {
 		report_skip("Skipping ptimer tests. Set ERRATA_7b6b46311a85=y to enable.");
 	} else if (ptimer_unsupported) {
-		report("ptimer: read CNTP_CTL_EL0", false);
+		report(false, "ptimer: read CNTP_CTL_EL0");
 		report_info("ptimer: skipping remaining tests");
 	}
 

lib/libcflat.h +4 -4

index b6635d9..d6d1323 100644
@@ -99,10 +99,10 @@ void report_prefix_pushf(const char *prefix_fmt, ...)
 					__attribute__((format(printf, 1, 2)));
 extern void report_prefix_push(const char *prefix);
 extern void report_prefix_pop(void);
-extern void report(const char *msg_fmt, unsigned pass, ...)
-					__attribute__((format(printf, 1, 3)));
-extern void report_xfail(const char *msg_fmt, bool xfail, unsigned pass, ...)
-					__attribute__((format(printf, 1, 4)));
+extern void report(bool pass, const char *msg_fmt, ...)
+					__attribute__((format(printf, 2, 3)));
+extern void report_xfail(bool xfail, bool pass, const char *msg_fmt, ...)
+					__attribute__((format(printf, 3, 4)));
 extern void report_abort(const char *msg_fmt, ...)
 					__attribute__((format(printf, 1, 2)))
 					__attribute__((noreturn));

lib/report.c +4 -4

index 2a5f549..2255dc3 100644
@@ -104,18 +104,18 @@ static void va_report(const char *msg_fmt,
 	spin_unlock(&lock);
 }
 
-void report(const char *msg_fmt, unsigned pass, ...)
+void report(bool pass, const char *msg_fmt, ...)
 {
 	va_list va;
-	va_start(va, pass);
+	va_start(va, msg_fmt);
 	va_report(msg_fmt, pass, false, false, va);
 	va_end(va);
 }
 
-void report_xfail(const char *msg_fmt, bool xfail, unsigned pass, ...)
+void report_xfail(bool xfail, bool pass, const char *msg_fmt, ...)
 {
 	va_list va;
-	va_start(va, pass);
+	va_start(va, msg_fmt);
 	va_report(msg_fmt, pass, xfail, false, va);
 	va_end(va);
 }

lib/s390x/interrupt.c +3 -2

index 5cade23..1d83154 100644
@@ -46,8 +46,9 @@ uint16_t clear_pgm_int(void)
 void check_pgm_int_code(uint16_t code)
 {
 	mb();
-	report("Program interrupt: expected(%d) == received(%d)",
-	       code == lc->pgm_int_code, code, lc->pgm_int_code);
+	report(code == lc->pgm_int_code,
+	       "Program interrupt: expected(%d) == received(%d)", code,
+	       lc->pgm_int_code);
 }
 
 static void fixup_pgm_int(void)

lib/x86/fault_test.c +1 -1

index b9db399..078dae3 100644
@@ -47,6 +47,6 @@ void test_run(struct fault_test *test)
 {
 	bool passed = fault_test(&(test->arg));
 
-	report("%s", passed, test->name);
+	report(passed, "%s", test->name);
 }
 

powerpc/emulator.c +22 -22

index a7f454e..147878e 100644
@@ -53,7 +53,7 @@ static void test_illegal(void)
 
 	asm volatile (".long 0");
 
-	report("exception", is_invalid == 8); /* illegal instruction */
+	report(is_invalid == 8, "exception"); /* illegal instruction */
 
 	report_prefix_pop();
 }

@@ -66,7 +66,7 @@ static void test_64bit(void)
 
 	asm("mfmsr %[msr]": [msr] "=r" (msr));
 
-	report("detected", msr & 0x8000000000000000UL);
+	report(msr & 0x8000000000000000UL, "detected");
 
 	report_prefix_pop();
 }

@@ -106,13 +106,13 @@ static void test_lswi(void)
 	 * mode, but QEMU does not support it. So in case we do not get an
 	 * exception, this is an expected failure and we run the other tests
 	 */
-	report_xfail("alignment", !alignment, alignment);
+	report_xfail(!alignment, alignment, "alignment");
 	if (alignment) {
 		report_prefix_pop();
 		return;
 	}
 #endif
-	report("partial", regs[0] == 0x01020300 && regs[1] == (uint64_t)-1);
+	report(regs[0] == 0x01020300 && regs[1] == (uint64_t)-1, "partial");
 
 	/* check NB = 0 ==> 32 bytes. */
 	asm volatile ("li r19,-1;"

@@ -142,11 +142,11 @@ static void test_lswi(void)
 		      "r11", "r12", "r13", "r14", "r15", "r16", "r17",
 		      "r18", "r19", "memory");
 
-	report("length", regs[0] == 0x01020304 && regs[1] == 0x05060708 &&
-			 regs[2] == 0x090a0b0c && regs[3] == 0x0d0e0f10 &&
-			 regs[4] == 0x11121314 && regs[5] == 0x15161718 &&
-			 regs[6] == 0x191a1b1c && regs[7] == 0x1d1e1f20 &&
-			 regs[8] == (uint64_t)-1);
+	report(regs[0] == 0x01020304 && regs[1] == 0x05060708 &&
+	       regs[2] == 0x090a0b0c && regs[3] == 0x0d0e0f10 &&
+	       regs[4] == 0x11121314 && regs[5] == 0x15161718 &&
+	       regs[6] == 0x191a1b1c && regs[7] == 0x1d1e1f20 &&
+	       regs[8] == (uint64_t)-1, "length");
 
 	/* check wrap around to r0 */
 	asm volatile ("li r31,-1;"

@@ -162,8 +162,8 @@ static void test_lswi(void)
 		      /* modify two registers from r31, wrap around to r0 */
 		      "r31", "r0", "memory");
 
-	report("wrap around to r0", regs[0] == 0x01020304 &&
-			            regs[1] == 0x05060708);
+	report(regs[0] == 0x01020304 && regs[1] == 0x05060708,
+	       "wrap around to r0");
 
 	/* check wrap around doesn't break RA */
 	asm volatile ("mr r29,r1\n"

@@ -189,7 +189,7 @@ static void test_lswi(void)
 	 * overwrite the register.
 	 * In all the cases, the register must stay untouched
 	 */
-	report("Don't overwrite Ra", regs[2] == (uint64_t)addr);
+	report(regs[2] == (uint64_t)addr, "Don't overwrite Ra");
 
 	report_prefix_pop();
 }

@@ -250,13 +250,13 @@ static void test_lswx(void)
 	 * mode, but QEMU does not support it. So in case we do not get an
 	 * exception, this is an expected failure and we run the other tests
 	 */
-	report_xfail("alignment", !alignment, alignment);
+	report_xfail(!alignment, alignment, "alignment");
 	if (alignment) {
 		report_prefix_pop();
 		return;
 	}
 #endif
-	report("partial", regs[0] == 0x01020300 && regs[1] == (uint64_t)-1);
+	report(regs[0] == 0x01020300 && regs[1] == (uint64_t)-1, "partial");
 
 	/* check an old know bug: the number of bytes is used as
 	 * the number of registers, so try 32 bytes.

@@ -290,11 +290,11 @@ static void test_lswx(void)
 		      "xer", "r11", "r12", "r13", "r14", "r15", "r16", "r17",
 		      "r18", "r19", "memory");
 
-	report("length", regs[0] == 0x01020304 && regs[1] == 0x05060708 &&
-			 regs[2] == 0x090a0b0c && regs[3] == 0x0d0e0f10 &&
-			 regs[4] == 0x11121314 && regs[5] == 0x15161718 &&
-			 regs[6] == 0x191a1b1c && regs[7] == 0x1d1e1f20 &&
-			 regs[8] == (uint64_t)-1);
+	report(regs[0] == 0x01020304 && regs[1] == 0x05060708 &&
+	       regs[2] == 0x090a0b0c && regs[3] == 0x0d0e0f10 &&
+	       regs[4] == 0x11121314 && regs[5] == 0x15161718 &&
+	       regs[6] == 0x191a1b1c && regs[7] == 0x1d1e1f20 &&
+	       regs[8] == (uint64_t)-1, "length");
 
 	/* check wrap around to r0 */
 

@@ -312,8 +312,8 @@ static void test_lswx(void)
 		      /* modify two registers from r31, wrap around to r0 */
 		      "xer", "r31", "r0", "memory");
 
-	report("wrap around to r0", regs[0] == 0x01020304 &&
-			            regs[1] == 0x05060708);
+	report(regs[0] == 0x01020304 && regs[1] == 0x05060708,
+	       "wrap around to r0");
 
 	/* check wrap around to r0 over RB doesn't break RB */
 

@@ -342,7 +342,7 @@ static void test_lswx(void)
 	 * overwrite the register.
 	 * In all the cases, the register must stay untouched
 	 */
-	report("Don't overwrite Rb", regs[1] == (uint64_t)addr);
+	report(regs[1] == (uint64_t)addr, "Don't overwrite Rb");
 
 	report_prefix_pop();
 }

powerpc/rtas.c +16 -16

index 5d43f33..9f5ec4b 100644
@@ -45,21 +45,21 @@ static void check_get_time_of_day(unsigned long start)
 	unsigned long t1, t2, count;
 
 	ret = rtas_token("get-time-of-day", &token);
-	report("token available", ret == 0);
+	report(ret == 0, "token available");
 	if (ret)
 		return;
 
 	ret = rtas_call(token, 0, 8, now);
-	report("execution", ret == 0);
+	report(ret == 0, "execution");
 
-	report("second",  now[5] >= 0 && now[5] <= 59);
-	report("minute", now[4] >= 0 && now[4] <= 59);
-	report("hour", now[3] >= 0 && now[3] <= 23);
-	report("day", now[2] >= 1 && now[2] <= 31);
-	report("month", now[1] >= 1 && now[1] <= 12);
-	report("year", now[0] >= 1970);
-	report("accuracy (< 3s)", mktime(now[0], now[1], now[2],
-					 now[3], now[4], now[5]) - start < 3);
+	report(now[5] >= 0 && now[5] <= 59, "second");
+	report(now[4] >= 0 && now[4] <= 59, "minute");
+	report(now[3] >= 0 && now[3] <= 23, "hour");
+	report(now[2] >= 1 && now[2] <= 31, "day");
+	report(now[1] >= 1 && now[1] <= 12, "month");
+	report(now[0] >= 1970, "year");
+	report(mktime(now[0], now[1], now[2], now[3], now[4], now[5]) - start < 3,
+	       "accuracy (< 3s)");
 
 	ret = rtas_call(token, 0, 8, now);
 	t1 = mktime(now[0], now[1], now[2], now[3], now[4], now[5]);

@@ -69,7 +69,7 @@ static void check_get_time_of_day(unsigned long start)
 		t2 = mktime(now[0], now[1], now[2], now[3], now[4], now[5]);
 		count++;
 	} while (t1 + DELAY > t2 && count < MAX_LOOP);
-	report("running", t1 + DELAY <= t2);
+	report(t1 + DELAY <= t2, "running");
 }
 
 static void check_set_time_of_day(void)

@@ -80,24 +80,24 @@ static void check_set_time_of_day(void)
 	unsigned long t1, t2, count;
 
 	ret = rtas_token("set-time-of-day", &stod_token);
-	report("token available", ret == 0);
+	report(ret == 0, "token available");
 	if (ret)
 		return;
 
 	/* 23:59:59 28/2/2000 */
 
 	ret = rtas_call(stod_token, 7, 1, NULL, 2000, 2, 28, 23, 59, 59);
-	report("execution", ret == 0);
+	report(ret == 0, "execution");
 
 	/* check it has worked */
 	ret = rtas_token("get-time-of-day", &gtod_token);
 	assert(ret == 0);
 	ret = rtas_call(gtod_token, 0, 8, date);
-	report("re-read", ret == 0);
+	report(ret == 0, "re-read");
 	t1 = mktime(2000, 2, 28, 23, 59, 59);
 	t2 = mktime(date[0], date[1], date[2],
 		    date[3], date[4], date[5]);
-	report("result", t2 - t1 < 2);
+	report(t2 - t1 < 2, "result");
 
 	/* check it is running */
 	count = 0;

@@ -107,7 +107,7 @@ static void check_set_time_of_day(void)
 			    date[3], date[4], date[5]);
 		count++;
 	} while (t1 + DELAY > t2 && count < MAX_LOOP);
-	report("running", t1 + DELAY <= t2);
+	report(t1 + DELAY <= t2, "running");
 }
 
 int main(int argc, char **argv)

powerpc/selftest.c +2 -2

index 4e29fd6..7acff71 100644
@@ -28,13 +28,13 @@ static void check_setup(int argc, char **argv)
 			phys_addr_t memsize = PHYSICAL_END - PHYSICAL_START;
 			phys_addr_t expected = ((phys_addr_t)val)*1024*1024;
 
-			report("size = %" PRIu64 " MB", memsize == expected,
+			report(memsize == expected, "size = %" PRIu64 " MB",
 							memsize/1024/1024);
 			++nr_tests;
 
 		} else if (strcmp(argv[i], "smp") == 0) {
 
-			report("nr_cpus = %d", nr_cpus == (int)val, nr_cpus);
+			report(nr_cpus == (int)val, "nr_cpus = %d", nr_cpus);
 			++nr_tests;
 		}
 

powerpc/spapr_hcall.c +15 -15

index 524d896..823a574 100644
@@ -39,18 +39,18 @@ static void test_h_set_sprg0(int argc, char **argv)
 
 	rc = hcall(H_SET_SPRG0, 0xcafebabedeadbeefULL);
 	sprg0 = mfspr(SPR_SPRG0);
-	report("sprg0 = 0xcafebabedeadbeef",
-		rc == H_SUCCESS && sprg0 == 0xcafebabedeadbeefULL);
+	report(rc == H_SUCCESS && sprg0 == 0xcafebabedeadbeefULL,
+	       "sprg0 = 0xcafebabedeadbeef");
 
 	rc = hcall(H_SET_SPRG0, 0xaaaaaaaa55555555ULL);
 	sprg0 = mfspr(SPR_SPRG0);
-	report("sprg0 = 0xaaaaaaaa55555555",
-		rc == H_SUCCESS && sprg0 == 0xaaaaaaaa55555555ULL);
+	report(rc == H_SUCCESS && sprg0 == 0xaaaaaaaa55555555ULL,
+	       "sprg0 = 0xaaaaaaaa55555555");
 
 	rc = hcall(H_SET_SPRG0, sprg0_orig);
 	sprg0 = mfspr(SPR_SPRG0);
-	report("sprg0 = %#" PRIx64,
-		rc == H_SUCCESS && sprg0 == sprg0_orig, sprg0_orig);
+	report(rc == H_SUCCESS && sprg0 == sprg0_orig, "sprg0 = %#" PRIx64,
+	       sprg0_orig);
 }
 
 /**

@@ -72,23 +72,23 @@ static void test_h_page_init(int argc, char **argv)
 
 	memset(dst, 0xaa, PAGE_SIZE);
 	rc = hcall(H_PAGE_INIT, H_ZERO_PAGE, dst, src);
-	report("h_zero_page", rc == H_SUCCESS && *(uint64_t*)dst == 0);
+	report(rc == H_SUCCESS && *(uint64_t *)dst == 0, "h_zero_page");
 
 	*(uint64_t*)src = 0xbeefc0dedeadcafeULL;
 	rc = hcall(H_PAGE_INIT, H_COPY_PAGE, dst, src);
-	report("h_copy_page",
-		rc == H_SUCCESS && *(uint64_t*)dst == 0xbeefc0dedeadcafeULL);
+	report(rc == H_SUCCESS && *(uint64_t *)dst == 0xbeefc0dedeadcafeULL,
+	       "h_copy_page");
 
 	*(uint64_t*)src = 0x9abcdef012345678ULL;
 	rc = hcall(H_PAGE_INIT, H_COPY_PAGE|H_ZERO_PAGE, dst, src);
-	report("h_copy_page+h_zero_page",
-		rc == H_SUCCESS &&  *(uint64_t*)dst == 0x9abcdef012345678ULL);
+	report(rc == H_SUCCESS && *(uint64_t *)dst == 0x9abcdef012345678ULL,
+	       "h_copy_page+h_zero_page");
 
 	rc = hcall(H_PAGE_INIT, H_ZERO_PAGE, dst + 0x123, src);
-	report("h_zero_page unaligned dst", rc == H_PARAMETER);
+	report(rc == H_PARAMETER, "h_zero_page unaligned dst");
 
 	rc = hcall(H_PAGE_INIT, H_COPY_PAGE, dst, src + 0x123);
-	report("h_copy_page unaligned src", rc == H_PARAMETER);
+	report(rc == H_PARAMETER, "h_copy_page unaligned src");
 }
 
 static int h_random(uint64_t *val)

@@ -122,7 +122,7 @@ static void test_h_random(int argc, char **argv)
 		report_skip("h-call is not available");
 		return;
 	}
-	report("h-call can be used successfully", rc == H_SUCCESS);
+	report(rc == H_SUCCESS, "h-call can be used successfully");
 
 	val0 = 0ULL;
 	val1 = ~0ULL;

@@ -136,7 +136,7 @@ static void test_h_random(int argc, char **argv)
 		val1 &= rval;
 	} while (i-- > 0 && (val0 != ~0ULL || val1 != 0ULL));
 
-	report("no stuck bits", rc == H_SUCCESS && val0 == ~0ULL && val1 == 0);
+	report(rc == H_SUCCESS && val0 == ~0ULL && val1 == 0, "no stuck bits");
 }
 
 struct {

powerpc/sprs.c +3 -2

index 3c2d98c..d3c8780 100644
@@ -299,8 +299,9 @@ int main(int argc, char **argv)
 	puts("Checking SPRs...\n");
 	for (i = 0; i < 1024; i++) {
 		if (before[i] != 0 || after[i] != 0)
-			report("SPR %d:\t%#018lx <==> %#018lx",
-				before[i] == after[i], i, before[i], after[i]);
+			report(before[i] == after[i],
+			       "SPR %d:\t%#018lx <==> %#018lx", i, before[i],
+			       after[i]);
 	}
 
 	return report_summary();

powerpc/tm.c +3 -3

index c588985..65cacdf 100644
@@ -127,7 +127,7 @@ static void test_h_cede_tm(int argc, char **argv)
 		mdelay(5);
 	}
 
-	report("H_CEDE TM", i == 500);
+	report(i == 500, "H_CEDE TM");
 }
 
 struct {

@@ -150,8 +150,8 @@ int main(int argc, char **argv)
 		report_skip("TM is not available");
 		goto done;
 	}
-	report("TM available in all 'ibm,pa-features' properties",
-	       cpus_with_tm == nr_cpus);
+	report(cpus_with_tm == nr_cpus,
+	       "TM available in all 'ibm,pa-features' properties");
 
 	all = argc == 1 || !strcmp(argv[1], "all");
 

s390x/cpumodel.c +1 -1

index 3811ee1..5d232c6 100644
@@ -47,7 +47,7 @@ int main(void)
 	report_prefix_push("dependency");
 	for (i = 0; i < ARRAY_SIZE(dep); i++) {
 		if (test_facility(dep[i][0])) {
-			report("%d implies %d", test_facility(dep[i][1]),
+			report(test_facility(dep[i][1]), "%d implies %d",
 				dep[i][0], dep[i][1]);
 		} else {
 			report_skip("facility %d not present", dep[i][0]);

s390x/diag288.c +1 -1

index b4934bf..e2ecdc8 100644
@@ -101,7 +101,7 @@ static void test_bite(void)
 		     "0:	nop\n"
 		     "		j	0b\n"
 		     "1:");
-	report("restart", true);
+	report(true, "restart");
 }
 
 int main(void)

s390x/diag308.c +2 -2

index 6b4ffa6..7fc4abd 100644
@@ -29,12 +29,12 @@ static void test_priv(void)
 extern int diag308_load_reset(u64);
 static void test_subcode0(void)
 {
-	report("load modified clear done", diag308_load_reset(0));
+	report(diag308_load_reset(0), "load modified clear done");
 }
 
 static void test_subcode1(void)
 {
-	report("load normal reset done", diag308_load_reset(1));
+	report(diag308_load_reset(1), "load normal reset done");
 }
 
 /* Expect a specification exception when using an uneven register */

s390x/emulator.c +9 -9

index bce7b79..1ee0df5 100644
@@ -28,10 +28,10 @@ static inline void __test_spm_ipm(uint8_t cc, uint8_t key)
 		      "ipm %0\n"
 		      : "+r"(out) : "r"(in) : "cc");
 
-	report("bit 32 and 33 set to zero", !(out & 0xc0000000UL));
-	report("bit 0-31, 40-63 unchanged",
-		(out & ~0xff000000ULL) == ~0xff000000ULL);
-	report("cc and key applied", !((in ^ out) & 0x3f000000UL));
+	report(!(out & 0xc0000000UL), "bit 32 and 33 set to zero");
+	report((out & ~0xff000000ULL) == ~0xff000000ULL,
+	       "bit 0-31, 40-63 unchanged");
+	report(!((in ^ out) & 0x3f000000UL), "cc and key applied");
 
 	report_prefix_pop();
 }

@@ -165,7 +165,7 @@ static inline void __test_basic_cpacf_opcode(unsigned int opcode)
 		report_skip("not available");
 		return;
 	}
-	report("query indicated in query", cpacf_query_func(opcode, 0));
+	report(cpacf_query_func(opcode, 0), "query indicated in query");
 
 	switch (opcode) {
 	case CPACF_KMCTR:

@@ -272,8 +272,8 @@ static void test_dxc(void)
 		     : : "r"(0) : "memory");
 	check_pgm_int_code(PGM_INT_CODE_DATA);
 
-	report("dxc in LC", lc->dxc_vxc == 0xff);
-	report("dxc in FPC", get_fpc_dxc() == 0xff);
+	report(lc->dxc_vxc == 0xff, "dxc in LC");
+	report(get_fpc_dxc() == 0xff, "dxc in FPC");
 	report_prefix_pop();
 
 	/* DXC (0xff) is to be stored in LC only on a trap (CRT) without AFP */

@@ -289,8 +289,8 @@ static void test_dxc(void)
 	afp_enable();
 	check_pgm_int_code(PGM_INT_CODE_DATA);
 
-	report("dxc in LC", lc->dxc_vxc == 0xff);
-	report("dxc not in FPC", get_fpc_dxc() == 0);
+	report(lc->dxc_vxc == 0xff, "dxc in LC");
+	report(get_fpc_dxc() == 0, "dxc not in FPC");
 	report_prefix_pop();
 }
 

s390x/gs.c +1 -1

index 26f22e8..f685aa9 100644
@@ -121,7 +121,7 @@ static void test_load(void)
 
 	guarded = 0;
 	v = load_guarded(&gs_area);
-	report("load guarded %ld", guarded, v);
+	report(guarded, "load guarded %ld", v);
 	guarded = 0;
 }
 

s390x/intercept.c +8 -8

index 404b4c6..3696e33 100644
@@ -33,7 +33,7 @@ static void test_stpx(void)
 		" spx	%0\n"
 		: "+Q"(old_prefix), "+Q"(tst_prefix)
 		: "Q"(new_prefix));
-	report("store prefix", old_prefix == 0 && tst_prefix == new_prefix);
+	report(old_prefix == 0 && tst_prefix == new_prefix, "store prefix");
 
 	expect_pgm_int();
 	low_prot_enable();

@@ -71,7 +71,7 @@ static void test_spx(void)
 		: "+Q"(old_prefix)
 		: "Q"(new_prefix)
 		: "memory");
-	report("stfl to new prefix", pagebuf[GEN_LC_STFL] != 0);
+	report(pagebuf[GEN_LC_STFL] != 0, "stfl to new prefix");
 
 	expect_pgm_int();
 	asm volatile(" spx 0(%0) " : : "r"(1));

@@ -88,7 +88,7 @@ static void test_stap(void)
 	uint16_t cpuid = 0xffff;
 
 	asm volatile ("stap %0\n" : "+Q"(cpuid));
-	report("get cpu address", cpuid != 0xffff);
+	report(cpuid != 0xffff, "get cpu address");
 
 	expect_pgm_int();
 	low_prot_enable();

@@ -111,9 +111,9 @@ static void test_stidp(void)
 	struct cpuid id = {};
 
 	asm volatile ("stidp %0\n" : "+Q"(id));
-	report("type set", id.type);
-	report("version valid", !id.version || id.version == 0xff);
-	report("reserved bits not set", !id.reserved);
+	report(id.type, "type set");
+	report(!id.version || id.version == 0xff, "version valid");
+	report(!id.reserved, "reserved bits not set");
 
 	expect_pgm_int();
 	low_prot_enable();

@@ -145,8 +145,8 @@ static void test_testblock(void)
 		: "=d" (cc)
 		: "a"(pagebuf + 0x123)
 		: "memory", "0", "cc");
-	report("page cleared",
-	       cc == 0 && pagebuf[0] == 0 &&  pagebuf[PAGE_SIZE - 1] == 0);
+	report(cc == 0 && pagebuf[0] == 0 && pagebuf[PAGE_SIZE - 1] == 0,
+	       "page cleared");
 
 	expect_pgm_int();
 	low_prot_enable();

s390x/pfmf.c +5 -4

index e81f7c5..ac57fe4 100644
@@ -45,7 +45,7 @@ static void test_4k_key(void)
 	pfmf(r1.val, pagebuf);
 	skey.val = get_storage_key(pagebuf);
 	skey.val &= SKEY_ACC | SKEY_FP;
-	report("set storage keys", skey.val == 0x30);
+	report(skey.val == 0x30, "set storage keys");
 out:
 	report_prefix_pop();
 }

@@ -75,7 +75,7 @@ static void test_1m_key(void)
 			break;
 		}
 	}
-	report("set storage keys", rp);
+	report(rp, "set storage keys");
 out:
 	report_prefix_pop();
 }

@@ -91,7 +91,8 @@ static void test_4k_clear(void)
 	report_prefix_push("4K");
 	memset(pagebuf, 42, PAGE_SIZE);
 	pfmf(r1.val, pagebuf);
-	report("clear memory", !memcmp(pagebuf, pagebuf + PAGE_SIZE, PAGE_SIZE));
+	report(!memcmp(pagebuf, pagebuf + PAGE_SIZE, PAGE_SIZE),
+	       "clear memory");
 	report_prefix_pop();
 }
 

@@ -110,7 +111,7 @@ static void test_1m_clear(void)
 	pfmf(r1.val, pagebuf);
 	for (i = 0; i < PAGE_SIZE * 256; i++)
 		sum |= pagebuf[i];
-	report("clear memory", !sum);
+	report(!sum, "clear memory");
 	report_prefix_pop();
 }
 

s390x/selftest.c +12 -11

index f4acdc4..4c16646 100644
@@ -26,7 +26,7 @@ static void test_fp(void)
 		"	std %1, %0\n"
 		: "=m" (c) : "f" (a), "m" (b));
 
-	report("3.0/2.0 == 1.5", c == 1.5);
+	report(c == 1.5, "3.0/2.0 == 1.5");
 }
 
 static void test_pgm_int(void)

@@ -49,11 +49,12 @@ static void test_malloc(void)
 	*tmp2 = 123456789;
 	mb();
 
-	report("malloc: got vaddr", (uintptr_t)tmp & 0xf000000000000000ul);
-	report("malloc: access works", *tmp == 123456789);
-	report("malloc: got 2nd vaddr", (uintptr_t)tmp2 & 0xf000000000000000ul);
-	report("malloc: access works", (*tmp2 == 123456789));
-	report("malloc: addresses differ", tmp != tmp2);
+	report((uintptr_t)tmp & 0xf000000000000000ul, "malloc: got vaddr");
+	report(*tmp == 123456789, "malloc: access works");
+	report((uintptr_t)tmp2 & 0xf000000000000000ul,
+	       "malloc: got 2nd vaddr");
+	report((*tmp2 == 123456789), "malloc: access works");
+	report(tmp != tmp2, "malloc: addresses differ");
 
 	expect_pgm_int();
 	configure_dat(0);

@@ -69,11 +70,11 @@ int main(int argc, char**argv)
 {
 	report_prefix_push("selftest");
 
-	report("true", true);
-	report("argc == 3", argc == 3);
-	report("argv[0] == PROGNAME", !strcmp(argv[0], "s390x/selftest.elf"));
-	report("argv[1] == test", !strcmp(argv[1], "test"));
-	report("argv[2] == 123", !strcmp(argv[2], "123"));
+	report(true, "true");
+	report(argc == 3, "argc == 3");
+	report(!strcmp(argv[0], "s390x/selftest.elf"), "argv[0] == PROGNAME");
+	report(!strcmp(argv[1], "test"), "argv[1] == test");
+	report(!strcmp(argv[2], "123"), "argv[2] == 123");
 
 	setup_vm();
 

s390x/skey.c +5 -6

index 5020e99..86d15e2 100644
@@ -35,8 +35,7 @@ static void test_set_mb(void)
 
 	ret1.val = get_storage_key(end - PAGE_SIZE) & (SKEY_ACC | SKEY_FP);
 	ret2.val = get_storage_key(end - PAGE_SIZE * 2) & (SKEY_ACC | SKEY_FP);
-	report("multi block",
-	       ret1.val == ret2.val && ret1.val == skey.val);
+	report(ret1.val == ret2.val && ret1.val == skey.val, "multi block");
 }
 
 static void test_chg(void)

@@ -48,7 +47,7 @@ static void test_chg(void)
 	skey1.val = get_storage_key(pagebuf);
 	pagebuf[0] = 3;
 	skey2.val = get_storage_key(pagebuf);
-	report("chg bit test", !skey1.str.ch && skey2.str.ch);
+	report(!skey1.str.ch && skey2.str.ch, "chg bit test");
 }
 
 static void test_set(void)

@@ -64,8 +63,8 @@ static void test_set(void)
 	 * CH are set by the machine for memory references and changes
 	 * and hence might change between a set and a get.
 	 */
-	report("set key test",
-	       skey.str.acc == ret.str.acc && skey.str.fp == ret.str.fp);
+	report(skey.str.acc == ret.str.acc && skey.str.fp == ret.str.fp,
+	       "set key test");
 }
 
 /* Returns true if we are running under z/VM 6.x */

@@ -106,7 +105,7 @@ static void test_priv(void)
 	report_prefix_pop();
 
 	skey.val = get_storage_key(pagebuf);
-	report("skey did not change on exception", skey.str.acc != 3);
+	report(skey.str.acc != 3, "skey did not change on exception");
 
 	report_prefix_push("iske");
 	if (is_zvm6) {

s390x/skrf.c +5 -5

index e77ff35..9cae589 100644
@@ -21,11 +21,11 @@ static uint8_t pagebuf[PAGE_SIZE * 2] __attribute__((aligned(PAGE_SIZE * 2)));
 static void test_facilities(void)
 {
 	report_prefix_push("facilities");
-	report("!10", !test_facility(10));
-	report("!14", !test_facility(14));
-	report("!66", !test_facility(66));
-	report("!145", !test_facility(145));
-	report("!149", !test_facility(140));
+	report(!test_facility(10), "!10");
+	report(!test_facility(14), "!14");
+	report(!test_facility(66), "!66");
+	report(!test_facility(145), "!145");
+	report(!test_facility(140), "!149");
 	report_prefix_pop();
 }
 

s390x/smp.c +19 -18

index 8782cfc..ab7e46c 100644
@@ -44,7 +44,7 @@ static void test_start(void)
 	while (!testflag) {
 		mb();
 	}
-	report("start", 1);
+	report(1, "start");
 }
 
 static void test_stop(void)

@@ -56,7 +56,7 @@ static void test_stop(void)
 	 * implementation
 	 */
 	while (!smp_cpu_stopped(1)) {}
-	report("stop", 1);
+	report(1, "stop");
 }
 
 static void test_stop_store_status(void)

@@ -69,8 +69,8 @@ static void test_stop_store_status(void)
 	lc->grs_sa[15] = 0;
 	smp_cpu_stop_store_status(1);
 	mb();
-	report("prefix", lc->prefix_sa == (uint32_t)(uintptr_t)cpu->lowcore);
-	report("stack", lc->grs_sa[15]);
+	report(lc->prefix_sa == (uint32_t)(uintptr_t)cpu->lowcore, "prefix");
+	report(lc->grs_sa[15], "stack");
 	report_prefix_pop();
 }
 

@@ -85,8 +85,9 @@ static void test_store_status(void)
 	report_prefix_push("running");
 	smp_cpu_restart(1);
 	sigp(1, SIGP_STORE_STATUS_AT_ADDRESS, (uintptr_t)status, &r);
-	report("incorrect state", r == SIGP_STATUS_INCORRECT_STATE);
-	report("status not written", !memcmp(status, (void*)status + PAGE_SIZE, PAGE_SIZE));
+	report(r == SIGP_STATUS_INCORRECT_STATE, "incorrect state");
+	report(!memcmp(status, (void *)status + PAGE_SIZE, PAGE_SIZE),
+	       "status not written");
 	report_prefix_pop();
 
 	memset(status, 0, PAGE_SIZE);

@@ -94,7 +95,7 @@ static void test_store_status(void)
 	smp_cpu_stop(1);
 	sigp(1, SIGP_STORE_STATUS_AT_ADDRESS, (uintptr_t)status, NULL);
 	while (!status->prefix) { mb(); }
-	report("status written", 1);
+	report(1, "status written");
 	free_pages(status, PAGE_SIZE * 2);
 	report_prefix_pop();
 

@@ -113,7 +114,7 @@ static void ecall(void)
 	load_psw_mask(mask);
 	testflag = 1;
 	while (lc->ext_int_code != 0x1202) { mb(); }
-	report("ecall", 1);
+	report(1, "ecall");
 	testflag= 1;
 }
 

@@ -148,7 +149,7 @@ static void emcall(void)
 	load_psw_mask(mask);
 	testflag= 1;
 	while (lc->ext_int_code != 0x1201) { mb(); }
-	report("ecall", 1);
+	report(1, "ecall");
 	testflag = 1;
 }
 

@@ -186,19 +187,19 @@ static void test_reset_initial(void)
 	sigp(1, SIGP_STORE_STATUS_AT_ADDRESS, (uintptr_t)status, NULL);
 
 	report_prefix_push("clear");
-	report("psw", !status->psw.mask && !status->psw.addr);
-	report("prefix", !status->prefix);
-	report("fpc", !status->fpc);
-	report("cpu timer", !status->cputm);
-	report("todpr", !status->todpr);
+	report(!status->psw.mask && !status->psw.addr, "psw");
+	report(!status->prefix, "prefix");
+	report(!status->fpc, "fpc");
+	report(!status->cputm, "cpu timer");
+	report(!status->todpr, "todpr");
 	report_prefix_pop();
 
 	report_prefix_push("initialized");
-	report("cr0 == 0xE0", status->crs[0] == 0xE0UL);
-	report("cr14 == 0xC2000000", status->crs[14] == 0xC2000000UL);
+	report(status->crs[0] == 0xE0UL, "cr0 == 0xE0");
+	report(status->crs[14] == 0xC2000000UL, "cr14 == 0xC2000000");
 	report_prefix_pop();
 
-	report("cpu stopped", smp_cpu_stopped(1));
+	report(smp_cpu_stopped(1), "cpu stopped");
 	free_pages(status, PAGE_SIZE);
 	report_prefix_pop();
 }

@@ -214,7 +215,7 @@ static void test_reset(void)
 	smp_cpu_setup(1, psw);
 
 	sigp_retry(1, SIGP_CPU_RESET, 0, NULL);
-	report("cpu stopped", smp_cpu_stopped(1));
+	report(smp_cpu_stopped(1), "cpu stopped");
 	report_prefix_pop();
 }
 

s390x/sthyi.c +23 -18

index 04a7b4f..68c57cb 100644
@@ -78,21 +78,21 @@ static void test_function_code(uint64_t addr)
 	uint64_t urc = 0;
 	int cc = sthyi((uint64_t)pagebuf, 42, &urc, 0, 2);
 
-	report("Illegal fcode", cc == 3 && urc == CODE_UNSUPP);
+	report(cc == 3 && urc == CODE_UNSUPP, "Illegal fcode");
 }
 
 static void test_fcode0_hdr(struct sthyi_hdr_sctn *hdr)
 {
 	report_prefix_push("Header");
 
-	report("length", hdr->INFHDLN >= sizeof(*hdr) && !(hdr->INFHDLN % 8));
-	report("Machine sctn length", (hdr->INFMLEN >= sizeof(struct sthyi_mach_sctn)
-				       && !(hdr->INFMLEN % 8)));
-	report("Partition section length", (hdr->INFPLEN >= sizeof(struct sthyi_par_sctn)
-					    && !(hdr->INFPLEN % 8)));
+	report(hdr->INFHDLN >= sizeof(*hdr) && !(hdr->INFHDLN % 8), "length");
+	report((hdr->INFMLEN >= sizeof(struct sthyi_mach_sctn) && !(hdr->INFMLEN % 8)),
+	       "Machine sctn length");
+	report((hdr->INFPLEN >= sizeof(struct sthyi_par_sctn) && !(hdr->INFPLEN % 8)),
+	       "Partition section length");
 
-	report("Machine offset", hdr->INFMOFF >= hdr->INFHDLN);
-	report("Partition offset", hdr->INFPOFF >= hdr->INFHDLN);
+	report(hdr->INFMOFF >= hdr->INFHDLN, "Machine offset");
+	report(hdr->INFPOFF >= hdr->INFHDLN, "Partition offset");
 	report_prefix_pop();
 }
 

@@ -102,18 +102,22 @@ static void test_fcode0_mach(struct sthyi_mach_sctn *mach)
 
 	report_prefix_push("Machine");
 	if (mach->INFMVAL1 & MACH_ID_VLD) {
-		report("type", memcmp(mach->INFMTYPE, null_buf, sizeof(mach->INFMTYPE)));
-		report("manufacturer", memcmp(mach->INFMMANU, null_buf, sizeof(mach->INFMMANU)));
-		report("sequence", memcmp(mach->INFMSEQ, null_buf, sizeof(mach->INFMSEQ)));
-		report("plant", memcmp(mach->INFMPMAN, null_buf, sizeof(mach->INFMPMAN)));
+		report(memcmp(mach->INFMTYPE, null_buf, sizeof(mach->INFMTYPE)),
+		       "type");
+		report(memcmp(mach->INFMMANU, null_buf, sizeof(mach->INFMMANU)),
+		       "manufacturer");
+		report(memcmp(mach->INFMSEQ, null_buf, sizeof(mach->INFMSEQ)),
+		       "sequence");
+		report(memcmp(mach->INFMPMAN, null_buf, sizeof(mach->INFMPMAN)),
+		       "plant");
 	}
 
 	if (mach->INFMVAL1 & MACH_NAME_VLD)
-		report("name", memcmp(mach->INFMNAME, null_buf,
-				      sizeof(mach->INFMNAME)));
+		report(memcmp(mach->INFMNAME, null_buf, sizeof(mach->INFMNAME)),
+		       "name");
 
 	if (mach->INFMVAL1 & MACH_CNT_VLD)
-		report("core counts", sum);
+		report(sum, "core counts");
 	report_prefix_pop();
 }
 

@@ -123,11 +127,12 @@ static void test_fcode0_par(struct sthyi_par_sctn *par)
 
 	report_prefix_push("Partition");
 	if (par->INFPVAL1 & PART_CNT_VLD)
-		report("core counts", sum);
+		report(sum, "core counts");
 
 	if (par->INFPVAL1 & PART_STSI_SUC) {
-		report("number", par->INFPPNUM);
-		report("name", memcmp(par->INFPPNAM, null_buf, sizeof(par->INFPPNAM)));
+		report(par->INFPPNUM, "number");
+		report(memcmp(par->INFPPNAM, null_buf, sizeof(par->INFPPNAM)),
+		       "name");
 	}
 	report_prefix_pop();
 }

s390x/stsi.c +4 -4

index c5bd0a2..e9206bc 100644
@@ -70,10 +70,10 @@ static inline unsigned long stsi_get_fc(void *addr)
 
 static void test_fc(void)
 {
-	report("invalid fc",  stsi(pagebuf, 7, 0, 0) == 3);
-	report("invalid selector 1", stsi(pagebuf, 1, 0, 1) == 3);
-	report("invalid selector 2", stsi(pagebuf, 1, 1, 0) == 3);
-	report("query fc >= 2",  stsi_get_fc(pagebuf) >= 2);
+	report(stsi(pagebuf, 7, 0, 0) == 3, "invalid fc");
+	report(stsi(pagebuf, 1, 0, 1) == 3, "invalid selector 1");
+	report(stsi(pagebuf, 1, 1, 0) == 3, "invalid selector 2");
+	report(stsi_get_fc(pagebuf) >= 2, "query fc >= 2");
 }
 
 int main(void)

s390x/vector.c +3 -3

index d40f647..0159ba1 100644
@@ -49,7 +49,7 @@ static void test_add(void)
 		     : [v3]  "=Q" (prm.c)
 		     : [v1]  "Q" (prm.a), [v2]  "Q" (prm.b)
 		     : "v0", "v1", "v2", "memory");
-	report("adding 21", prm.c == 42);
+	report(prm.c == 42, "adding 21");
 }
 
 /* z14 vector extension test */

@@ -75,7 +75,7 @@ static void test_ext1_nand(void)
 		     : [v3]  "=Q" (prm.c)
 		     : [v1]  "Q" (prm.a), [v2]  "Q" (prm.b)
 		     : "v0", "v1", "v2", "memory");
-	report("nand ff", !prm.c);
+	report(!prm.c, "nand ff");
 }
 
 /* z14 bcd extension test */

@@ -102,7 +102,7 @@ static void test_bcd_add(void)
 		     : [v3]  "=Q" (prm.c)
 		     : [v1]  "Q" (prm.a), [v2]  "Q" (prm.b)
 		     : "v0", "v1", "v2", "memory");
-	report("bcd add 21", prm.c == 0x42c);
+	report(prm.c == 0x42c, "bcd add 21");
 }
 
 static void init(void)

x86/apic.c +76 -72

index eb785c4..2aacad6 100644
@@ -16,7 +16,7 @@ static void test_lapic_existence(void)
 
     version = (u8)apic_read(APIC_LVR);
     printf("apic version: %x\n", version);
-    report("apic existence", version >= 0x10 && version <= 0x15);
+    report(version >= 0x10 && version <= 0x15, "apic existence");
 }
 
 #define TSC_DEADLINE_TIMER_VECTOR 0xef

@@ -37,8 +37,8 @@ static void __test_tsc_deadline_timer(void)
 
     wrmsr(MSR_IA32_TSCDEADLINE, rdmsr(MSR_IA32_TSC));
     asm volatile ("nop");
-    report("tsc deadline timer", tdt_count == 1);
-    report("tsc deadline timer clearing", rdmsr(MSR_IA32_TSCDEADLINE) == 0);
+    report(tdt_count == 1, "tsc deadline timer");
+    report(rdmsr(MSR_IA32_TSCDEADLINE) == 0, "tsc deadline timer clearing");
 }
 
 static int enable_tsc_deadline_timer(void)

@@ -82,22 +82,22 @@ static void test_enable_x2apic(void)
         printf("x2apic enabled\n");
 
         apicbase = orig_apicbase & ~(APIC_EN | APIC_EXTD);
-        report("x2apic enabled to invalid state",
-               test_write_apicbase_exception(apicbase | APIC_EXTD));
-        report("x2apic enabled to apic enabled",
-               test_write_apicbase_exception(apicbase | APIC_EN));
-
-        report("x2apic enabled to disabled state",
-               !test_write_apicbase_exception(apicbase | 0));
-        report("disabled to invalid state",
-               test_write_apicbase_exception(apicbase | APIC_EXTD));
-        report("disabled to x2apic enabled",
-               test_write_apicbase_exception(apicbase | APIC_EN | APIC_EXTD));
-
-        report("apic disabled to apic enabled",
-               !test_write_apicbase_exception(apicbase | APIC_EN));
-        report("apic enabled to invalid state",
-               test_write_apicbase_exception(apicbase | APIC_EXTD));
+        report(test_write_apicbase_exception(apicbase | APIC_EXTD),
+               "x2apic enabled to invalid state");
+        report(test_write_apicbase_exception(apicbase | APIC_EN),
+               "x2apic enabled to apic enabled");
+
+        report(!test_write_apicbase_exception(apicbase | 0),
+               "x2apic enabled to disabled state");
+        report(test_write_apicbase_exception(apicbase | APIC_EXTD),
+               "disabled to invalid state");
+        report(test_write_apicbase_exception(apicbase | APIC_EN | APIC_EXTD),
+               "disabled to x2apic enabled");
+
+        report(!test_write_apicbase_exception(apicbase | APIC_EN),
+               "apic disabled to apic enabled");
+        report(test_write_apicbase_exception(apicbase | APIC_EXTD),
+               "apic enabled to invalid state");
 
         if (orig_apicbase & APIC_EXTD)
             enable_x2apic();

@@ -112,8 +112,8 @@ static void test_enable_x2apic(void)
     } else {
         printf("x2apic not detected\n");
 
-        report("enable unsupported x2apic",
-               test_write_apicbase_exception(APIC_EN | APIC_EXTD));
+        report(test_write_apicbase_exception(APIC_EN | APIC_EXTD),
+               "enable unsupported x2apic");
     }
 }
 

@@ -124,11 +124,11 @@ static void verify_disabled_apic_mmio(void)
     u32 cr8 = read_cr8();
 
     memset((void *)APIC_DEFAULT_PHYS_BASE, 0xff, PAGE_SIZE);
-    report("*0xfee00030: %x", *lvr == ~0, *lvr);
-    report("CR8: %lx", read_cr8() == cr8, read_cr8());
+    report(*lvr == ~0, "*0xfee00030: %x", *lvr);
+    report(read_cr8() == cr8, "CR8: %lx", read_cr8());
     write_cr8(cr8 ^ MAX_TPR);
-    report("CR8: %lx", read_cr8() == (cr8 ^ MAX_TPR), read_cr8());
-    report("*0xfee00080: %x", *tpr == ~0, *tpr);
+    report(read_cr8() == (cr8 ^ MAX_TPR), "CR8: %lx", read_cr8());
+    report(*tpr == ~0, "*0xfee00080: %x", *tpr);
     write_cr8(cr8);
 }
 

@@ -144,26 +144,27 @@ static void test_apic_disable(void)
     assert_msg(orig_apicbase & APIC_EN, "APIC not enabled.");
 
     disable_apic();
-    report("Local apic disabled", !(rdmsr(MSR_IA32_APICBASE) & APIC_EN));
-    report("CPUID.1H:EDX.APIC[bit 9] is clear", !this_cpu_has(X86_FEATURE_APIC));
+    report(!(rdmsr(MSR_IA32_APICBASE) & APIC_EN), "Local apic disabled");
+    report(!this_cpu_has(X86_FEATURE_APIC),
+           "CPUID.1H:EDX.APIC[bit 9] is clear");
     verify_disabled_apic_mmio();
 
     reset_apic();
-    report("Local apic enabled in xAPIC mode",
-	   (rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) == APIC_EN);
-    report("CPUID.1H:EDX.APIC[bit 9] is set", this_cpu_has(X86_FEATURE_APIC));
-    report("*0xfee00030: %x", *lvr == apic_version, *lvr);
-    report("*0xfee00080: %x", *tpr == cr8, *tpr);
+    report((rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) == APIC_EN,
+           "Local apic enabled in xAPIC mode");
+    report(this_cpu_has(X86_FEATURE_APIC), "CPUID.1H:EDX.APIC[bit 9] is set");
+    report(*lvr == apic_version, "*0xfee00030: %x", *lvr);
+    report(*tpr == cr8, "*0xfee00080: %x", *tpr);
     write_cr8(cr8 ^ MAX_TPR);
-    report("*0xfee00080: %x", *tpr == (cr8 ^ MAX_TPR) << 4, *tpr);
+    report(*tpr == (cr8 ^ MAX_TPR) << 4, "*0xfee00080: %x", *tpr);
     write_cr8(cr8);
 
     if (enable_x2apic()) {
 	apic_write(APIC_SPIV, 0x1ff);
-	report("Local apic enabled in x2APIC mode",
-	   (rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) ==
-	   (APIC_EN | APIC_EXTD));
-	report("CPUID.1H:EDX.APIC[bit 9] is set", this_cpu_has(X86_FEATURE_APIC));
+	report((rdmsr(MSR_IA32_APICBASE) & (APIC_EN | APIC_EXTD)) == (APIC_EN | APIC_EXTD),
+               "Local apic enabled in x2APIC mode");
+	report(this_cpu_has(X86_FEATURE_APIC),
+               "CPUID.1H:EDX.APIC[bit 9] is set");
 	verify_disabled_apic_mmio();
 	if (!(orig_apicbase & APIC_EXTD))
 	    reset_apic();

@@ -184,16 +185,16 @@ static void test_apicbase(void)
 
     report_prefix_push("apicbase");
 
-    report("relocate apic",
-           *(volatile u32 *)(ALTERNATE_APIC_BASE + APIC_LVR) == lvr);
+    report(*(volatile u32 *)(ALTERNATE_APIC_BASE + APIC_LVR) == lvr,
+           "relocate apic");
 
     value = orig_apicbase | (1UL << cpuid_maxphyaddr());
-    report("reserved physaddr bits",
-           test_for_exception(GP_VECTOR, do_write_apicbase, &value));
+    report(test_for_exception(GP_VECTOR, do_write_apicbase, &value),
+           "reserved physaddr bits");
 
     value = orig_apicbase | 1;
-    report("reserved low bits",
-           test_for_exception(GP_VECTOR, do_write_apicbase, &value));
+    report(test_for_exception(GP_VECTOR, do_write_apicbase, &value),
+           "reserved low bits");
 
     wrmsr(MSR_IA32_APICBASE, orig_apicbase);
     apic_write(APIC_SPIV, 0x1ff);

@@ -217,29 +218,29 @@ static void __test_apic_id(void * unused)
         reset_apic();
 
     id = apic_id();
-    report("xapic id matches cpuid", initial_xapic_id == id);
+    report(initial_xapic_id == id, "xapic id matches cpuid");
 
     newid = (id + 1) << 24;
-    report("writeable xapic id",
-            !test_for_exception(GP_VECTOR, do_write_apic_id, &newid) &&
-	    (id == apic_id() || id + 1 == apic_id()));
+    report(!test_for_exception(GP_VECTOR, do_write_apic_id, &newid) &&
+           (id == apic_id() || id + 1 == apic_id()),
+           "writeable xapic id");
 
     if (!enable_x2apic())
         goto out;
 
-    report("non-writeable x2apic id",
-            test_for_exception(GP_VECTOR, do_write_apic_id, &newid));
-    report("sane x2apic id", initial_xapic_id == (apic_id() & 0xff));
+    report(test_for_exception(GP_VECTOR, do_write_apic_id, &newid),
+           "non-writeable x2apic id");
+    report(initial_xapic_id == (apic_id() & 0xff), "sane x2apic id");
 
     /* old QEMUs do not set initial x2APIC ID */
-    report("x2apic id matches cpuid",
-           initial_xapic_id == (initial_x2apic_id & 0xff) &&
-           initial_x2apic_id == apic_id());
+    report(initial_xapic_id == (initial_x2apic_id & 0xff) && 
+           initial_x2apic_id == apic_id(),
+           "x2apic id matches cpuid");
 
 out:
     reset_apic();
 
-    report("correct xapic id after reset", initial_xapic_id == apic_id());
+    report(initial_xapic_id == apic_id(), "correct xapic id after reset");
 
     /* old KVMs do not reset xAPIC ID */
     if (id != apic_id())

@@ -279,7 +280,7 @@ static void test_self_ipi(void)
         pause();
     } while (rdtsc() - start < 1000000000 && ipi_count == 0);
 
-    report("self ipi", ipi_count == 1);
+    report(ipi_count == 1, "self ipi");
 }
 
 volatile int nmi_counter_private, nmi_counter, nmi_hlt_counter, sti_loop_active;

@@ -343,7 +344,7 @@ static void test_sti_nmi(void)
 	}
     }
     sti_loop_active = 0;
-    report("nmi-after-sti", nmi_hlt_counter == 0);
+    report(nmi_hlt_counter == 0, "nmi-after-sti");
 }
 
 static volatile bool nmi_done, nmi_flushed;

@@ -417,7 +418,7 @@ static void test_multiple_nmi(void)
 	}
     }
     nmi_done = true;
-    report("multiple nmi", ok);
+    report(ok, "multiple nmi");
 }
 
 static void pending_nmi_handler(isr_regs_t *regs)

@@ -445,7 +446,7 @@ static void test_pending_nmi(void)
         if (nmi_received != 2)
             break;
     }
-    report("pending nmi", nmi_received == 2);
+    report(nmi_received == 2, "pending nmi");
 }
 
 static volatile int lvtt_counter = 0;

@@ -485,8 +486,8 @@ static void test_apic_timer_one_shot(void)
      * cases, the following should satisfy on all modern
      * processors.
      */
-    report("APIC LVT timer one shot", (lvtt_counter == 1) &&
-           (tsc2 - tsc1 >= interval));
+    report((lvtt_counter == 1) && (tsc2 - tsc1 >= interval),
+           "APIC LVT timer one shot");
 }
 
 static atomic_t broadcast_counter;

@@ -527,11 +528,11 @@ static void test_physical_broadcast(void)
 	printf("starting broadcast (%s)\n", enable_x2apic() ? "x2apic" : "xapic");
 	apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_FIXED | APIC_INT_ASSERT |
 			BROADCAST_VECTOR, broadcast_address);
-	report("APIC physical broadcast address", broadcast_received(ncpus));
+	report(broadcast_received(ncpus), "APIC physical broadcast address");
 
 	apic_icr_write(APIC_DEST_PHYSICAL | APIC_DM_FIXED | APIC_INT_ASSERT |
 			BROADCAST_VECTOR | APIC_DEST_ALLINC, 0);
-	report("APIC physical broadcast shorthand", broadcast_received(ncpus));
+	report(broadcast_received(ncpus), "APIC physical broadcast shorthand");
 }
 
 static void wait_until_tmcct_common(uint32_t initial_count, bool stop_when_half, bool should_wrap_around)

@@ -583,15 +584,15 @@ static void test_apic_change_mode(void)
 
 	apic_change_mode(APIC_LVT_TIMER_PERIODIC);
 
-	report("TMICT value reset", apic_read(APIC_TMICT) == tmict);
+	report(apic_read(APIC_TMICT) == tmict, "TMICT value reset");
 
 	/* Testing one-shot */
 	apic_change_mode(APIC_LVT_TIMER_ONESHOT);
 	apic_write(APIC_TMICT, tmict);
-	report("TMCCT should have a non-zero value", apic_read(APIC_TMCCT));
+	report(apic_read(APIC_TMCCT), "TMCCT should have a non-zero value");
 
 	wait_until_tmcct_is_zero(tmict, false);
-	report("TMCCT should have reached 0", !apic_read(APIC_TMCCT));
+	report(!apic_read(APIC_TMCCT), "TMCCT should have reached 0");
 
 	/*
 	 * Write TMICT before changing mode from one-shot to periodic TMCCT should

@@ -600,20 +601,22 @@ static void test_apic_change_mode(void)
 	apic_write(APIC_TMICT, tmict);
 	wait_until_tmcct_is_zero(tmict, true);
 	apic_change_mode(APIC_LVT_TIMER_PERIODIC);
-	report("TMCCT should have a non-zero value", apic_read(APIC_TMCCT));
+	report(apic_read(APIC_TMCCT), "TMCCT should have a non-zero value");
 
 	/*
 	 * After the change of mode, the counter should not be reset and continue
 	 * counting down from where it was
 	 */
-	report("TMCCT should not be reset to TMICT value", apic_read(APIC_TMCCT) < (tmict / 2));
+	report(apic_read(APIC_TMCCT) < (tmict / 2),
+	       "TMCCT should not be reset to TMICT value");
 	/*
 	 * Specifically wait for timer wrap around and skip 0.
 	 * Under KVM lapic there is a possibility that a small amount of consecutive
 	 * TMCCR reads return 0 while hrtimer is reset in an async callback
 	 */
 	wait_until_tmcct_wrap_around(tmict, false);
-	report("TMCCT should be reset to the initial-count", apic_read(APIC_TMCCT) > (tmict / 2));
+	report(apic_read(APIC_TMCCT) > (tmict / 2),
+	       "TMCCT should be reset to the initial-count");
 
 	wait_until_tmcct_is_zero(tmict, true);
 	/*

@@ -621,13 +624,14 @@ static void test_apic_change_mode(void)
 	 * TMCCT should be > 0 and count-down to 0
 	 */
 	apic_change_mode(APIC_LVT_TIMER_ONESHOT);
-	report("TMCCT should not be reset to init", apic_read(APIC_TMCCT) < (tmict / 2));
+	report(apic_read(APIC_TMCCT) < (tmict / 2),
+	       "TMCCT should not be reset to init");
 	wait_until_tmcct_is_zero(tmict, false);
-	report("TMCCT should have reach zero", !apic_read(APIC_TMCCT));
+	report(!apic_read(APIC_TMCCT), "TMCCT should have reach zero");
 
 	/* now tmcct == 0 and tmict != 0 */
 	apic_change_mode(APIC_LVT_TIMER_PERIODIC);
-	report("TMCCT should stay at zero", !apic_read(APIC_TMCCT));
+	report(!apic_read(APIC_TMCCT), "TMCCT should stay at zero");
 }
 
 #define KVM_HC_SEND_IPI 10

@@ -638,7 +642,7 @@ static void test_pv_ipi(void)
     unsigned long a0 = 0xFFFFFFFF, a1 = 0, a2 = 0xFFFFFFFF, a3 = 0x0;
 
     asm volatile("vmcall" : "=a"(ret) :"a"(KVM_HC_SEND_IPI), "b"(a0), "c"(a1), "d"(a2), "S"(a3));
-    report("PV IPIs testing", !ret);
+    report(!ret, "PV IPIs testing");
 }
 
 int main(void)

x86/asyncpf.c +6 -5

index de3d592..80bbe45 100644
@@ -55,21 +55,22 @@ static void pf_isr(struct ex_regs *r)
 
 	switch (reason) {
 		case 0:
-			report("unexpected #PF at %#lx", false, read_cr2());
+			report(false, "unexpected #PF at %#lx", read_cr2());
 			break;
 		case KVM_PV_REASON_PAGE_NOT_PRESENT:
 			phys = virt_to_pte_phys(phys_to_virt(read_cr3()), virt);
 			install_pte(phys_to_virt(read_cr3()), 1, virt, phys, 0);
 			write_cr3(read_cr3());
-			report("Got not present #PF token %lx virt addr %p phys addr %#" PRIx64,
-					true, read_cr2(), virt, phys);
+			report(true,
+			       "Got not present #PF token %lx virt addr %p phys addr %#" PRIx64,
+			       read_cr2(), virt, phys);
 			while(phys) {
 				safe_halt(); /* enables irq */
 				irq_disable();
 			}
 			break;
 		case KVM_PV_REASON_PAGE_READY:
-			report("Got present #PF token %lx", true, read_cr2());
+			report(true, "Got present #PF token %lx", read_cr2());
 			if ((uint32_t)read_cr2() == ~0)
 				break;
 			install_pte(phys_to_virt(read_cr3()), 1, virt, phys | PT_PRESENT_MASK | PT_WRITABLE_MASK, 0);

@@ -77,7 +78,7 @@ static void pf_isr(struct ex_regs *r)
 			phys = 0;
 			break;
 		default:
-			report("unexpected async pf reason %d", false, reason);
+			report(false, "unexpected async pf reason %d", reason);
 			break;
 	}
 }

x86/cmpxchg8b.c +1 -1

index c56d295..bbba2f9 100644
@@ -14,7 +14,7 @@ static void test_cmpxchg8b(u32 *mem)
         "lock cmpxchg8b (%0)\n"
         "pop %%ebx" : : "D" (mem),
         "d" (2), "a" (1), "c" (4), [ebx_val] "i" (3) : "memory");
-    report("cmpxchg8b", mem[0] == 3 && mem[1] == 4);
+    report(mem[0] == 3 && mem[1] == 4, "cmpxchg8b");
 }
 
 int main(void)

x86/debug.c +34 -35

index 7365c25..c5db4c6 100644
@@ -81,25 +81,25 @@ int main(int ac, char **av)
 
 	extern unsigned char sw_bp;
 	asm volatile("int3; sw_bp:");
-	report("#BP", bp_addr == (unsigned long)&sw_bp);
+	report(bp_addr == (unsigned long)&sw_bp, "#BP");
 
 	n = 0;
 	extern unsigned char hw_bp1;
 	set_dr0(&hw_bp1);
 	set_dr7(0x00000402);
 	asm volatile("hw_bp1: nop");
-	report("hw breakpoint (test that dr6.BS is not set)",
-	       n == 1 &&
-	       db_addr[0] == ((unsigned long)&hw_bp1) && dr6[0] == 0xffff0ff1);
+	report(n == 1 &&
+	       db_addr[0] == ((unsigned long)&hw_bp1) && dr6[0] == 0xffff0ff1,
+	       "hw breakpoint (test that dr6.BS is not set)");
 
 	n = 0;
 	extern unsigned char hw_bp2;
 	set_dr0(&hw_bp2);
 	set_dr6(0x00004002);
 	asm volatile("hw_bp2: nop");
-	report("hw breakpoint (test that dr6.BS is not cleared)",
-	       n == 1 &&
-	       db_addr[0] == ((unsigned long)&hw_bp2) && dr6[0] == 0xffff4ff1);
+	report(n == 1 &&
+	       db_addr[0] == ((unsigned long)&hw_bp2) && dr6[0] == 0xffff4ff1,
+	       "hw breakpoint (test that dr6.BS is not cleared)");
 
 	n = 0;
 	set_dr6(0);

@@ -114,11 +114,11 @@ int main(int ac, char **av)
 		"push %%rax\n\t"
 		"popf\n\t"
 		: "=r" (start) : : "rax");
-	report("single step",
-	       n == 3 &&
-	       db_addr[0] == start+1+6 && dr6[0] == 0xffff4ff0 &&
-	       db_addr[1] == start+1+6+1 && dr6[1] == 0xffff4ff0 &&
-	       db_addr[2] == start+1+6+1+1 && dr6[2] == 0xffff4ff0);
+	report(n == 3 &&
+	       db_addr[0] == start + 1 + 6 && dr6[0] == 0xffff4ff0 &&
+	       db_addr[1] == start + 1 + 6 + 1 && dr6[1] == 0xffff4ff0 &&
+	       db_addr[2] == start + 1 + 6 + 1 + 1 && dr6[2] == 0xffff4ff0,
+	       "single step");
 
 	/*
 	 * cpuid and rdmsr (among others) trigger VM exits and are then

@@ -141,15 +141,15 @@ int main(int ac, char **av)
 		"rdmsr\n\t"
 		"popf\n\t"
 		: "=r" (start) : : "rax", "ebx", "ecx", "edx");
-	report("single step emulated instructions",
-	       n == 7 &&
-	       db_addr[0] == start+1+6 && dr6[0] == 0xffff4ff0 &&
-	       db_addr[1] == start+1+6+1 && dr6[1] == 0xffff4ff0 &&
-	       db_addr[2] == start+1+6+1+3 && dr6[2] == 0xffff4ff0 &&
-	       db_addr[3] == start+1+6+1+3+2 && dr6[3] == 0xffff4ff0 &&
-	       db_addr[4] == start+1+6+1+3+2+5 && dr6[4] == 0xffff4ff0 &&
-	       db_addr[5] == start+1+6+1+3+2+5+2 && dr6[5] == 0xffff4ff0 &&
-	       db_addr[6] == start+1+6+1+3+2+5+2+1 && dr6[6] == 0xffff4ff0);
+	report(n == 7 &&
+	       db_addr[0] == start + 1 + 6 && dr6[0] == 0xffff4ff0 &&
+	       db_addr[1] == start + 1 + 6 + 1 && dr6[1] == 0xffff4ff0 &&
+	       db_addr[2] == start + 1 + 6 + 1 + 3 && dr6[2] == 0xffff4ff0 &&
+	       db_addr[3] == start + 1 + 6 + 1 + 3 + 2 && dr6[3] == 0xffff4ff0 &&
+	       db_addr[4] == start + 1 + 6 + 1 + 3 + 2 + 5 && dr6[4] == 0xffff4ff0 &&
+	       db_addr[5] == start + 1 + 6 + 1 + 3 + 2 + 5 + 2 && dr6[5] == 0xffff4ff0 &&
+	       db_addr[6] == start + 1 + 6 + 1 + 3 + 2 + 5 + 2 + 1 && dr6[6] == 0xffff4ff0,
+	       "single step emulated instructions");
 
 	n = 0;
 	set_dr1((void *)&value);

@@ -160,9 +160,9 @@ int main(int ac, char **av)
 		"mov $42,%%rax\n\t"
 		"mov %%rax,%0\n\t; hw_wp1:"
 		: "=m" (value) : : "rax");
-	report("hw watchpoint (test that dr6.BS is not cleared)",
-	       n == 1 &&
-	       db_addr[0] == ((unsigned long)&hw_wp1) && dr6[0] == 0xffff4ff2);
+	report(n == 1 &&
+	       db_addr[0] == ((unsigned long)&hw_wp1) && dr6[0] == 0xffff4ff2,
+	       "hw watchpoint (test that dr6.BS is not cleared)");
 
 	n = 0;
 	set_dr6(0);

@@ -172,18 +172,17 @@ int main(int ac, char **av)
 		"mov $42,%%rax\n\t"
 		"mov %%rax,%0\n\t; hw_wp2:"
 		: "=m" (value) : : "rax");
-	report("hw watchpoint (test that dr6.BS is not set)",
-	       n == 1 &&
-	       db_addr[0] == ((unsigned long)&hw_wp2) && dr6[0] == 0xffff0ff2);
+	report(n == 1 &&
+	       db_addr[0] == ((unsigned long)&hw_wp2) && dr6[0] == 0xffff0ff2,
+	       "hw watchpoint (test that dr6.BS is not set)");
 
 	n = 0;
 	set_dr6(0);
 	extern unsigned char sw_icebp;
 	asm volatile(".byte 0xf1; sw_icebp:");
-	report("icebp",
-	       n == 1 &&
-	       db_addr[0] == (unsigned long)&sw_icebp &&
-	       dr6[0] == 0xffff0ff0);
+	report(n == 1 &&
+	       db_addr[0] == (unsigned long)&sw_icebp && dr6[0] == 0xffff0ff0,
+	       "icebp");
 
 	set_dr7(0x400);
 	value = KERNEL_DS;

@@ -203,7 +202,7 @@ int main(int ac, char **av)
 		"mov %0,%%ss\n\t"
 		".byte 0x2e, 0x2e, 0xf1"
 		: "=m" (value) : : "rax");
-	report("MOV SS + watchpoint + ICEBP", n == 3);
+	report(n == 3, "MOV SS + watchpoint + ICEBP");
 
 	/*
 	 * Here the #DB handler is invoked twice, once as a software exception

@@ -215,7 +214,7 @@ int main(int ac, char **av)
 		"mov %0,%%ss\n\t"
 		"int $1"
 		: "=m" (value) : : "rax");
-	report("MOV SS + watchpoint + int $1", n == 7);
+	report(n == 7, "MOV SS + watchpoint + int $1");
 
 	/*
 	 * Here the #DB and #BP handlers are invoked once each.

@@ -228,7 +227,7 @@ int main(int ac, char **av)
 		"sw_bp2:"
 		: "=m" (value) : : "rax");
 	extern unsigned char sw_bp2;
-	report("MOV SS + watchpoint + INT3",
-	       n == 3 && bp_addr == (unsigned long)&sw_bp2);
+	report(n == 3 && bp_addr == (unsigned long)&sw_bp2,
+	       "MOV SS + watchpoint + INT3");
 	return report_summary();
 }

x86/emulator.c +147 -143

index 621caf9..8fe03b8 100644
@@ -42,7 +42,7 @@ static void test_stringio(void)
 		     : : "i"((short)TESTDEV_IO_PORT),
 		       "S"(st1), "c"(sizeof(st1) - 1));
 	asm volatile("inb %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT));
-	report("outsb up", r == st1[sizeof(st1) - 2]); /* last char */
+	report(r == st1[sizeof(st1) - 2], "outsb up"); /* last char */
 
 	asm volatile("std \n\t"
 		     "movw %0, %%dx \n\t"

@@ -51,7 +51,7 @@ static void test_stringio(void)
 		       "S"(st1 + sizeof(st1) - 2), "c"(sizeof(st1) - 1));
 	asm volatile("cld \n\t" : : );
 	asm volatile("in %1, %0\n\t" : "=a"(r) : "i"((short)TESTDEV_IO_PORT));
-	report("outsb down", r == st1[0]);
+	report(r == st1[0], "outsb down");
 }
 
 static void test_cmps_one(unsigned char *m1, unsigned char *m3)

@@ -64,67 +64,68 @@ static void test_cmps_one(unsigned char *m1, unsigned char *m3)
 		     "repe/cmpsb"
 		     : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp)
 		     : : "cc");
-	report("repe/cmpsb (1)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30);
+	report(rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30, "repe/cmpsb (1)");
 
 	rsi = m1; rdi = m3; rcx = 30;
 	asm volatile("or $1, %[tmp]\n\t" // clear ZF
 		     "repe/cmpsb"
 		     : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp)
 		     : : "cc");
-	report("repe/cmpsb (1.zf)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30);
+	report(rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30,
+	       "repe/cmpsb (1.zf)");
 
 	rsi = m1; rdi = m3; rcx = 15;
 	asm volatile("xor %[tmp], %[tmp] \n\t"
 		     "repe/cmpsw"
 		     : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp)
 		     : : "cc");
-	report("repe/cmpsw (1)", rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30);
+	report(rcx == 0 && rsi == m1 + 30 && rdi == m3 + 30, "repe/cmpsw (1)");
 
 	rsi = m1; rdi = m3; rcx = 7;
 	asm volatile("xor %[tmp], %[tmp] \n\t"
 		     "repe/cmpsl"
 		     : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp)
 		     : : "cc");
-	report("repe/cmpll (1)", rcx == 0 && rsi == m1 + 28 && rdi == m3 + 28);
+	report(rcx == 0 && rsi == m1 + 28 && rdi == m3 + 28, "repe/cmpll (1)");
 
 	rsi = m1; rdi = m3; rcx = 4;
 	asm volatile("xor %[tmp], %[tmp] \n\t"
 		     "repe/cmpsq"
 		     : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp)
 		     : : "cc");
-	report("repe/cmpsq (1)", rcx == 0 && rsi == m1 + 32 && rdi == m3 + 32);
+	report(rcx == 0 && rsi == m1 + 32 && rdi == m3 + 32, "repe/cmpsq (1)");
 
 	rsi = m1; rdi = m3; rcx = 130;
 	asm volatile("xor %[tmp], %[tmp] \n\t"
 		     "repe/cmpsb"
 		     : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp)
 		     : : "cc");
-	report("repe/cmpsb (2)",
-	       rcx == 29 && rsi == m1 + 101 && rdi == m3 + 101);
+	report(rcx == 29 && rsi == m1 + 101 && rdi == m3 + 101,
+	       "repe/cmpsb (2)");
 
 	rsi = m1; rdi = m3; rcx = 65;
 	asm volatile("xor %[tmp], %[tmp] \n\t"
 		     "repe/cmpsw"
 		     : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp)
 		     : : "cc");
-	report("repe/cmpsw (2)",
-	       rcx == 14 && rsi == m1 + 102 && rdi == m3 + 102);
+	report(rcx == 14 && rsi == m1 + 102 && rdi == m3 + 102,
+	       "repe/cmpsw (2)");
 
 	rsi = m1; rdi = m3; rcx = 32;
 	asm volatile("xor %[tmp], %[tmp] \n\t"
 		     "repe/cmpsl"
 		     : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp)
 		     : : "cc");
-	report("repe/cmpll (2)",
-	       rcx == 6 && rsi == m1 + 104 && rdi == m3 + 104);
+	report(rcx == 6 && rsi == m1 + 104 && rdi == m3 + 104,
+	       "repe/cmpll (2)");
 
 	rsi = m1; rdi = m3; rcx = 16;
 	asm volatile("xor %[tmp], %[tmp] \n\t"
 		     "repe/cmpsq"
 		     : "+S"(rsi), "+D"(rdi), "+c"(rcx), [tmp]"=&r"(tmp)
 		     : : "cc");
-	report("repe/cmpsq (2)",
-	       rcx == 3 && rsi == m1 + 104 && rdi == m3 + 104);
+	report(rcx == 3 && rsi == m1 + 104 && rdi == m3 + 104,
+	       "repe/cmpsq (2)");
 
 }
 

@@ -150,35 +151,35 @@ static void test_scas(void *mem)
 
     di = mem;
     asm ("scasb; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff11));
-    report("scasb match", di == mem + 1 && z);
+    report(di == mem + 1 && z, "scasb match");
 
     di = mem;
     asm ("scasb; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff54));
-    report("scasb mismatch", di == mem + 1 && !z);
+    report(di == mem + 1 && !z, "scasb mismatch");
 
     di = mem;
     asm ("scasw; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff2211));
-    report("scasw match", di == mem + 2 && z);
+    report(di == mem + 2 && z, "scasw match");
 
     di = mem;
     asm ("scasw; setz %0" : "=rm"(z), "+D"(di) : "a"(0xffdd11));
-    report("scasw mismatch", di == mem + 2 && !z);
+    report(di == mem + 2 && !z, "scasw mismatch");
 
     di = mem;
     asm ("scasl; setz %0" : "=rm"(z), "+D"(di) : "a"(0xff44332211ul));
-    report("scasd match", di == mem + 4 && z);
+    report(di == mem + 4 && z, "scasd match");
 
     di = mem;
     asm ("scasl; setz %0" : "=rm"(z), "+D"(di) : "a"(0x45332211));
-    report("scasd mismatch", di == mem + 4 && !z);
+    report(di == mem + 4 && !z, "scasd mismatch");
 
     di = mem;
     asm ("scasq; setz %0" : "=rm"(z), "+D"(di) : "a"(0x77665544332211ul));
-    report("scasq match", di == mem + 8 && z);
+    report(di == mem + 8 && z, "scasq match");
 
     di = mem;
     asm ("scasq; setz %0" : "=rm"(z), "+D"(di) : "a"(3));
-    report("scasq mismatch", di == mem + 8 && !z);
+    report(di == mem + 8 && !z, "scasq mismatch");
 }
 
 static void test_cr8(void)

@@ -189,7 +190,7 @@ static void test_cr8(void)
 	src = 3;
 	asm volatile("mov %[src], %%cr8; mov %%cr8, %[dst]"
 		     : [dst]"+r"(dst), [src]"+r"(src));
-	report("mov %%cr8", dst == 3 && src == 3);
+	report(dst == 3 && src == 3, "mov %%cr8");
 }
 
 static void test_push(void *mem)

@@ -214,10 +215,10 @@ static void test_push(void *mem)
 		       [reg]"r"(-17l), [mem]"r"(&memw)
 		     : "memory");
 
-	report("push $imm8", stack_top[-1] == -7ul);
-	report("push %%reg", stack_top[-2] == -17ul);
-	report("push mem", stack_top[-3] == 0x123456789abcdeful);
-	report("push $imm", stack_top[-4] == -7070707);
+	report(stack_top[-1] == -7ul, "push $imm8");
+	report(stack_top[-2] == -17ul, "push %%reg");
+	report(stack_top[-3] == 0x123456789abcdeful, "push mem");
+	report(stack_top[-4] == -7070707, "push $imm");
 }
 
 static void test_pop(void *mem)

@@ -232,7 +233,7 @@ static void test_pop(void *mem)
 	asm volatile("pushq %[val] \n\t"
 		     "popq (%[mem])"
 		     : : [val]"m"(memw), [mem]"r"(mem) : "memory");
-	report("pop mem", *(unsigned long *)mem == memw);
+	report(*(unsigned long *)mem == memw, "pop mem");
 
 	memw = 7 - memw;
 	asm volatile("mov %%rsp, %[tmp] \n\t"

@@ -243,7 +244,7 @@ static void test_pop(void *mem)
 		     : [tmp]"=&r"(tmp), [tmp2]"=m"(tmp2)
 		     : [val]"r"(memw), [stack_top]"r"(stack_top)
 		     : "memory");
-	report("pop mem (2)", tmp2 == memw);
+	report(tmp2 == memw, "pop mem (2)");
 
 	memw = 129443 - memw;
 	asm volatile("mov %%rsp, %[tmp] \n\t"

@@ -254,7 +255,7 @@ static void test_pop(void *mem)
 		     : [tmp]"=&r"(tmp), [tmp2]"=r"(tmp2)
 		     : [val]"r"(memw), [stack_top]"r"(stack_top)
 		     : "memory");
-	report("pop reg", tmp2 == memw);
+	report(tmp2 == memw, "pop reg");
 
 	asm volatile("mov %%rsp, %[tmp] \n\t"
 		     "mov %[stack_top], %%rsp \n\t"

@@ -264,7 +265,7 @@ static void test_pop(void *mem)
 		     "1: mov %[tmp], %%rsp"
 		     : [tmp]"=&r"(tmp) : [stack_top]"r"(stack_top)
 		     : "memory");
-	report("ret", 1);
+	report(1, "ret");
 
 	stack_top[-1] = 0x778899;
 	asm volatile("mov %[stack_top], %%r8 \n\t"

@@ -277,7 +278,7 @@ static void test_pop(void *mem)
 		     "mov %%r8, %[tmp3]"
 		     : [tmp]"=&r"(tmp), [tmp3]"=&r"(tmp3) : [stack_top]"r"(stack_top-1)
 		     : "memory", "r8", "r9");
-	report("leave", tmp == (ulong)stack_top && tmp3 == 0x778899);
+	report(tmp == (ulong)stack_top && tmp3 == 0x778899, "leave");
 
 	rbp = 0xaa55aa55bb66bb66ULL;
 	rsp = (unsigned long)stack_top;

@@ -291,10 +292,10 @@ static void test_pop(void *mem)
 		     "xchg %%r8, %[rsp] \n\t"
 		     "xchg %%r9, %[rbp]"
 		     : [rsp]"+a"(rsp), [rbp]"+b"(rbp) : : "memory", "r8", "r9");
-	report("enter",
-	       rsp == (unsigned long)stack_top - 8 - 0x1238
+	report(rsp == (unsigned long)stack_top - 8 - 0x1238
 	       && rbp == (unsigned long)stack_top - 8
-	       && stack_top[-1] == 0xaa55aa55bb66bb66ULL);
+	       && stack_top[-1] == 0xaa55aa55bb66bb66ULL,
+	       "enter");
 }
 
 static void test_ljmp(void *mem)

@@ -307,7 +308,7 @@ static void test_ljmp(void *mem)
     asm volatile ("rex64/ljmp *%0"::"m"(*m));
     res = 0;
 jmpf:
-    report("ljmp", res);
+    report(res, "ljmp");
 }
 
 static void test_incdecnotneg(void *mem)

@@ -318,36 +319,36 @@ static void test_incdecnotneg(void *mem)
     *m = 0;
 
     asm volatile ("incl %0":"+m"(*m));
-    report("incl",  *m == 1);
+    report(*m == 1, "incl");
     asm volatile ("decl %0":"+m"(*m));
-    report("decl",  *m == 0);
+    report(*m == 0, "decl");
     asm volatile ("incb %0":"+m"(*m));
-    report("incb",  *m == 1);
+    report(*m == 1, "incb");
     asm volatile ("decb %0":"+m"(*m));
-    report("decb",  *m == 0);
+    report(*m == 0, "decb");
 
     asm volatile ("lock incl %0":"+m"(*m));
-    report("lock incl",  *m == 1);
+    report(*m == 1, "lock incl");
     asm volatile ("lock decl %0":"+m"(*m));
-    report("lock decl",  *m == 0);
+    report(*m == 0, "lock decl");
     asm volatile ("lock incb %0":"+m"(*m));
-    report("lock incb",  *m == 1);
+    report(*m == 1, "lock incb");
     asm volatile ("lock decb %0":"+m"(*m));
-    report("lock decb",  *m == 0);
+    report(*m == 0, "lock decb");
 
     *m = v;
 
     asm ("lock negq %0" : "+m"(*m)); v = -v;
-    report("lock negl", *m == v);
+    report(*m == v, "lock negl");
     asm ("lock notq %0" : "+m"(*m)); v = ~v;
-    report("lock notl", *m == v);
+    report(*m == v, "lock notl");
 
     *mb = vb;
 
     asm ("lock negb %0" : "+m"(*mb)); vb = -vb;
-    report("lock negb", *mb == vb);
+    report(*mb == vb, "lock negb");
     asm ("lock notb %0" : "+m"(*mb)); vb = ~vb;
-    report("lock notb", *mb == vb);
+    report(*mb == vb, "lock notb");
 }
 
 static void test_smsw(uint64_t *h_mem)

@@ -359,7 +360,7 @@ static void test_smsw(uint64_t *h_mem)
 	msw_orig = read_cr0();
 
 	asm("smsw %0" : "=r"(msw));
-	report("smsw (1)", msw == msw_orig);
+	report(msw == msw_orig, "smsw (1)");
 
 	memset(mem, 0, 16);
 	pmsw = (void *)mem;

@@ -368,13 +369,13 @@ static void test_smsw(uint64_t *h_mem)
 	for (i = 0; i < 8; ++i)
 		if (i != 4 && pmsw[i])
 			zero = 0;
-	report("smsw (2)", msw == pmsw[4] && zero);
+	report(msw == pmsw[4] && zero, "smsw (2)");
 
 	/* Trigger exit on smsw */
 	*h_mem = 0x12345678abcdeful;
 	asm volatile("smsw %0" : "+m"(*h_mem));
-	report("smsw (3)", msw == (unsigned short)*h_mem &&
-		(*h_mem & ~0xfffful) == 0x12345678ab0000ul);
+	report(msw == (unsigned short)*h_mem &&
+	       (*h_mem & ~0xfffful) == 0x12345678ab0000ul, "smsw (3)");
 }
 
 static void test_lmsw(void)

@@ -388,18 +389,18 @@ static void test_lmsw(void)
 	msw = cr0 ^ 8;
 	asm("lmsw %0" : : "r"(msw));
 	printf("before %lx after %lx\n", cr0, read_cr0());
-	report("lmsw (1)", (cr0 ^ read_cr0()) == 8);
+	report((cr0 ^ read_cr0()) == 8, "lmsw (1)");
 
 	pmsw = (void *)mem;
 	*pmsw = cr0;
 	asm("lmsw %0" : : "m"(*pmsw));
 	printf("before %lx after %lx\n", cr0, read_cr0());
-	report("lmsw (2)", cr0 == read_cr0());
+	report(cr0 == read_cr0(), "lmsw (2)");
 
 	/* lmsw can't clear cr0.pe */
 	msw = (cr0 & ~1ul) ^ 4;  /* change EM to force trap */
 	asm("lmsw %0" : : "r"(msw));
-	report("lmsw (3)", (cr0 ^ read_cr0()) == 4 && (cr0 & 1));
+	report((cr0 ^ read_cr0()) == 4 && (cr0 & 1), "lmsw (3)");
 
 	/* back to normal */
 	msw = cr0;

@@ -419,8 +420,8 @@ static void test_xchg(void *mem)
 		     : [rax]"=r"(rax)
 		     : [memq]"r"(memq)
 		     : "memory", "rax");
-	report("xchg reg, r/m (1)",
-	       rax == 0xfedcba98765432ef && *memq == 0x123456789abcd10);
+	report(rax == 0xfedcba98765432ef && *memq == 0x123456789abcd10,
+	       "xchg reg, r/m (1)");
 
 	asm volatile("mov $0x123456789abcdef, %%rax\n\t"
 		     "mov %%rax, (%[memq])\n\t"

@@ -430,8 +431,8 @@ static void test_xchg(void *mem)
 		     : [rax]"=r"(rax)
 		     : [memq]"r"(memq)
 		     : "memory", "rax");
-	report("xchg reg, r/m (2)",
-	       rax == 0xfedcba987654cdef && *memq == 0x123456789ab3210);
+	report(rax == 0xfedcba987654cdef && *memq == 0x123456789ab3210,
+	       "xchg reg, r/m (2)");
 
 	asm volatile("mov $0x123456789abcdef, %%rax\n\t"
 		     "mov %%rax, (%[memq])\n\t"

@@ -441,8 +442,8 @@ static void test_xchg(void *mem)
 		     : [rax]"=r"(rax)
 		     : [memq]"r"(memq)
 		     : "memory", "rax");
-	report("xchg reg, r/m (3)",
-	       rax == 0x89abcdef && *memq == 0x123456776543210);
+	report(rax == 0x89abcdef && *memq == 0x123456776543210,
+	       "xchg reg, r/m (3)");
 
 	asm volatile("mov $0x123456789abcdef, %%rax\n\t"
 		     "mov %%rax, (%[memq])\n\t"

@@ -452,8 +453,8 @@ static void test_xchg(void *mem)
 		     : [rax]"=r"(rax)
 		     : [memq]"r"(memq)
 		     : "memory", "rax");
-	report("xchg reg, r/m (4)",
-	       rax == 0x123456789abcdef && *memq == 0xfedcba9876543210);
+	report(rax == 0x123456789abcdef && *memq == 0xfedcba9876543210,
+	       "xchg reg, r/m (4)");
 }
 
 static void test_xadd(void *mem)

@@ -469,8 +470,8 @@ static void test_xadd(void *mem)
 		     : [rax]"=r"(rax)
 		     : [memq]"r"(memq)
 		     : "memory", "rax");
-	report("xadd reg, r/m (1)",
-	       rax == 0xfedcba98765432ef && *memq == 0x123456789abcdff);
+	report(rax == 0xfedcba98765432ef && *memq == 0x123456789abcdff,
+	       "xadd reg, r/m (1)");
 
 	asm volatile("mov $0x123456789abcdef, %%rax\n\t"
 		     "mov %%rax, (%[memq])\n\t"

@@ -480,8 +481,8 @@ static void test_xadd(void *mem)
 		     : [rax]"=r"(rax)
 		     : [memq]"r"(memq)
 		     : "memory", "rax");
-	report("xadd reg, r/m (2)",
-	       rax == 0xfedcba987654cdef && *memq == 0x123456789abffff);
+	report(rax == 0xfedcba987654cdef && *memq == 0x123456789abffff,
+	       "xadd reg, r/m (2)");
 
 	asm volatile("mov $0x123456789abcdef, %%rax\n\t"
 		     "mov %%rax, (%[memq])\n\t"

@@ -491,8 +492,8 @@ static void test_xadd(void *mem)
 		     : [rax]"=r"(rax)
 		     : [memq]"r"(memq)
 		     : "memory", "rax");
-	report("xadd reg, r/m (3)",
-	       rax == 0x89abcdef && *memq == 0x1234567ffffffff);
+	report(rax == 0x89abcdef && *memq == 0x1234567ffffffff,
+	       "xadd reg, r/m (3)");
 
 	asm volatile("mov $0x123456789abcdef, %%rax\n\t"
 		     "mov %%rax, (%[memq])\n\t"

@@ -502,8 +503,8 @@ static void test_xadd(void *mem)
 		     : [rax]"=r"(rax)
 		     : [memq]"r"(memq)
 		     : "memory", "rax");
-	report("xadd reg, r/m (4)",
-	       rax == 0x123456789abcdef && *memq == 0xffffffffffffffff);
+	report(rax == 0x123456789abcdef && *memq == 0xffffffffffffffff,
+	       "xadd reg, r/m (4)");
 }
 
 static void test_btc(void *mem)

@@ -515,14 +516,14 @@ static void test_btc(void *mem)
 	asm ("btcl $32, %0" :: "m"(a[0]) : "memory");
 	asm ("btcl $1, %0" :: "m"(a[1]) : "memory");
 	asm ("btcl %1, %0" :: "m"(a[0]), "r"(66) : "memory");
-	report("btcl imm8, r/m", a[0] == 1 && a[1] == 2 && a[2] == 4);
+	report(a[0] == 1 && a[1] == 2 && a[2] == 4, "btcl imm8, r/m");
 
 	asm ("btcl %1, %0" :: "m"(a[3]), "r"(-1) : "memory");
-	report("btcl reg, r/m", a[0] == 1 && a[1] == 2 && a[2] == 0x80000004);
+	report(a[0] == 1 && a[1] == 2 && a[2] == 0x80000004, "btcl reg, r/m");
 
 	asm ("btcq %1, %0" : : "m"(a[2]), "r"(-1l) : "memory");
-	report("btcq reg, r/m", a[0] == 1 && a[1] == 0x80000002 &&
-		a[2] == 0x80000004 && a[3] == 0);
+	report(a[0] == 1 && a[1] == 0x80000002 && a[2] == 0x80000004 && a[3] == 0,
+	       "btcq reg, r/m");
 }
 
 static void test_bsfbsr(void *mem)

@@ -534,37 +535,37 @@ static void test_bsfbsr(void *mem)
 
 	*memw = 0xc000;
 	asm("bsfw %[mem], %[a]" : [a]"=a"(ax) : [mem]"m"(*memw));
-	report("bsfw r/m, reg", ax == 14);
+	report(ax == 14, "bsfw r/m, reg");
 
 	*meml = 0xc0000000;
 	asm("bsfl %[mem], %[a]" : [a]"=a"(eax) : [mem]"m"(*meml));
-	report("bsfl r/m, reg", eax == 30);
+	report(eax == 30, "bsfl r/m, reg");
 
 	*memq = 0xc00000000000;
 	asm("bsfq %[mem], %[a]" : [a]"=a"(rax) : [mem]"m"(*memq));
-	report("bsfq r/m, reg", rax == 46);
+	report(rax == 46, "bsfq r/m, reg");
 
 	*memq = 0;
 	asm("bsfq %[mem], %[a]; setz %[z]"
 	    : [a]"=a"(rax), [z]"=rm"(z) : [mem]"m"(*memq));
-	report("bsfq r/m, reg", z == 1);
+	report(z == 1, "bsfq r/m, reg");
 
 	*memw = 0xc000;
 	asm("bsrw %[mem], %[a]" : [a]"=a"(ax) : [mem]"m"(*memw));
-	report("bsrw r/m, reg", ax == 15);
+	report(ax == 15, "bsrw r/m, reg");
 
 	*meml = 0xc0000000;
 	asm("bsrl %[mem], %[a]" : [a]"=a"(eax) : [mem]"m"(*meml));
-	report("bsrl r/m, reg", eax == 31);
+	report(eax == 31, "bsrl r/m, reg");
 
 	*memq = 0xc00000000000;
 	asm("bsrq %[mem], %[a]" : [a]"=a"(rax) : [mem]"m"(*memq));
-	report("bsrq r/m, reg", rax == 47);
+	report(rax == 47, "bsrq r/m, reg");
 
 	*memq = 0;
 	asm("bsrq %[mem], %[a]; setz %[z]"
 	    : [a]"=a"(rax), [z]"=rm"(z) : [mem]"m"(*memq));
-	report("bsrq r/m, reg", z == 1);
+	report(z == 1, "bsrq r/m, reg");
 }
 
 static void test_imul(ulong *mem)

@@ -573,39 +574,39 @@ static void test_imul(ulong *mem)
 
     *mem = 51; a = 0x1234567812345678UL;
     asm ("imulw %1, %%ax" : "+a"(a) : "m"(*mem));
-    report("imul ax, mem", a == 0x12345678123439e8);
+    report(a == 0x12345678123439e8, "imul ax, mem");
 
     *mem = 51; a = 0x1234567812345678UL;
     asm ("imull %1, %%eax" : "+a"(a) : "m"(*mem));
-    report("imul eax, mem", a == 0xa06d39e8);
+    report(a == 0xa06d39e8, "imul eax, mem");
 
     *mem = 51; a = 0x1234567812345678UL;
     asm ("imulq %1, %%rax" : "+a"(a) : "m"(*mem));
-    report("imul rax, mem", a == 0xA06D39EBA06D39E8UL);
+    report(a == 0xA06D39EBA06D39E8UL, "imul rax, mem");
 
     *mem  = 0x1234567812345678UL; a = 0x8765432187654321L;
     asm ("imulw $51, %1, %%ax" : "+a"(a) : "m"(*mem));
-    report("imul ax, mem, imm8", a == 0x87654321876539e8);
+    report(a == 0x87654321876539e8, "imul ax, mem, imm8");
 
     *mem = 0x1234567812345678UL;
     asm ("imull $51, %1, %%eax" : "+a"(a) : "m"(*mem));
-    report("imul eax, mem, imm8", a == 0xa06d39e8);
+    report(a == 0xa06d39e8, "imul eax, mem, imm8");
 
     *mem = 0x1234567812345678UL;
     asm ("imulq $51, %1, %%rax" : "+a"(a) : "m"(*mem));
-    report("imul rax, mem, imm8", a == 0xA06D39EBA06D39E8UL);
+    report(a == 0xA06D39EBA06D39E8UL, "imul rax, mem, imm8");
 
     *mem  = 0x1234567812345678UL; a = 0x8765432187654321L;
     asm ("imulw $311, %1, %%ax" : "+a"(a) : "m"(*mem));
-    report("imul ax, mem, imm", a == 0x8765432187650bc8);
+    report(a == 0x8765432187650bc8, "imul ax, mem, imm");
 
     *mem = 0x1234567812345678UL;
     asm ("imull $311, %1, %%eax" : "+a"(a) : "m"(*mem));
-    report("imul eax, mem, imm", a == 0x1d950bc8);
+    report(a == 0x1d950bc8, "imul eax, mem, imm");
 
     *mem = 0x1234567812345678UL;
     asm ("imulq $311, %1, %%rax" : "+a"(a) : "m"(*mem));
-    report("imul rax, mem, imm", a == 0x1D950BDE1D950BC8L);
+    report(a == 0x1D950BDE1D950BC8L, "imul rax, mem, imm");
 }
 
 static void test_muldiv(long *mem)

@@ -616,26 +617,26 @@ static void test_muldiv(long *mem)
     *mem = 0; a = 1; d = 2;
     asm (ASM_TRY("1f") "divq %3; movb $0, %2; 1:"
 	 : "+a"(a), "+d"(d), "+q"(ex) : "m"(*mem));
-    report("divq (fault)", a == 1 && d == 2 && ex);
+    report(a == 1 && d == 2 && ex, "divq (fault)");
 
     *mem = 987654321098765UL; a = 123456789012345UL; d = 123456789012345UL;
     asm (ASM_TRY("1f") "divq %3; movb $0, %2; 1:"
 	 : "+a"(a), "+d"(d), "+q"(ex) : "m"(*mem));
-    report("divq (1)",
-	   a == 0x1ffffffb1b963b33ul && d == 0x273ba4384ede2ul && !ex);
+    report(a == 0x1ffffffb1b963b33ul && d == 0x273ba4384ede2ul && !ex,
+           "divq (1)");
     aa = 0x1111111111111111; dd = 0x2222222222222222;
     *mem = 0x3333333333333333; a = aa; d = dd;
     asm("mulb %2" : "+a"(a), "+d"(d) : "m"(*mem));
-    report("mulb mem", a == 0x1111111111110363 && d == dd);
+    report(a == 0x1111111111110363 && d == dd, "mulb mem");
     *mem = 0x3333333333333333; a = aa; d = dd;
     asm("mulw %2" : "+a"(a), "+d"(d) : "m"(*mem));
-    report("mulw mem", a == 0x111111111111c963 && d == 0x2222222222220369);
+    report(a == 0x111111111111c963 && d == 0x2222222222220369, "mulw mem");
     *mem = 0x3333333333333333; a = aa; d = dd;
     asm("mull %2" : "+a"(a), "+d"(d) : "m"(*mem));
-    report("mull mem", a == 0x962fc963 && d == 0x369d036);
+    report(a == 0x962fc963 && d == 0x369d036, "mull mem");
     *mem = 0x3333333333333333; a = aa; d = dd;
     asm("mulq %2" : "+a"(a), "+d"(d) : "m"(*mem));
-    report("mulq mem", a == 0x2fc962fc962fc963 && d == 0x369d0369d0369d0);
+    report(a == 0x2fc962fc962fc963 && d == 0x369d0369d0369d0, "mulq mem");
 }
 
 typedef unsigned __attribute__((vector_size(16))) sse128;

@@ -665,24 +666,24 @@ static __attribute__((target("sse"))) void test_sse(sse_union *mem)
     write_cr4(read_cr4() | 0x200); /* OSFXSR */
     v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4;
     asm("movdqu %1, %0" : "=m"(*mem) : "x"(v.sse));
-    report("movdqu (read)", sseeq(&v, mem));
+    report(sseeq(&v, mem), "movdqu (read)");
     mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8;
     asm("movdqu %1, %0" : "=x"(v.sse) : "m"(*mem));
-    report("movdqu (write)", sseeq(mem, &v));
+    report(sseeq(mem, &v), "movdqu (write)");
 
     v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4;
     asm("movaps %1, %0" : "=m"(*mem) : "x"(v.sse));
-    report("movaps (read)", sseeq(mem, &v));
+    report(sseeq(mem, &v), "movaps (read)");
     mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8;
     asm("movaps %1, %0" : "=x"(v.sse) : "m"(*mem));
-    report("movaps (write)", sseeq(&v, mem));
+    report(sseeq(&v, mem), "movaps (write)");
 
     v.u[0] = 1; v.u[1] = 2; v.u[2] = 3; v.u[3] = 4;
     asm("movapd %1, %0" : "=m"(*mem) : "x"(v.sse));
-    report("movapd (read)", sseeq(mem, &v));
+    report(sseeq(mem, &v), "movapd (read)");
     mem->u[0] = 5; mem->u[1] = 6; mem->u[2] = 7; mem->u[3] = 8;
     asm("movapd %1, %0" : "=x"(v.sse) : "m"(*mem));
-    report("movapd (write)", sseeq(&v, mem));
+    report(sseeq(&v, mem), "movapd (write)");
 }
 
 static void test_mmx(uint64_t *mem)

@@ -693,10 +694,10 @@ static void test_mmx(uint64_t *mem)
     asm volatile("fninit");
     v = 0x0102030405060708ULL;
     asm("movq %1, %0" : "=m"(*mem) : "y"(v));
-    report("movq (mmx, read)", v == *mem);
+    report(v == *mem, "movq (mmx, read)");
     *mem = 0x8070605040302010ull;
     asm("movq %1, %0" : "=y"(v) : "m"(*mem));
-    report("movq (mmx, write)", v == *mem);
+    report(v == *mem, "movq (mmx, write)");
 }
 
 static void test_rip_relative(unsigned *mem, char *insn_ram)

@@ -711,17 +712,17 @@ static void test_rip_relative(unsigned *mem, char *insn_ram)
 
     *mem = 0;
     asm("callq *%1" : "+m"(*mem) : "r"(insn_ram));
-    report("movb $imm, 0(%%rip)", *mem == 0x10000);
+    report(*mem == 0x10000, "movb $imm, 0(%%rip)");
 }
 
 static void test_shld_shrd(u32 *mem)
 {
     *mem = 0x12345678;
     asm("shld %2, %1, %0" : "+m"(*mem) : "r"(0xaaaaaaaaU), "c"((u8)3));
-    report("shld (cl)", *mem == ((0x12345678 << 3) | 5));
+    report(*mem == ((0x12345678 << 3) | 5), "shld (cl)");
     *mem = 0x12345678;
     asm("shrd %2, %1, %0" : "+m"(*mem) : "r"(0x55555555U), "c"((u8)3));
-    report("shrd (cl)", *mem == ((0x12345678 >> 3) | (5u << 29)));
+    report(*mem == ((0x12345678 >> 3) | (5u << 29)), "shrd (cl)");
 }
 
 static void test_cmov(u32 *mem)

@@ -733,7 +734,7 @@ static void test_cmov(u32 *mem)
 	     "cmovnel (%[mem]), %%eax\n\t"
 	     "movq %%rax, %[val]\n\t"
 	     : [val]"=r"(val) : [mem]"r"(mem) : "%rax", "cc");
-	report("cmovnel", val == 0x12345678ul);
+	report(val == 0x12345678ul, "cmovnel");
 }
 
 static unsigned long rip_advance;

@@ -760,7 +761,7 @@ static void test_mmx_movq_mf(uint64_t *mem)
     asm(KVM_FEP "movq_start: movq %mm0, (%rax); movq_end:");
     /* exit MMX mode */
     asm volatile("fnclex; emms");
-    report("movq mmx generates #MF", exceptions == 1);
+    report(exceptions == 1, "movq mmx generates #MF");
     handle_exception(MF_VECTOR, 0);
 }
 

@@ -774,7 +775,7 @@ static void test_jmp_noncanonical(uint64_t *mem)
 	rip_advance = &nc_jmp_end - &nc_jmp_start;
 	handle_exception(GP_VECTOR, advance_rip_and_note_exception);
 	asm volatile ("nc_jmp_start: jmp *%0; nc_jmp_end:" : : "m"(*mem));
-	report("jump to non-canonical address", exceptions == 1);
+	report(exceptions == 1, "jump to non-canonical address");
 	handle_exception(GP_VECTOR, 0);
 }
 

@@ -783,7 +784,7 @@ static void test_movabs(uint64_t *mem)
     /* mov $0x9090909090909090, %rcx */
     unsigned long rcx;
     asm(KVM_FEP "mov $0x9090909090909090, %0" : "=c" (rcx) : "0" (0));
-    report("64-bit mov imm2", rcx == 0x9090909090909090);
+    report(rcx == 0x9090909090909090, "64-bit mov imm2");
 }
 
 static void test_smsw_reg(uint64_t *mem)

@@ -793,14 +794,14 @@ static void test_smsw_reg(uint64_t *mem)
 	const unsigned long in_rax = 0x1234567890abcdeful;
 
 	asm(KVM_FEP "smsww %w0\n\t" : "=a" (rax) : "0" (in_rax));
-	report("16-bit smsw reg", (u16)rax == (u16)cr0 &&
-				  rax >> 16 == in_rax >> 16);
+	report((u16)rax == (u16)cr0 && rax >> 16 == in_rax >> 16,
+	       "16-bit smsw reg");
 
 	asm(KVM_FEP "smswl %k0\n\t" : "=a" (rax) : "0" (in_rax));
-	report("32-bit smsw reg", rax == (u32)cr0);
+	report(rax == (u32)cr0, "32-bit smsw reg");
 
 	asm(KVM_FEP "smswq %q0\n\t" : "=a" (rax) : "0" (in_rax));
-	report("64-bit smsw reg", rax == cr0);
+	report(rax == cr0, "64-bit smsw reg");
 }
 
 static void test_nop(uint64_t *mem)

@@ -808,7 +809,7 @@ static void test_nop(uint64_t *mem)
 	unsigned long rax;
 	const unsigned long in_rax = 0x1234567890abcdeful;
 	asm(KVM_FEP "nop\n\t" : "=a" (rax) : "0" (in_rax));
-	report("nop", rax == in_rax);
+	report(rax == in_rax, "nop");
 }
 
 static void test_mov_dr(uint64_t *mem)

@@ -819,7 +820,7 @@ static void test_mov_dr(uint64_t *mem)
 	unsigned long dr6_fixed_1 = rtm_support ? 0xfffe0ff0ul : 0xffff0ff0ul;
 	asm(KVM_FEP "movq %0, %%dr6\n\t"
 	    KVM_FEP "movq %%dr6, %0\n\t" : "=a" (rax) : "a" (in_rax));
-	report("mov_dr6", rax == dr6_fixed_1);
+	report(rax == dr6_fixed_1, "mov_dr6");
 }
 
 static void test_push16(uint64_t *mem)

@@ -834,7 +835,7 @@ static void test_push16(uint64_t *mem)
 			"movq %[rsp1], %%rsp\n\t" :
 			[rsp1]"=r"(rsp1), [rsp2]"=r"(rsp2), [r]"=r"(r)
 			: [v]"m"(*mem) : "memory");
-	report("push16", rsp1 == rsp2);
+	report(rsp1 == rsp2, "push16");
 }
 
 static void test_crosspage_mmio(volatile uint8_t *mem)

@@ -845,9 +846,9 @@ static void test_crosspage_mmio(volatile uint8_t *mem)
     mem[4095] = 0x99;
     mem[4096] = 0x77;
     asm volatile("mov %1, %0" : "=r"(w) : "m"(*pw) : "memory");
-    report("cross-page mmio read", w == 0x7799);
+    report(w == 0x7799, "cross-page mmio read");
     asm volatile("mov %1, %0" : "=m"(*pw) : "r"((uint16_t)0x88aa));
-    report("cross-page mmio write", mem[4095] == 0xaa && mem[4096] == 0x88);
+    report(mem[4095] == 0xaa && mem[4096] == 0x88, "cross-page mmio write");
 }
 
 static void test_string_io_mmio(volatile uint8_t *mem)

@@ -859,7 +860,7 @@ static void test_string_io_mmio(volatile uint8_t *mem)
 
 	asm volatile ("cld; rep insb" : : "d" (TESTDEV_IO_PORT), "D" (mmio), "c" (1024));
 
-	report("string_io_mmio", mmio[1023] == 0x99);
+	report(mmio[1023] == 0x99, "string_io_mmio");
 }
 
 /* kvm doesn't allow lidt/lgdt from mmio, so the test is disabled */

@@ -878,7 +879,8 @@ static void test_lgdt_lidt(volatile uint8_t *mem)
     sgdt(&fresh);
     lgdt(&orig);
     sti();
-    report("lgdt (long address)", orig.limit == fresh.limit && orig.base == fresh.base);
+    report(orig.limit == fresh.limit && orig.base == fresh.base,
+           "lgdt (long address)");
 
     sidt(&orig);
     *(struct descriptor_table_ptr *)mem = (struct descriptor_table_ptr) {

@@ -890,7 +892,8 @@ static void test_lgdt_lidt(volatile uint8_t *mem)
     sidt(&fresh);
     lidt(&orig);
     sti();
-    report("lidt (long address)", orig.limit == fresh.limit && orig.base == fresh.base);
+    report(orig.limit == fresh.limit && orig.base == fresh.base,
+           "lidt (long address)");
 }
 #endif
 

@@ -909,14 +912,15 @@ static void test_sreg(volatile uint16_t *mem)
     // check for null segment load
     *mem = 0;
     asm volatile("mov %0, %%ss" : : "m"(*mem));
-    report("mov null, %%ss", read_ss() == 0);
+    report(read_ss() == 0, "mov null, %%ss");
 
     // check for exception when ss.rpl != cpl on null segment load
     exceptions = 0;
     handle_exception(GP_VECTOR, ss_bad_rpl);
     *mem = 3;
     asm volatile("mov %0, %%ss; ss_bad_rpl_cont:" : : "m"(*mem));
-    report("mov null, %%ss (with ss.rpl != cpl)", exceptions == 1 && read_ss() == 0);
+    report(exceptions == 1 && read_ss() == 0,
+           "mov null, %%ss (with ss.rpl != cpl)");
     handle_exception(GP_VECTOR, 0);
     write_ss(ss);
 }

@@ -941,7 +945,7 @@ static void test_lldt(volatile uint16_t *mem)
     asm volatile("lldt %0" : : "m"(*mem));
     lgdt(&orig_gdt);
     sti();
-    report("lldt", sldt() == *mem);
+    report(sldt() == *mem, "lldt");
 }
 #endif
 

@@ -958,32 +962,32 @@ static void test_ltr(volatile uint16_t *mem)
     *trp &= ~busy_mask;
     *mem = tr;
     asm volatile("ltr %0" : : "m"(*mem) : "memory");
-    report("ltr", str() == tr && (*trp & busy_mask));
+    report(str() == tr && (*trp & busy_mask), "ltr");
 }
 
 static void test_simplealu(u32 *mem)
 {
     *mem = 0x1234;
     asm("or %1, %0" : "+m"(*mem) : "r"(0x8001));
-    report("or", *mem == 0x9235);
+    report(*mem == 0x9235, "or");
     asm("add %1, %0" : "+m"(*mem) : "r"(2));
-    report("add", *mem == 0x9237);
+    report(*mem == 0x9237, "add");
     asm("xor %1, %0" : "+m"(*mem) : "r"(0x1111));
-    report("xor", *mem == 0x8326);
+    report(*mem == 0x8326, "xor");
     asm("sub %1, %0" : "+m"(*mem) : "r"(0x26));
-    report("sub", *mem == 0x8300);
+    report(*mem == 0x8300, "sub");
     asm("clc; adc %1, %0" : "+m"(*mem) : "r"(0x100));
-    report("adc(0)", *mem == 0x8400);
+    report(*mem == 0x8400, "adc(0)");
     asm("stc; adc %1, %0" : "+m"(*mem) : "r"(0x100));
-    report("adc(0)", *mem == 0x8501);
+    report(*mem == 0x8501, "adc(0)");
     asm("clc; sbb %1, %0" : "+m"(*mem) : "r"(0));
-    report("sbb(0)", *mem == 0x8501);
+    report(*mem == 0x8501, "sbb(0)");
     asm("stc; sbb %1, %0" : "+m"(*mem) : "r"(0));
-    report("sbb(1)", *mem == 0x8500);
+    report(*mem == 0x8500, "sbb(1)");
     asm("and %1, %0" : "+m"(*mem) : "r"(0xfe77));
-    report("and", *mem == 0x8400);
+    report(*mem == 0x8400, "and");
     asm("test %1, %0" : "+m"(*mem) : "r"(0xf000));
-    report("test", *mem == 0x8400);
+    report(*mem == 0x8400, "test");
 }
 
 static void illegal_movbe_handler(struct ex_regs *regs)

@@ -1005,7 +1009,7 @@ static void test_illegal_movbe(void)
 	handle_exception(UD_VECTOR, illegal_movbe_handler);
 	asm volatile(".byte 0x0f; .byte 0x38; .byte 0xf0; .byte 0xc0;\n\t"
 		     " bad_movbe_cont:" : : : "rax");
-	report("illegal movbe", exceptions == 1);
+	report(exceptions == 1, "illegal movbe");
 	handle_exception(UD_VECTOR, 0);
 }
 

@@ -1042,7 +1046,7 @@ int main(void)
 		     : [t2]"=r"(t2)
 		     : [t1]"r"(t1), [mem]"r"(mem)
 		     : "memory");
-	report("mov reg, r/m (1)", t2 == 0x123456789abcdef);
+	report(t2 == 0x123456789abcdef, "mov reg, r/m (1)");
 
 	test_simplealu(mem);
 	test_cmps(mem);

x86/eventinj.c +15 -15

index c38848e..aa7c233 100644
@@ -226,7 +226,7 @@ int main(void)
 	asm volatile ("divl %3": "=a"(res)
 		      : "d"(0), "a"(1500), "m"(test_divider));
 	printf("Result is %d\n", res);
-	report("DE exception", res == 150);
+	report(res == 150, "DE exception");
 
 	/* generate soft exception (BP) that will fault on IDT and stack */
 	test_count = 0;

@@ -236,7 +236,7 @@ int main(void)
 	flush_stack();
 	asm volatile ("int $3");
 	printf("After int 3\n");
-	report("BP exception", test_count == 1);
+	report(test_count == 1, "BP exception");
 
 #ifndef __x86_64__
 	/* generate soft exception (OF) that will fault on IDT */

@@ -246,7 +246,7 @@ int main(void)
 	printf("Try into\n");
 	asm volatile ("addb $127, %b0\ninto"::"a"(127));
 	printf("After into\n");
-	report("OF exception", test_count == 1);
+	report(test_count == 1, "OF exception");
 
 	/* generate soft exception (OF) using two bit instruction that will
 	   fault on IDT */

@@ -256,7 +256,7 @@ int main(void)
 	printf("Try into\n");
 	asm volatile ("addb $127, %b0\naddr16 into"::"a"(127));
 	printf("After into\n");
-	report("2 byte OF exception", test_count == 1);
+	report(test_count == 1, "2 byte OF exception");
 #endif
 
 	/* generate HW interrupt that will fault on IDT */

@@ -268,7 +268,7 @@ int main(void)
 	io_delay();
 	irq_disable();
 	printf("After vec 33 to self\n");
-	report("vec 33", test_count == 1);
+	report(test_count == 1, "vec 33");
 
 	/* generate soft interrupt that will fault on IDT and stack */
 	test_count = 0;

@@ -277,7 +277,7 @@ int main(void)
 	flush_stack();
 	asm volatile ("int $33");
 	printf("After int $33\n");
-	report("int $33", test_count == 1);
+	report(test_count == 1, "int $33");
 
 	/* Inject two HW interrupt than open iterrupt windows. Both interrupt
 	   will fault on IDT access */

@@ -291,7 +291,7 @@ int main(void)
 	asm volatile("nop");
 	irq_disable();
 	printf("After vec 32 and 33 to self\n");
-	report("vec 32/33", test_count == 2);
+	report(test_count == 2, "vec 32/33");
 
 
 	/* Inject HW interrupt, do sti and than (while in irq shadow) inject

@@ -306,7 +306,7 @@ int main(void)
 	asm volatile ("sti; int $33");
 	irq_disable();
 	printf("After vec 32 and int $33\n");
-	report("vec 32/int $33", test_count == 2);
+	report(test_count == 2, "vec 32/int $33");
 
 	/* test that TPR is honored */
 	test_count = 0;

@@ -320,7 +320,7 @@ int main(void)
 	io_delay();
 	apic_write(APIC_TASKPRI, 0x2 << 4);
 	printf("After 33/62 TPR test\n");
-	report("TPR", test_count == 1);
+	report(test_count == 1, "TPR");
 	apic_write(APIC_TASKPRI, 0x0);
 	while(test_count != 2); /* wait for second irq */
 	irq_disable();

@@ -334,7 +334,7 @@ int main(void)
 	flush_stack();
 	asm volatile ("int $33");
 	printf("After int33\n");
-	report("NP exception", test_count == 2);
+	report(test_count == 2, "NP exception");
 
 	/* generate NMI that will fault on IDT */
 	test_count = 0;

@@ -349,7 +349,7 @@ int main(void)
 	irq_enable();
 	asm volatile ("nop");
 	irq_disable();
-	report("NMI", test_count == 2);
+	report(test_count == 2, "NMI");
 
 	/* generate NMI that will fault on IRET */
 	printf("Before NMI IRET test\n");

@@ -364,7 +364,7 @@ int main(void)
 	asm volatile ("nop");
 	irq_disable();
 	printf("After NMI to self\n");
-	report("NMI", test_count == 2);
+	report(test_count == 2, "NMI");
 	stack_phys = (ulong)virt_to_phys(alloc_page());
 	stack_va = alloc_vpage();
 

@@ -384,7 +384,7 @@ int main(void)
 		      : "d"(0), "a"(1500), "m"(test_divider));
 	restore_stack();
 	printf("Result is %d\n", res);
-	report("DE PF exceptions", res == 150);
+	report(res == 150, "DE PF exceptions");
 
 	/* Generate NP and PF exceptions serially */
 	printf("Before NP test\n");

@@ -402,7 +402,7 @@ int main(void)
 	asm volatile ("int $33");
 	restore_stack();
 	printf("After int33\n");
-	report("NP PF exceptions", test_count == 2);
+	report(test_count == 2, "NP PF exceptions");
 
 	pt = alloc_page();
 	cr3 = (void*)read_cr3();

@@ -426,7 +426,7 @@ int main(void)
 	asm volatile("int $33");
 	restore_stack();
 	printf("After int 33 with shadowed stack\n");
-	report("int 33 with shadowed stack", test_count == 1);
+	report(test_count == 1, "int 33 with shadowed stack");
 
 	return report_summary();
 }

x86/hypercall.c +4 -2

index 37fec8e..7fbbf30 100644
@@ -71,10 +71,12 @@ int main(int ac, char **av)
 	topmost[4093] = 0x0f;
 	topmost[4094] = 0x01;
 	topmost[4095] = 0xc1;
-	report("VMCALL on edge of canonical address space (intel)", test_edge());
+	report(test_edge(),
+	       "VMCALL on edge of canonical address space (intel)");
 
 	topmost[4095] = 0xd9;
-	report("VMMCALL on edge of canonical address space (AMD)", test_edge());
+	report(test_edge(),
+	       "VMMCALL on edge of canonical address space (AMD)");
 #endif
 
 	return report_summary();

x86/hyperv_clock.c +5 -4

index d57591f..99775a9 100644
@@ -112,7 +112,7 @@ static void check_test(int ncpus)
 	for (i = ncpus - 1; i >= 0; i--)
 		pass &= ok[i];
 
-	report("TSC reference precision test", pass);
+	report(pass, "TSC reference precision test");
 }
 
 static void hv_perf_test(void *data)

@@ -159,8 +159,8 @@ int main(int ac, char **av)
 
 	hv_clock = alloc_page();
 	wrmsr(HV_X64_MSR_REFERENCE_TSC, (u64)(uintptr_t)hv_clock | 1);
-	report("MSR value after enabling",
-	       rdmsr(HV_X64_MSR_REFERENCE_TSC) == ((u64)(uintptr_t)hv_clock | 1));
+	report(rdmsr(HV_X64_MSR_REFERENCE_TSC) == ((u64)(uintptr_t)hv_clock | 1),
+	       "MSR value after enabling");
 
 	hvclock_get_time_values(&shadow, hv_clock);
 	if (shadow.tsc_sequence == 0 || shadow.tsc_sequence == 0xFFFFFFFF) {

@@ -189,7 +189,8 @@ int main(int ac, char **av)
 	perf_test(ncpus);
 
 	wrmsr(HV_X64_MSR_REFERENCE_TSC, 0LL);
-	report("MSR value after disabling", rdmsr(HV_X64_MSR_REFERENCE_TSC) == 0);
+	report(rdmsr(HV_X64_MSR_REFERENCE_TSC) == 0,
+	       "MSR value after disabling");
 
 	return nerr > 0 ? 1 : 0;
 }

x86/hyperv_connections.c +14 -14

index 8eade41..55cc033 100644
@@ -292,36 +292,36 @@ int main(int ac, char **av)
 		on_cpu(i, setup_cpu, (void *)read_cr3());
 
 	ncpus_ok = run_test(ncpus, 0, WAIT_CYCLES, do_msg, msg_ok);
-	report("send message to self: %d/%d",
-	       ncpus_ok == ncpus, ncpus_ok, ncpus);
+	report(ncpus_ok == ncpus, "send message to self: %d/%d", ncpus_ok,
+	       ncpus);
 
 	run_test(ncpus, 0, 0, clear_msg, NULL);
 
 	ncpus_ok = run_test(ncpus, 1, WAIT_CYCLES, do_msg, msg_ok);
-	report("send message to another cpu: %d/%d",
-	       ncpus_ok == ncpus, ncpus_ok, ncpus);
+	report(ncpus_ok == ncpus, "send message to another cpu: %d/%d",
+	       ncpus_ok, ncpus);
 
 	ncpus_ok = run_test(ncpus, 1, WAIT_CYCLES, do_msg, msg_busy);
-	report("send message to busy slot: %d/%d",
-	       ncpus_ok == ncpus, ncpus_ok, ncpus);
+	report(ncpus_ok == ncpus, "send message to busy slot: %d/%d",
+	       ncpus_ok, ncpus);
 
 	ncpus_ok = run_test(ncpus, 0, WAIT_CYCLES, clear_msg, msg_ok);
-	report("receive pending message: %d/%d",
-	       ncpus_ok == ncpus, ncpus_ok, ncpus);
+	report(ncpus_ok == ncpus, "receive pending message: %d/%d", ncpus_ok,
+	       ncpus);
 
 	ncpus_ok = run_test(ncpus, 0, WAIT_CYCLES, do_evt, evt_ok);
-	report("signal event on self: %d/%d",
-	       ncpus_ok == ncpus, ncpus_ok, ncpus);
+	report(ncpus_ok == ncpus, "signal event on self: %d/%d", ncpus_ok,
+	       ncpus);
 
 	run_test(ncpus, 0, 0, clear_evt, NULL);
 
 	ncpus_ok = run_test(ncpus, 1, WAIT_CYCLES, do_evt, evt_ok);
-	report("signal event on another cpu: %d/%d",
-	       ncpus_ok == ncpus, ncpus_ok, ncpus);
+	report(ncpus_ok == ncpus, "signal event on another cpu: %d/%d",
+	       ncpus_ok, ncpus);
 
 	ncpus_ok = run_test(ncpus, 1, WAIT_CYCLES, do_evt, evt_busy);
-	report("signal event already set: %d/%d",
-	       ncpus_ok == ncpus, ncpus_ok, ncpus);
+	report(ncpus_ok == ncpus, "signal event already set: %d/%d", ncpus_ok,
+	       ncpus);
 
 	for (i = 0; i < ncpus; i++)
 		on_cpu(i, teardown_cpu, NULL);

x86/hyperv_stimer.c +15 -13

index b6332fd..ddfc844 100644
@@ -96,7 +96,7 @@ static void process_stimer_msg(struct svcpu *svcpu,
 
     if (msg->header.message_type != HVMSG_TIMER_EXPIRED &&
         msg->header.message_type != HVMSG_NONE) {
-        report("invalid Hyper-V SynIC msg type", false);
+        report(false, "invalid Hyper-V SynIC msg type");
         report_summary();
         abort();
     }

@@ -106,7 +106,7 @@ static void process_stimer_msg(struct svcpu *svcpu,
     }
 
     if (msg->header.payload_size < sizeof(*payload)) {
-        report("invalid Hyper-V SynIC msg payload size", false);
+        report(false, "invalid Hyper-V SynIC msg payload size");
         report_summary();
         abort();
     }

@@ -114,7 +114,7 @@ static void process_stimer_msg(struct svcpu *svcpu,
     /* Now process timer expiration message */
 
     if (payload->timer_index >= ARRAY_SIZE(svcpu->timer)) {
-        report("invalid Hyper-V SynIC timer index", false);
+        report(false, "invalid Hyper-V SynIC timer index");
         report_summary();
         abort();
     }

@@ -234,7 +234,7 @@ static void stimer_test_periodic(int vcpu, struct stimer *timer1,
            (atomic_read(&timer2->fire_count) < 1000)) {
         pause();
     }
-    report("Hyper-V SynIC periodic timers test vcpu %d", true, vcpu);
+    report(true, "Hyper-V SynIC periodic timers test vcpu %d", vcpu);
     stimer_shutdown(timer1);
     stimer_shutdown(timer2);
 }

@@ -246,7 +246,7 @@ static void stimer_test_one_shot(int vcpu, struct stimer *timer)
     while (atomic_read(&timer->fire_count) < 1) {
         pause();
     }
-    report("Hyper-V SynIC one-shot test vcpu %d", true, vcpu);
+    report(true, "Hyper-V SynIC one-shot test vcpu %d", vcpu);
     stimer_shutdown(timer);
 }
 

@@ -257,7 +257,8 @@ static void stimer_test_auto_enable_one_shot(int vcpu, struct stimer *timer)
     while (atomic_read(&timer->fire_count) < 1) {
         pause();
     }
-    report("Hyper-V SynIC auto-enable one-shot timer test vcpu %d", true, vcpu);
+    report(true, "Hyper-V SynIC auto-enable one-shot timer test vcpu %d",
+           vcpu);
     stimer_shutdown(timer);
 }
 

@@ -268,7 +269,8 @@ static void stimer_test_auto_enable_periodic(int vcpu, struct stimer *timer)
     while (atomic_read(&timer->fire_count) < 1000) {
         pause();
     }
-    report("Hyper-V SynIC auto-enable periodic timer test vcpu %d", true, vcpu);
+    report(true, "Hyper-V SynIC auto-enable periodic timer test vcpu %d",
+           vcpu);
     stimer_shutdown(timer);
 }
 

@@ -286,8 +288,8 @@ static void stimer_test_one_shot_busy(int vcpu, struct stimer *timer)
         rmb();
     while (!msg->header.message_flags.msg_pending);
 
-    report("no timer fired while msg slot busy: vcpu %d",
-           !atomic_read(&timer->fire_count), vcpu);
+    report(!atomic_read(&timer->fire_count),
+           "no timer fired while msg slot busy: vcpu %d", vcpu);
 
     msg->header.message_type = HVMSG_NONE;
     wmb();

@@ -296,7 +298,7 @@ static void stimer_test_one_shot_busy(int vcpu, struct stimer *timer)
     while (atomic_read(&timer->fire_count) < 1) {
         pause();
     }
-    report("timer resumed when msg slot released: vcpu %d", true, vcpu);
+    report(true, "timer resumed when msg slot released: vcpu %d", vcpu);
 
     stimer_shutdown(timer);
 }

@@ -354,17 +356,17 @@ int main(int ac, char **av)
 {
 
     if (!synic_supported()) {
-        report("Hyper-V SynIC is not supported", true);
+        report(true, "Hyper-V SynIC is not supported");
         goto done;
     }
 
     if (!stimer_supported()) {
-        report("Hyper-V SynIC timers are not supported", true);
+        report(true, "Hyper-V SynIC timers are not supported");
         goto done;
     }
 
     if (!hv_time_ref_counter_supported()) {
-        report("Hyper-V time reference counter is not supported", true);
+        report(true, "Hyper-V time reference counter is not supported");
         goto done;
     }
 

x86/hyperv_synic.c +2 -2

index 9a5f53f..b6c7104 100644
@@ -90,7 +90,7 @@ static void synic_test_prepare(void *ctx)
     }
     r = rdmsr(HV_X64_MSR_EOM);
     if (r != 0) {
-        report("Hyper-V SynIC test, EOM read %#" PRIx64, false, r);
+        report(false, "Hyper-V SynIC test, EOM read %#" PRIx64, r);
         return;
     }
 

@@ -177,7 +177,7 @@ int main(int ac, char **av)
             ok &= atomic_read(&isr_enter_count[i]) == 16;
         }
 
-        report("Hyper-V SynIC test", ok);
+        report(ok, "Hyper-V SynIC test");
     } else {
         printf("Hyper-V SynIC is not supported");
     }

x86/idt_test.c +4 -4

index 844c860..aa29733 100644
@@ -31,11 +31,11 @@ int main(void)
     printf("Starting IDT test\n");
     setup_idt();
     r = test_gp(&rflags_rf);
-    report("Testing #GP", r == GP_VECTOR);
-    report("Testing #GP rflags.rf", rflags_rf);
+    report(r == GP_VECTOR, "Testing #GP");
+    report(rflags_rf, "Testing #GP rflags.rf");
     r = test_ud2(&rflags_rf);
-    report("Testing #UD", r == UD_VECTOR);
-    report("Testing #UD rflags.rf", rflags_rf);
+    report(r == UD_VECTOR, "Testing #UD");
+    report(rflags_rf, "Testing #UD rflags.rf");
 
     return report_summary();
 }

x86/intel-iommu.c +13 -12

index f24170d..25feec0 100644
@@ -56,7 +56,7 @@ static void vtd_test_dmar(void)
 	 * Check data match between 0-3 bytes and 4-7 bytes of the
 	 * page.
 	 */
-	report(VTD_TEST_DMAR_4B, *((uint32_t *)page + 1) == DMA_TEST_WORD);
+	report(*((uint32_t *)page + 1) == DMA_TEST_WORD, VTD_TEST_DMAR_4B);
 
 	free_page(page);
 

@@ -102,7 +102,7 @@ static void vtd_test_ir(void)
 	edu_reg_writel(dev, EDU_REG_INTR_RAISE, 0);
 
 	/* We are good as long as we reach here */
-	report(VTD_TEST_IR_IOAPIC, edu_intr_recved == true);
+	report(edu_intr_recved == true, VTD_TEST_IR_IOAPIC);
 
 	/*
 	 * Setup EDU PCI device MSI, using interrupt remapping. By

@@ -125,7 +125,7 @@ static void vtd_test_ir(void)
 		cpu_relax();
 
 	/* We are good as long as we reach here */
-	report(VTD_TEST_IR_MSI, edu_intr_recved == true);
+	report(edu_intr_recved == true, VTD_TEST_IR_MSI);
 
 	report_prefix_pop();
 }

@@ -139,15 +139,16 @@ int main(int argc, char *argv[])
 
 	report_prefix_push("vtd_init");
 
-	report("fault status check", vtd_readl(DMAR_FSTS_REG) == 0);
-	report("QI enablement", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_QI);
-	report("DMAR table setup", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_ROOT);
-	report("IR table setup", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_IR_TABLE);
-	report("DMAR enablement", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_DMAR);
-	report("IR enablement", vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_IR);
-	report("DMAR support 39 bits address width",
-	       vtd_readq(DMAR_CAP_REG) & VTD_CAP_SAGAW);
-	report("DMAR support huge pages", vtd_readq(DMAR_CAP_REG) & VTD_CAP_SLLPS);
+	report(vtd_readl(DMAR_FSTS_REG) == 0, "fault status check");
+	report(vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_QI, "QI enablement");
+	report(vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_ROOT, "DMAR table setup");
+	report(vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_IR_TABLE, "IR table setup");
+	report(vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_DMAR, "DMAR enablement");
+	report(vtd_readl(DMAR_GSTS_REG) & VTD_GCMD_IR, "IR enablement");
+	report(vtd_readq(DMAR_CAP_REG) & VTD_CAP_SAGAW,
+	       "DMAR support 39 bits address width");
+	report(vtd_readq(DMAR_CAP_REG) & VTD_CAP_SLLPS,
+	       "DMAR support huge pages");
 
 	report_prefix_pop();
 

x86/ioapic.c +28 -29

index c32dabd..c3083a8 100644
@@ -22,8 +22,8 @@ static void ioapic_reg_version(void)
 	data_write = data_read ^ 0xffffffff;
 
 	ioapic_write_reg(version_offset, data_write);
-	report("version register read only test",
-	       data_read == ioapic_read_reg(version_offset));
+	report(data_read == ioapic_read_reg(version_offset),
+	       "version register read only test");
 }
 
 static void ioapic_reg_id(void)

@@ -38,8 +38,7 @@ static void ioapic_reg_id(void)
 	ioapic_write_reg(id_offset, data_write);
 
 	diff = data_read ^ ioapic_read_reg(id_offset);
-	report("id register only bits [24:27] writable",
-	       diff == 0x0f000000);
+	report(diff == 0x0f000000, "id register only bits [24:27] writable");
 }
 
 static void ioapic_arbitration_id(void)

@@ -52,12 +51,12 @@ static void ioapic_arbitration_id(void)
 	write = 0x0f000000;
 
 	ioapic_write_reg(id_offset, write);
-	report("arbitration register set by id",
-	       ioapic_read_reg(arb_offset) == write);
+	report(ioapic_read_reg(arb_offset) == write,
+	       "arbitration register set by id");
 
 	ioapic_write_reg(arb_offset, 0x0);
-	report("arbtration register read only",
-               ioapic_read_reg(arb_offset) == write);
+	report(ioapic_read_reg(arb_offset) == write,
+	       "arbtration register read only");
 }
 
 static volatile int g_isr_76;

@@ -74,7 +73,7 @@ static void test_ioapic_edge_intr(void)
 	ioapic_set_redir(0x0e, 0x76, TRIGGER_EDGE);
 	toggle_irq_line(0x0e);
 	asm volatile ("nop");
-	report("edge triggered intr", g_isr_76 == 1);
+	report(g_isr_76 == 1, "edge triggered intr");
 }
 
 static volatile int g_isr_77;

@@ -92,7 +91,7 @@ static void test_ioapic_level_intr(void)
 	ioapic_set_redir(0x0e, 0x77, TRIGGER_LEVEL);
 	set_irq_line(0x0e, 1);
 	asm volatile ("nop");
-	report("level triggered intr", g_isr_77 == 1);
+	report(g_isr_77 == 1, "level triggered intr");
 }
 
 static int g_78, g_66, g_66_after_78;

@@ -125,8 +124,8 @@ static void test_ioapic_simultaneous(void)
 	toggle_irq_line(0x0e);
 	irq_enable();
 	asm volatile ("nop");
-	report("ioapic simultaneous edge interrupts",
-	       g_66 && g_78 && g_66_after_78 && g_66_rip == g_78_rip);
+	report(g_66 && g_78 && g_66_after_78 && g_66_rip == g_78_rip,
+	       "ioapic simultaneous edge interrupts");
 }
 
 static volatile int g_tmr_79 = -1;

@@ -147,8 +146,8 @@ static void test_ioapic_edge_tmr(bool expected_tmr_before)
 	tmr_before = apic_read_bit(APIC_TMR, 0x79);
 	toggle_irq_line(0x0e);
 	asm volatile ("nop");
-	report("TMR for ioapic edge interrupts (expected %s)",
-	       tmr_before == expected_tmr_before && !g_tmr_79,
+	report(tmr_before == expected_tmr_before && !g_tmr_79,
+	       "TMR for ioapic edge interrupts (expected %s)",
 	       expected_tmr_before ? "true" : "false");
 }
 

@@ -161,8 +160,8 @@ static void test_ioapic_level_tmr(bool expected_tmr_before)
 	tmr_before = apic_read_bit(APIC_TMR, 0x79);
 	set_irq_line(0x0e, 1);
 	asm volatile ("nop");
-	report("TMR for ioapic level interrupts (expected %s)",
-	       tmr_before == expected_tmr_before && g_tmr_79,
+	report(tmr_before == expected_tmr_before && g_tmr_79,
+	       "TMR for ioapic level interrupts (expected %s)",
 	       expected_tmr_before ? "true" : "false");
 }
 

@@ -187,8 +186,8 @@ static void test_ioapic_edge_tmr_smp(bool expected_tmr_before)
 	i = 0;
 	while(g_tmr_79 == -1) i++;
 	printf("%d iterations before interrupt received\n", i);
-	report("TMR for ioapic edge interrupts (expected %s)",
-	       tmr_before == expected_tmr_before && !g_tmr_79,
+	report(tmr_before == expected_tmr_before && !g_tmr_79,
+	       "TMR for ioapic edge interrupts (expected %s)",
 	       expected_tmr_before ? "true" : "false");
 }
 

@@ -212,8 +211,8 @@ static void test_ioapic_level_tmr_smp(bool expected_tmr_before)
 	i = 0;
 	while(g_tmr_79 == -1) i++;
 	printf("%d iterations before interrupt received\n", i);
-	report("TMR for ioapic level interrupts (expected %s)",
-	       tmr_before == expected_tmr_before && g_tmr_79,
+	report(tmr_before == expected_tmr_before && g_tmr_79,
+	       "TMR for ioapic level interrupts (expected %s)",
 	       expected_tmr_before ? "true" : "false");
 }
 

@@ -236,7 +235,7 @@ static void test_ioapic_level_coalesce(void)
 	ioapic_set_redir(0x0e, 0x98, TRIGGER_LEVEL);
 	set_irq_line(0x0e, 1);
 	asm volatile ("nop");
-	report("coalesce simultaneous level interrupts", g_isr_98 == 1);
+	report(g_isr_98 == 1, "coalesce simultaneous level interrupts");
 }
 
 static int g_isr_99;

@@ -255,7 +254,7 @@ static void test_ioapic_level_sequential(void)
 	set_irq_line(0x0e, 1);
 	set_irq_line(0x0e, 1);
 	asm volatile ("nop");
-	report("sequential level interrupts", g_isr_99 == 2);
+	report(g_isr_99 == 2, "sequential level interrupts");
 }
 
 static volatile int g_isr_9a;

@@ -287,7 +286,7 @@ static void test_ioapic_level_retrigger(void)
 
 	asm volatile ("sti");
 
-	report("retriggered level interrupts without masking", g_isr_9a == 2);
+	report(g_isr_9a == 2, "retriggered level interrupts without masking");
 }
 
 static volatile int g_isr_81;

@@ -309,13 +308,13 @@ static void test_ioapic_edge_mask(void)
 	set_irq_line(0x0e, 0);
 
 	asm volatile ("nop");
-	report("masked level interrupt", g_isr_81 == 0);
+	report(g_isr_81 == 0, "masked level interrupt");
 
 	set_mask(0x0e, false);
 	set_irq_line(0x0e, 1);
 
 	asm volatile ("nop");
-	report("unmasked level interrupt", g_isr_81 == 1);
+	report(g_isr_81 == 1, "unmasked level interrupt");
 }
 
 static volatile int g_isr_82;

@@ -336,12 +335,12 @@ static void test_ioapic_level_mask(void)
 	set_irq_line(0x0e, 1);
 
 	asm volatile ("nop");
-	report("masked level interrupt", g_isr_82 == 0);
+	report(g_isr_82 == 0, "masked level interrupt");
 
 	set_mask(0x0e, false);
 
 	asm volatile ("nop");
-	report("unmasked level interrupt", g_isr_82 == 1);
+	report(g_isr_82 == 1, "unmasked level interrupt");
 }
 
 static volatile int g_isr_83;

@@ -362,7 +361,7 @@ static void test_ioapic_level_retrigger_mask(void)
 	asm volatile ("nop");
 	set_mask(0x0e, false);
 	asm volatile ("nop");
-	report("retriggered level interrupts with mask", g_isr_83 == 2);
+	report(g_isr_83 == 2, "retriggered level interrupts with mask");
 
 	set_irq_line(0x0e, 0);
 	set_mask(0x0e, false);

@@ -402,7 +401,7 @@ static void test_ioapic_self_reconfigure(void)
 	ioapic_write_redir(0xe, e);
 	set_irq_line(0x0e, 1);
 	e = ioapic_read_redir(0xe);
-	report("Reconfigure self", g_isr_84 == 1 && e.remote_irr == 0);
+	report(g_isr_84 == 1 && e.remote_irr == 0, "Reconfigure self");
 }
 
 

x86/memory.c +9 -8

index 4f8949b..22c50c9 100644
@@ -36,21 +36,21 @@ int main(int ac, char **av)
 	expected = !this_cpu_has(X86_FEATURE_CLFLUSH); /* CLFLUSH */
 	ud = 0;
 	asm volatile("clflush (%0)" : : "b" (&target));
-	report("clflush (%s)", ud == expected, expected ? "ABSENT" : "present");
+	report(ud == expected, "clflush (%s)", expected ? "ABSENT" : "present");
 
 	expected = !this_cpu_has(X86_FEATURE_XMM); /* SSE */
 	ud = 0;
 	asm volatile("sfence");
-	report("sfence (%s)", ud == expected, expected ? "ABSENT" : "present");
+	report(ud == expected, "sfence (%s)", expected ? "ABSENT" : "present");
 
 	expected = !this_cpu_has(X86_FEATURE_XMM2); /* SSE2 */
 	ud = 0;
 	asm volatile("lfence");
-	report("lfence (%s)", ud == expected, expected ? "ABSENT" : "present");
+	report(ud == expected, "lfence (%s)", expected ? "ABSENT" : "present");
 
 	ud = 0;
 	asm volatile("mfence");
-	report("mfence (%s)", ud == expected, expected ? "ABSENT" : "present");
+	report(ud == expected, "mfence (%s)", expected ? "ABSENT" : "present");
 
 	/* 4-byte instructions: */
 	isize = 4;

@@ -59,26 +59,27 @@ int main(int ac, char **av)
 	ud = 0;
 	/* clflushopt (%rbx): */
 	asm volatile(".byte 0x66, 0x0f, 0xae, 0x3b" : : "b" (&target));
-	report("clflushopt (%s)", ud == expected, expected ? "ABSENT" : "present");
+	report(ud == expected, "clflushopt (%s)",
+	       expected ? "ABSENT" : "present");
 
 	expected = !this_cpu_has(X86_FEATURE_CLWB); /* CLWB */
 	ud = 0;
 	/* clwb (%rbx): */
 	asm volatile(".byte 0x66, 0x0f, 0xae, 0x33" : : "b" (&target));
-	report("clwb (%s)", ud == expected, expected ? "ABSENT" : "present");
+	report(ud == expected, "clwb (%s)", expected ? "ABSENT" : "present");
 
 	ud = 0;
 	/* clwb requires a memory operand, the following is NOT a valid
 	 * CLWB instruction (modrm == 0xF0).
 	 */
 	asm volatile(".byte 0x66, 0x0f, 0xae, 0xf0");
-	report("invalid clwb", ud);
+	report(ud, "invalid clwb");
 
 	expected = !this_cpu_has(X86_FEATURE_PCOMMIT); /* PCOMMIT */
 	ud = 0;
 	/* pcommit: */
 	asm volatile(".byte 0x66, 0x0f, 0xae, 0xf8");
-	report("pcommit (%s)", ud == expected, expected ? "ABSENT" : "present");
+	report(ud == expected, "pcommit (%s)", expected ? "ABSENT" : "present");
 
 	return report_summary();
 }

x86/msr.c +1 -1

index beb321f..de2cb6d 100644
@@ -91,7 +91,7 @@ static void test_msr_rw(int msr_index, unsigned long long input, unsigned long l
         printf("testing %s: output = %#x:%#x expected = %#x:%#x\n", sptr,
[… more lines in the raw message]

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x86/pcid.c +5 -5

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x86/pku.c +13 -7

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x86/pmu.c +13 -12

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x86/rdpru.c +1 -1

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x86/smap.c +18 -10

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x86/smptest.c +1 -1

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x86/svm.c +7 -7

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x86/syscall.c +2 -2

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x86/taskswitch2.c +13 -13

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x86/tsc.c +2 -2

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x86/tsc_adjust.c +11 -11

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x86/tscdeadline_latency.c +1 -1

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x86/umip.c +12 -12

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x86/vmx.c +85 -82

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x86/vmx.h +5 -4

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x86/vmx_tests.c +315 -284

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x86/xsave.c +40 -40

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Signature · 1 line

2.18.1