NVIDIA Tegra20 CPUFreq driver major update
Subsystems (7)
v2 cover NVIDIA Tegra20 CPUFreq driver major update
Hello,
This series moves intermediate-clk handling from tegra20-cpufreq into tegra-clk driver, this allows us to switch to generic cpufreq-dt driver which brings voltage scaling, per-hardware OPPs and Tegra30 support out of the box. All boards need to adopt CPU OPPs in their device-trees in order to get cpufreq support. This series adds OPPs only to selective boards because there is assumption in a current device-trees that CPU voltage is set for 1GHz freq and this won't work for those CPUs that can go over 1GHz and thus require voltage regulators to be set up for voltage scaling support (CC'ed Marcel for Toradex boards). We could probably add delete-node for OPPs over 1GHz if there are not actively maintained boards.
NOTE(!): the voltage scaling functionality depends on a reviewed and yet unapplied series [0], thus [0] needs to be applied first.
[0] https://lkml.org/lkml/2019/7/25/892
Changelog:
v2: - Kept modularity of the tegra20-cpufreq as was requested by Viresh Kumar
in a review comment to v1.
- Added acks from Viresh Kumar.
- Added tested-by from Nicolas Chauvet to the "trimslice" patch. Nicolas told me on IRC that it works fine.
- Fixed compilation of the "Add custom CCLK implementation" patch. The error happened because v1 was based on top of yet unreviewed/unapplied patch "clk: tegra: divider: Support enable-bit for Super clocks". Thanks to Peter Geis for reporting the problem.
- Replaced Tegra30 "beaver" board with "cardhu-a04" because turned out that's what NVIDIA uses in the testing farm.
Dmitry Osipenko (17):
clk: tegra: Add custom CCLK implementation
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra20: Support custom CCLK implementation
clk: tegra30: Support custom CCLK implementation
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported
now)
ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
ARM: dts: tegra20: Add CPU clock
ARM: dts: tegra30: Add CPU clock
ARM: dts: tegra20: Add CPU Operating Performance Points
ARM: dts: tegra30: Add CPU Operating Performance Points
ARM: dts: tegra20: paz00: Set up voltage regulators for DVFS
ARM: dts: tegra20: paz00: Add CPU Operating Performance Points
ARM: dts: tegra20: trimslice: Add CPU Operating Performance Points
ARM: dts: tegra30: cardhu-a04: Set up voltage regulators for DVFS
ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
.../cpufreq/nvidia,tegra20-cpufreq.txt | 56 + .../boot/dts/tegra20-cpu-opp-microvolt.dtsi | 201 +++ arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 302 +++++ arch/arm/boot/dts/tegra20-paz00.dts | 41 +- arch/arm/boot/dts/tegra20-trimslice.dts | 11 + arch/arm/boot/dts/tegra20.dtsi | 2 + arch/arm/boot/dts/tegra30-cardhu-a04.dts | 48 + .../boot/dts/tegra30-cpu-opp-microvolt.dtsi | 801 +++++++++++ arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 1202 +++++++++++++++++ arch/arm/boot/dts/tegra30.dtsi | 4 + arch/arm/mach-tegra/tegra.c | 4 + drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-pll.c | 12 +- drivers/clk/tegra/clk-tegra-super-cclk.c | 164 +++ drivers/clk/tegra/clk-tegra20.c | 6 +- drivers/clk/tegra/clk-tegra30.c | 6 +- drivers/clk/tegra/clk.h | 12 + drivers/cpufreq/Kconfig.arm | 6 +- drivers/cpufreq/cpufreq-dt-platdev.c | 2 + drivers/cpufreq/tegra20-cpufreq.c | 211 +-- 20 files changed, 2916 insertions(+), 176 deletions(-) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt create mode 100644 arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi create mode 100644 arch/arm/boot/dts/tegra20-cpu-opp.dtsi create mode 100644 arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi create mode 100644 arch/arm/boot/dts/tegra30-cpu-opp.dtsi create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c
Signature · 1 line
2.23.0
PATCH v2 1/17 clk: tegra: Add custom CCLK implementation
CCLK stands for "CPU Clock", CPU core is running off CCLK. CCLK supports multiple parents and it has internal clock divider which uses clock skipping technique, meaning that CPU's voltage should correspond to the parent clock rate and not CCLK. PLLX is the main CCLK parent that provides clock rates above 1GHz and it has special property such that the CCLK's internal divider is set into bypass mode when PLLX is set as a parent for CCLK.
This patch forks generic Super Clock into CCLK implementation which takes into account all CCLK specifics. The proper CCLK implementation is needed by the upcoming Tegra20 CPUFreq driver update that will allow to utilize the generic cpufreq-dt driver by moving intermediate clock handling into the clock driver. Note that technically this all could be squashed into clk-super, but result will be messier.
Note that currently all CCLKLP bits are left in the clk-super.c and only CCLKG is supported by clk-tegra-super-cclk. It shouldn't be difficult to move the CCLKLP bits, but CCLKLP is not used by anything in kernel and thus better not to touch it for now.
--- drivers/clk/tegra/Makefile | 1 + drivers/clk/tegra/clk-tegra-super-cclk.c | 130 +++++++++++++++++++++++ drivers/clk/tegra/clk.h | 4 + 3 files changed, 135 insertions(+) create mode 100644 drivers/clk/tegra/clk-tegra-super-cclk.c
drivers/clk/tegra/Makefile +1 -0
@@ -14,6 +14,7 @@ obj-y += clk-tegra-audio.o obj-y += clk-tegra-periph.o obj-y += clk-tegra-pmc.o obj-y += clk-tegra-fixed.o +obj-y += clk-tegra-super-cclk.o obj-y += clk-tegra-super-gen4.o obj-$(CONFIG_TEGRA_CLK_EMC) += clk-emc.o obj-$(CONFIG_ARCH_TEGRA_2x_SOC) += clk-tegra20.o
drivers/clk/tegra/clk-tegra-super-cclk.c new file +130 -0
130 lines not on this page · raw message
drivers/clk/tegra/clk.h +4 -0
@@ -699,6 +699,10 @@ struct clk *tegra_clk_register_super_clk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +struct clk *tegra_clk_register_super_cclk (const char *name, +const char *const *parent_names,u8 num_parents, +unsigned long flags,void __iomem *reg,u8 clk_super_flags, +spinlock_t *lock);/** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
Signature · 1 line
2.23.0
PATCH v2 2/17 clk: tegra: pll: Add pre/post rate-change hooks
In reply to Dmitry OsipenkoThere is a need to temporarily re-parent CCLK away from PLLX if PLLX's rate is about to change. The newly introduced PLL pre/post rate-change hooks allow to handle such case.
--- drivers/clk/tegra/clk-pll.c | 12 +++++++++++- drivers/clk/tegra/clk.h | 6 ++++++ 2 files changed, 17 insertions(+), 1 deletion(-)
drivers/clk/tegra/clk-pll.c +11 -1
@@ -744,13 +744,19 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg, state =clk_pll_is_enabled (hw); +if (state && pll->params->pre_rate_change) { + ret = pll->params->pre_rate_change (); +if (WARN_ON (ret)) +return ret; + } +_get_pll_mnp (pll, &old_cfg);if (state && pll->params->defaults_set && pll->params->dyn_ramp && (cfg->m == old_cfg.m) && (cfg->p == old_cfg.p)) { ret = pll->params->dyn_ramp (pll, cfg);if (!ret) -return 0 ; + goto done; }if (state) {
@@ -772,6 +778,10 @@ static int _program_pll(struct clk_hw *hw, struct tegra_clk_pll_freq_table *cfg,pll_clk_start_ss (pll); } +done: +if (state && pll->params->post_rate_change) + pll->params->post_rate_change (); +return ret; }
drivers/clk/tegra/clk.h +6 -0
@@ -211,6 +211,10 @@ struct tegra_clk_pll;* disabled. * @dyn_ramp: Callback which can be used to define a custom * dynamic ramp function for a given PLL. +* @pre_rate_change: Callback which is invoked just before changing +* PLL's rate. +* @post_rate_change: Callback which is invoked right after changing +* PLL's rate. * * Flags: * TEGRA_PLL_USE_LOCK - This flag indicated to use lock bits for
@@ -287,6 +291,8 @@ struct tegra_clk_pll_params {void (*set_defaults)(struct tegra_clk_pll *pll);int (*dyn_ramp)(struct tegra_clk_pll *pll,struct tegra_clk_pll_freq_table *cfg); +int (*pre_rate_change)(void ); +void (*post_rate_change)(void ); };#define TEGRA_PLL_USE_LOCK BIT(0)
Signature · 1 line
2.23.0
PATCH v2 3/17 clk: tegra: cclk: Add helpers for handling PLLX rate changes
In reply to Dmitry OsipenkoCCLK should be re-parented away from PLLX if PLLX's rate is changing. The PLLP parent is a common safe CPU parent for all Tegra SoCs, thus CCLK will be re-parented to PLLP before PLLX rate-change begins and then switched back to PLLX after the rate-change completion. This patch adds helper functions which perform CCLK re-parenting, these helpers will be utilized by further patches.
--- drivers/clk/tegra/clk-tegra-super-cclk.c | 34 ++++++++++++++++++++++++ drivers/clk/tegra/clk.h | 2 ++ 2 files changed, 36 insertions(+)
drivers/clk/tegra/clk-tegra-super-cclk.c +34 -0
@@ -21,6 +21,9 @@#define PLLP_INDEX 4#define PLLX_INDEX 8 +static struct tegra_clk_super_mux *cclk_super; +static bool cclk_on_pllx; +static u8 cclk_super_get_parent (struct clk_hw *hw) {return tegra_clk_super_ops.get_parent (hw);
@@ -98,6 +101,9 @@ struct clk *tegra_clk_register_super_cclk(const char *name,struct clk *clk;struct clk_init_data init; +if (WARN_ON (cclk_super)) +return ERR_PTR (-EBUSY ); + super =kzalloc (sizeof (*super),GFP_KERNEL );if (!super)return ERR_PTR (-ENOMEM );
@@ -125,6 +131,34 @@ struct clk *tegra_clk_register_super_cclk(const char *name, clk =clk_register (NULL , &super->hw);if (IS_ERR (clk))kfree (super); +else + cclk_super = super;return clk; } + +int tegra_cclk_pre_pllx_rate_change (void ) +{ +if (IS_ERR_OR_NULL (cclk_super)) +return -EINVAL ; + +if (cclk_super_get_parent (&cclk_super->hw) ==PLLX_INDEX ) + cclk_on_pllx = true; +else + cclk_on_pllx = false; + +/* +* CPU needs to be temporarily re-parented away from PLLX if PLLX +* changes its rate. PLLP is a safe parent for CPU on all Tegra SoCs. +*/ +if (cclk_on_pllx) +cclk_super_set_parent (&cclk_super->hw,PLLP_INDEX ); + +return 0 ; +} + +void tegra_cclk_post_pllx_rate_change (void ) +{ +if (cclk_on_pllx) +cclk_super_set_parent (&cclk_super->hw,PLLX_INDEX ); +}
drivers/clk/tegra/clk.h +2 -0
@@ -709,6 +709,8 @@ struct clk *tegra_clk_register_super_cclk(const char *name, const char * const *parent_names, u8 num_parents, unsigned long flags, void __iomem *reg, u8 clk_super_flags, spinlock_t *lock); +int tegra_cclk_pre_pllx_rate_change (void ); +void tegra_cclk_post_pllx_rate_change (void );/** * struct tegra_sdmmc_mux - switch divider with Low Jitter inputs for SDMMC
Signature · 1 line
2.23.0
PATCH v2 4/17 clk: tegra20: Support custom CCLK implementation
In reply to Dmitry OsipenkoWe're going to switch to the generic cpufreq-dt driver on Tegra20 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra20 SoCs to use that implementation.
--- drivers/clk/tegra/clk-tegra20.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/clk/tegra/clk-tegra20.c +4 -2
@@ -391,6 +391,8 @@ static struct tegra_clk_pll_params pll_x_params = { .lock_delay = 300, .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, };static struct tegra_clk_pll_params pll_e_params = {
@@ -704,9 +706,9 @@ static void tegra20_super_clk_init(void)struct clk *clk;/* CCLK */ - clk =tegra_clk_register_super_mux ("cclk" , cclk_parents, + clk =tegra_clk_register_super_cclk ("cclk" , cclk_parents,ARRAY_SIZE (cclk_parents),CLK_SET_RATE_PARENT , - clk_base +CCLK_BURST_POLICY ,0 ,4 ,0 ,0 ,NULL ); + clk_base +CCLK_BURST_POLICY ,0 ,NULL ); clks[TEGRA20_CLK_CCLK ] = clk;/* SCLK */
Signature · 1 line
2.23.0
PATCH v2 5/17 clk: tegra30: Support custom CCLK implementation
In reply to Dmitry OsipenkoWe're going to switch to the generic cpufreq-dt driver on Tegra30 and thus CCLK intermediate re-parenting will be performed by the clock driver. There is now special CCLK implementation that supports all CCLK quirks, this patch makes Tegra30 SoCs to use that implementation.
--- drivers/clk/tegra/clk-tegra30.c | 6 ++++-- 1 file changed, 4 insertions(+), 2 deletions(-)
drivers/clk/tegra/clk-tegra30.c +4 -2
@@ -499,6 +499,8 @@ static struct tegra_clk_pll_params pll_x_params __ro_after_init = { .freq_table = pll_x_freq_table, .flags = TEGRA_PLL_HAS_CPCON | TEGRA_PLL_SET_DCCON | TEGRA_PLL_USE_LOCK | TEGRA_PLL_HAS_LOCK_ENABLE, + .pre_rate_change = tegra_cclk_pre_pllx_rate_change, + .post_rate_change = tegra_cclk_post_pllx_rate_change, };static struct tegra_clk_pll_params pll_e_params__ro_after_init = {
@@ -932,11 +934,11 @@ static void __init tegra30_super_clk_init(void)clk_register_clkdev (clk,"pll_p_out4_cclkg" ,NULL );/* CCLKG */ - clk =tegra_clk_register_super_mux ("cclk_g" , cclk_g_parents, + clk =tegra_clk_register_super_cclk ("cclk_g" , cclk_g_parents,ARRAY_SIZE (cclk_g_parents),CLK_SET_RATE_PARENT , clk_base +CCLKG_BURST_POLICY , -0 ,4 ,0 ,0 ,NULL ); +0 ,NULL ); clks[TEGRA30_CLK_CCLK_G ] = clk;/*
Signature · 1 line
2.23.0
PATCH v2 6/17 dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
In reply to Dmitry OsipenkoAdd device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoCs.
--- .../cpufreq/nvidia,tegra20-cpufreq.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt new file +56 -0
@@ -0,0 +1,56 @@ +Binding for NVIDIA Tegra20 CPUFreq +================================== + +Required properties: +- clocks: Must contain an entry for the CPU clock. + See ../clocks/clock-bindings.txt for details. +- operating-points-v2: See ../bindings/opp/opp.txt for details. +- #cooling-cells: Should be 2. See ../thermal/thermal.txt for details. + +For each opp entry in 'operating-points-v2' table: +- opp-supported-hw: Two bitfields indicating: + On Tegra20: + 1. CPU process ID mask + 2. SoC speedo ID mask + + On Tegra30: + 1. CPU process ID mask + 2. CPU speedo ID mask + + A bitwise AND is performed against these values and if any bit + matches, the OPP gets enabled. + +- opp-microvolt: CPU voltage triplet. + +Optional properties: +- cpu-supply: Phandle to the CPU power supply. + +Example: + regulators { + cpu_reg: regulator0 { + regulator-name = "vdd_cpu"; + }; + }; + + cpu0_opp_table: opp_table0 { + compatible = "operating-points-v2"; + + opp@456000000 { + clock-latency-ns = <125000>; + opp-microvolt = <825000 825000 1125000>; + opp-supported-hw = <0x03 0x0001>; + opp-hz = /bits/ 64 <456000000>; + }; + + ... + }; + + cpus { + cpu@0 { + compatible = "arm,cortex-a9"; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; + operating-points-v2 = <&cpu0_opp_table>; + cpu-supply = <&cpu_reg>; + #cooling-cells = <2>; + }; + };
Signature · 1 line
2.23.0
Re: [PATCH v2 06/17] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
Quoted 10 lines · Dmitry Osipenko
Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoCs.
Acked-by Viresh Kumar <[email protected]>Signed-off-by Dmitry Osipenko <[email protected]>--- .../cpufreq/nvidia,tegra20-cpufreq.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
Re: [PATCH v2 06/17] dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
30.10.2019 00:42, Rob Herring пишет:
Quoted 12 lines · Dmitry Osipenko
Quoted 10 lines
Add device-tree binding that describes CPU frequency-scaling hardware found on NVIDIA Tegra20/30 SoCs.
Acked-by Viresh Kumar <[email protected]>Signed-off-by Dmitry Osipenko <[email protected]>--- .../cpufreq/nvidia,tegra20-cpufreq.txt | 56 +++++++++++++++++++ 1 file changed, 56 insertions(+) create mode 100644 Documentation/devicetree/bindings/cpufreq/nvidia,tegra20-cpufreq.txt
Quoted 2 lines
Reviewed-by Rob Herring <[email protected]>
Thanks!
PATCH v2 7/17 cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)
In reply to Dmitry OsipenkoRe-parenting to intermediate clock is supported now by the clock driver and thus there is no need in a customized CPUFreq driver, all that code is common for both Tegra20 and Tegra30. The available CPU freqs are now specified in device-tree in a form of OPPs, all users should update their device-trees.
--- drivers/cpufreq/Kconfig.arm | 6 +- drivers/cpufreq/cpufreq-dt-platdev.c | 2 + drivers/cpufreq/tegra20-cpufreq.c | 211 +++++++-------------------- 3 files changed, 55 insertions(+), 164 deletions(-)
drivers/cpufreq/Kconfig.arm +3 -3
@@ -295,11 +295,11 @@ config ARM_TANGO_CPUFREQ default y config ARM_TEGRA20_CPUFREQ - tristate "Tegra20 CPUFreq support" - depends on ARCH_TEGRA + tristate "Tegra20/30 CPUFreq support" + depends on ARCH_TEGRA && CPUFREQ_DT default y help - This adds the CPUFreq driver support for Tegra20 SOCs. + This adds the CPUFreq driver support for Tegra20/30 SOCs. config ARM_TEGRA124_CPUFREQ bool "Tegra124 CPUFreq support"
drivers/cpufreq/cpufreq-dt-platdev.c +2 -0
@@ -121,6 +121,8 @@ static const struct of_device_id blacklist[] __initconst = { { .compatible = "mediatek,mt8176", }, { .compatible = "mediatek,mt8183", }, + { .compatible = "nvidia,tegra20", }, + { .compatible = "nvidia,tegra30", }, { .compatible = "nvidia,tegra124", }, { .compatible = "nvidia,tegra210", },
drivers/cpufreq/tegra20-cpufreq.c +50 -161
251 lines not on this page · raw message
Signature · 1 line
2.23.0
PATCH v2 8/17 ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
In reply to Dmitry OsipenkoThe tegra20-cpufreq now instantiates cpufreq-dt and Tegra30 is fully supported by that driver.
--- arch/arm/mach-tegra/tegra.c | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/mach-tegra/tegra.c +4 -0
@@ -95,6 +95,10 @@ static void __init tegra_dt_init_late(void)if (IS_ENABLED (CONFIG_ARCH_TEGRA_2x_SOC) &&of_machine_is_compatible ("nvidia,tegra20" ))platform_device_register_simple ("tegra20-cpufreq" ,-1 ,NULL ,0 ); + +if (IS_ENABLED (CONFIG_ARCH_TEGRA_3x_SOC) && +of_machine_is_compatible ("nvidia,tegra30" )) +platform_device_register_simple ("tegra20-cpufreq" ,-1 ,NULL ,0 ); }static const char *const tegra_dt_board_compat[] = {
Signature · 1 line
2.23.0
PATCH v2 9/17 ARM: dts: tegra20: Add CPU clock
In reply to Dmitry OsipenkoAll CPU cores share the same CPU clock.
--- arch/arm/boot/dts/tegra20.dtsi | 2 ++ 1 file changed, 2 insertions(+)
arch/arm/boot/dts/tegra20.dtsi +2 -0
@@ -851,12 +851,14 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA20_CLK_CCLK>; }; };
Signature · 1 line
2.23.0
PATCH v2 10/17 ARM: dts: tegra30: Add CPU clock
In reply to Dmitry OsipenkoAll "geared" CPU cores share the same CPU clock.
--- arch/arm/boot/dts/tegra30.dtsi | 4 ++++ 1 file changed, 4 insertions(+)
arch/arm/boot/dts/tegra30.dtsi +4 -0
@@ -1006,24 +1006,28 @@ device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <0>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; }; cpu@1 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <1>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; }; cpu@2 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <2>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; }; cpu@3 { device_type = "cpu"; compatible = "arm,cortex-a9"; reg = <3>; + clocks = <&tegra_car TEGRA30_CLK_CCLK_G>; }; };
Signature · 1 line
2.23.0
PATCH v2 11/17 ARM: dts: tegra20: Add CPU Operating Performance Points
In reply to Dmitry OsipenkoOperating Point are specified per HW version. The OPP voltages are kept in a separate DTSI file because some boards may not define CPU regulator in their device-tree if voltage scaling isn't necessary, like for example in a case of tegra20-trimslice which is outlet-powered device.
--- .../boot/dts/tegra20-cpu-opp-microvolt.dtsi | 201 ++++++++++++ arch/arm/boot/dts/tegra20-cpu-opp.dtsi | 302 ++++++++++++++++++ 2 files changed, 503 insertions(+) create mode 100644 arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi create mode 100644 arch/arm/boot/dts/tegra20-cpu-opp.dtsi
arch/arm/boot/dts/tegra20-cpu-opp-microvolt.dtsi new file +201 -0
@@ -0,0 +1,201 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpu0_opp_table: cpu_opp_table0 { + opp@216000000_750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp@216000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@312000000_750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp@312000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@456000000_750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp@456000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@456000000_800_2_2 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@456000000_800_3_2 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@456000000_825 { + opp-microvolt = <825000 825000 1125000>; + }; + + opp@608000000_750 { + opp-microvolt = <750000 750000 1125000>; + }; + + opp@608000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@608000000_800_3_2 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@608000000_825 { + opp-microvolt = <825000 825000 1125000>; + }; + + opp@608000000_850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp@608000000_900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp@760000000_775 { + opp-microvolt = <775000 775000 1125000>; + }; + + opp@760000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@760000000_850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp@760000000_875 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@760000000_875_1_1 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@760000000_875_0_2 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@760000000_875_1_2 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@760000000_900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp@760000000_975 { + opp-microvolt = <975000 975000 1125000>; + }; + + opp@816000000_800 { + opp-microvolt = <800000 800000 1125000>; + }; + + opp@816000000_850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp@816000000_875 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@816000000_950 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp@816000000_1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp@912000000_850 { + opp-microvolt = <850000 850000 1125000>; + }; + + opp@912000000_900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp@912000000_925 { + opp-microvolt = <925000 925000 1125000>; + }; + + opp@912000000_950 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp@912000000_950_0_2 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp@912000000_950_2_2 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp@912000000_1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp@912000000_1050 { + opp-microvolt = <1050000 1050000 1125000>; + }; + + opp@1000000000_875 { + opp-microvolt = <875000 875000 1125000>; + }; + + opp@1000000000_900 { + opp-microvolt = <900000 900000 1125000>; + }; + + opp@1000000000_950 { + opp-microvolt = <950000 950000 1125000>; + }; + + opp@1000000000_975 { + opp-microvolt = <975000 975000 1125000>; + }; + + opp@1000000000_1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp@1000000000_1000_0_2 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp@1000000000_1025 { + opp-microvolt = <1025000 1025000 1125000>; + }; + + opp@1000000000_1100 { + opp-microvolt = <1100000 1100000 1125000>; + }; + + opp@1200000000_1000 { + opp-microvolt = <1000000 1000000 1125000>; + }; + + opp@1200000000_1050 { + opp-microvolt = <1050000 1050000 1125000>; + }; + + opp@1200000000_1100 { + opp-microvolt = <1100000 1100000 1125000>; + }; + + opp@1200000000_1125 { + opp-microvolt = <1125000 1125000 1125000>; + }; + }; +};
arch/arm/boot/dts/tegra20-cpu-opp.dtsi new file +302 -0
302 lines not on this page · raw message
Signature · 1 line
2.23.0
PATCH v2 12/17 ARM: dts: tegra30: Add CPU Operating Performance Points
In reply to Dmitry OsipenkoOperating Point are specified per HW version. The OPP voltages are kept in a separate DTSI file because some boards may not define CPU regulator in their device-tree if voltage scaling isn't necessary for them.
--- .../boot/dts/tegra30-cpu-opp-microvolt.dtsi | 801 +++++++++++ arch/arm/boot/dts/tegra30-cpu-opp.dtsi | 1202 +++++++++++++++++ 2 files changed, 2003 insertions(+) create mode 100644 arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi create mode 100644 arch/arm/boot/dts/tegra30-cpu-opp.dtsi
arch/arm/boot/dts/tegra30-cpu-opp-microvolt.dtsi new file +801 -0
@@ -0,0 +1,801 @@ +// SPDX-License-Identifier: GPL-2.0 + +/ { + cpu0_opp_table: cpu_opp_table0 { + opp@51000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@51000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@51000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@102000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@102000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@102000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@204000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@204000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@204000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@312000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@312000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@340000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@340000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@370000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@456000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@456000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@475000000_800 { + opp-microvolt = <800000 800000 1250000>; + }; + + opp@475000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@475000000_850_0_1 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@475000000_850_0_4 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@475000000_850_0_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@475000000_850_0_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@608000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@608000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@620000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_1_1 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_2_1 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_3_1 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_1_4 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_2_4 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_3_4 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_1_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_2_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_3_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_4_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_1_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_2_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_3_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_850_4_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@640000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_1 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_2 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_3 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_4 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_4_7 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_3_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_4_8 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_850_0_10 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@760000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_1 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_1 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_2 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_2 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_3 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_3 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_4 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_4 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_7 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_7 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_1_8 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_900_2_8 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@760000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@760000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@816000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@816000000_912 { + opp-microvolt = <912000 912000 1250000>; + }; + + opp@860000000_850 { + opp-microvolt = <850000 850000 1250000>; + }; + + opp@860000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_1 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_1 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_2 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_2 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_3 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_3 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_4 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_4 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_7 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_7 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_4_7 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_2_8 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_3_8 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_900_4_8 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@860000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_1 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_2 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_3 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_4 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_975_1_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@860000000_1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@910000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@1000000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@1000000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_1 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_1 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_2 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_2 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_3 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_3 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_4 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_4 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_4_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_2_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_3_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_975_4_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1000000000_1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1000000000_1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1100000000_900 { + opp-microvolt = <900000 900000 1250000>; + }; + + opp@1100000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_1 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_2 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_3 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_4 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_4_7 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_3_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_975_4_8 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1100000000_1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_1 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_2 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_3 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_4 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_7 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1000_2_8 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1100000000_1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1100000000_1075 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1150000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1200000000_975 { + opp-microvolt = <975000 975000 1250000>; + }; + + opp@1200000000_1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_1 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_2 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_3 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_4 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_7 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_4_7 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_3_8 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1000_4_8 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1200000000_1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_1 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_2 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_3 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_4 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_7 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1025_2_8 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1200000000_1050 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1200000000_1075 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1200000000_1100 { + opp-microvolt = <1100000 1100000 1250000>; + }; + + opp@1300000000_1000 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1300000000_1000_4_7 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1300000000_1000_4_8 { + opp-microvolt = <1000000 1000000 1250000>; + }; + + opp@1300000000_1025 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1300000000_1025_3_1 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1300000000_1025_3_7 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1300000000_1025_3_8 { + opp-microvolt = <1025000 1025000 1250000>; + }; + + opp@1300000000_1050 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_2_1 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_2 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_3 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_4 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_5 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_6 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_2_7 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_2_8 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_12 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1050_3_13 { + opp-microvolt = <1050000 1050000 1250000>; + }; + + opp@1300000000_1075 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1300000000_1075_2_2 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1300000000_1075_2_3 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1300000000_1075_2_4 { + opp-microvolt = <1075000 1075000 1250000>; + }; + + opp@1300000000_1100 { + opp-microvolt = <1100000 1100000 1250000>; + }; + + opp@1300000000_1125 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1300000000_1150 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1300000000_1175 { + opp-microvolt = <1175000 1175000 1250000>; + }; + + opp@1400000000_1100 { + opp-microvolt = <1100000 1100000 1250000>; + }; + + opp@1400000000_1125 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1400000000_1150 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1400000000_1150_2_4 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1400000000_1175 { + opp-microvolt = <1175000 1175000 1250000>; + }; + + opp@1400000000_1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + + opp@1500000000_1125 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1500000000_1125_4_5 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1500000000_1125_4_6 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1500000000_1125_4_12 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1500000000_1125_4_13 { + opp-microvolt = <1125000 1125000 1250000>; + }; + + opp@1500000000_1150 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1500000000_1150_3_5 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1500000000_1150_3_6 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1500000000_1150_3_12 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1500000000_1150_3_13 { + opp-microvolt = <1150000 1150000 1250000>; + }; + + opp@1500000000_1200 { + opp-microvolt = <1200000 1200000 1250000>; + }; + + opp@1500000000_1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + + opp@1600000000_1212 { + opp-microvolt = <1212000 1212000 1250000>; + }; + + opp@1600000000_1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + + opp@1700000000_1212 { + opp-microvolt = <1212000 1212000 1250000>; + }; + + opp@1700000000_1237 { + opp-microvolt = <1237000 1237000 1250000>; + }; + }; +};
arch/arm/boot/dts/tegra30-cpu-opp.dtsi new file +1202 -0
1,202 lines not on this page · raw message
Signature · 1 line
2.23.0
PATCH v2 13/17 ARM: dts: tegra20: paz00: Set up voltage regulators for DVFS
In reply to Dmitry OsipenkoSet min/max voltage and couple CPU/CORE/RTC regulators.
--- arch/arm/boot/dts/tegra20-paz00.dts | 27 ++++++++++++++++++++------- 1 file changed, 20 insertions(+), 7 deletions(-)
arch/arm/boot/dts/tegra20-paz00.dts +20 -7
@@ -337,18 +337,26 @@ regulator-always-on; }; - sm0 { + core_vdd_reg: sm0 { regulator-name = "+1.2vs_sm0,vdd_core"; regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + regulator-coupled-with = <&rtc_vdd_reg &cpu_vdd_reg>; + regulator-coupled-max-spread = <170000 450000>; regulator-always-on; + + nvidia,tegra-core-regulator; }; - sm1 { + cpu_vdd_reg: sm1 { regulator-name = "+1.0vs_sm1,vdd_cpu"; - regulator-min-microvolt = <1000000>; - regulator-max-microvolt = <1000000>; + regulator-min-microvolt = <750000>; + regulator-max-microvolt = <1100000>; + regulator-coupled-with = <&core_vdd_reg &rtc_vdd_reg>; + regulator-coupled-max-spread = <450000 450000>; regulator-always-on; + + nvidia,tegra-cpu-regulator; }; sm2_reg: sm2 {
@@ -367,10 +375,15 @@ regulator-always-on; }; - ldo2 { + rtc_vdd_reg: ldo2 { regulator-name = "+1.2vs_ldo2,vdd_rtc"; regulator-min-microvolt = <1200000>; - regulator-max-microvolt = <1200000>; + regulator-max-microvolt = <1225000>; + regulator-coupled-with = <&core_vdd_reg &cpu_vdd_reg>; + regulator-coupled-max-spread = <170000 450000>; + regulator-always-on; + + nvidia,tegra-rtc-regulator; }; ldo3 {
Signature · 1 line
2.23.0
PATCH v2 14/17 ARM: dts: tegra20: paz00: Add CPU Operating Performance Points
In reply to Dmitry OsipenkoUtilize common Tegra20 CPU OPP table. CPU DVFS is available now on AC100.
--- arch/arm/boot/dts/tegra20-paz00.dts | 14 ++++++++++++++ 1 file changed, 14 insertions(+)
arch/arm/boot/dts/tegra20-paz00.dts +14 -0
@@ -3,6 +3,8 @@ #include <dt-bindings/input/input.h> #include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" +#include "tegra20-cpu-opp-microvolt.dtsi" / { model = "Toshiba AC100 / Dynabook AZ";
@@ -616,4 +618,16 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&cpu_vdd_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };
Signature · 1 line
2.23.0
PATCH v2 15/17 ARM: dts: tegra20: trimslice: Add CPU Operating Performance Points
In reply to Dmitry OsipenkoUtilize common Tegra20 CPU OPP table. CPU voltage scaling is available now on TrimSlice.
--- arch/arm/boot/dts/tegra20-trimslice.dts | 11 +++++++++++ 1 file changed, 11 insertions(+)
arch/arm/boot/dts/tegra20-trimslice.dts +11 -0
@@ -3,6 +3,7 @@ #include <dt-bindings/input/input.h> #include "tegra20.dtsi" +#include "tegra20-cpu-opp.dtsi" / { model = "Compulab TrimSlice board";
@@ -471,4 +472,14 @@ <&tegra_car TEGRA20_CLK_CDEV1>; clock-names = "pll_a", "pll_a_out0", "mclk"; }; + + cpus { + cpu0: cpu@0 { + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };
Signature · 1 line
2.23.0
PATCH v2 16/17 ARM: dts: tegra30: cardhu-a04: Set up voltage regulators for DVFS
In reply to Dmitry OsipenkoSet min/max voltage and couple CPU/CORE regulators.
--- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm/boot/dts/tegra30-cardhu-a04.dts +24 -0
@@ -103,4 +103,28 @@ gpio = <&gpio TEGRA_GPIO(DD, 0) GPIO_ACTIVE_HIGH>; }; }; + + i2c@7000d000 { + pmic: tps65911@2d { + regulators { + vddctrl_reg: vddctrl { + regulator-min-microvolt = <800000>; + regulator-max-microvolt = <1125000>; + regulator-coupled-with = <&vddcore_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + + nvidia,tegra-cpu-regulator; + }; + }; + }; + + vddcore_reg: tps62361@60 { + regulator-coupled-with = <&vddctrl_reg>; + regulator-coupled-max-spread = <300000>; + regulator-max-step-microvolt = <100000>; + + nvidia,tegra-core-regulator; + }; + }; };
Signature · 1 line
2.23.0
PATCH v2 17/17 ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
In reply to Dmitry OsipenkoUtilize common Tegra30 CPU OPP table. CPU DVFS is available now on cardhu-a04.
--- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)
arch/arm/boot/dts/tegra30-cardhu-a04.dts +24 -0
@@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30-cardhu.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /* This dts file support the cardhu A04 and later versions of board */
@@ -127,4 +129,26 @@ nvidia,tegra-core-regulator; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };
Signature · 1 line
2.23.0
Jon Hunter
maintainerRe: [PATCH v2 17/17] ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
Quoted 38 lines · Dmitry Osipenko
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on cardhu-a04.
Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm/boot/dts/tegra30-cardhu-a04.dts +15
-0@@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30-cardhu.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /* This dts file support the cardhu A04 and later versions of board */@@ -127,4 +129,26 @@ nvidia,tegra-core-regulator; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 {
arch/arm/boot/dts/tegra30-cardhu-a04.dts line 154
Quoted 10 lines
arch/arm/boot/dts/tegra30-cardhu-a04.dts +9
-0+ cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };
Sorry for not testing this sooner, but this is generating the following WARNING on boot ...
[ 2.916019] ------------[ cut here ]------------ [ 2.920669] WARNING: CPU: 2 PID: 1 at /dvs/git/dirty/git-master_l4t-upstream/kernel/drivers/opp/of.c:688 _of_add_opp_table_v2.part.2+0x45c/0x4d4 [ 2.933713] Modules linked in: [ 2.936785] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc7-next-20191112-gfc6d6db1df2c #1 [ 2.945403] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [ 2.951706] [<c0112924>] (unwind_backtrace) from [<c010c9d0>] (show_stack+0x10/0x14) [ 2.959467] [<c010c9d0>] (show_stack) from [<c0aa4494>] (dump_stack+0xc0/0xd4) [ 2.966707] [<c0aa4494>] (dump_stack) from [<c0124750>] (__warn+0xe0/0xf8) [ 2.973593] [<c0124750>] (__warn) from [<c0124818>] (warn_slowpath_fmt+0xb0/0xb8) [ 2.981090] [<c0124818>] (warn_slowpath_fmt) from [<c0754be0>] (_of_add_opp_table_v2.part.2+0x45c/0x4d4) [ 2.990583] [<c0754be0>] (_of_add_opp_table_v2.part.2) from [<c0754c98>] (dev_pm_opp_of_add_table+0x40/0x15c) [ 3.000508] [<c0754c98>] (dev_pm_opp_of_add_table) from [<c0754de8>] (dev_pm_opp_of_cpumask_add_table+0x34/0xb4) [ 3.010704] [<c0754de8>] (dev_pm_opp_of_cpumask_add_table) from [<c075b058>] (cpufreq_init+0xf8/0x2cc) [ 3.020024] [<c075b058>] (cpufreq_init) from [<c0758758>] (cpufreq_online+0x260/0x824) [ 3.027953] [<c0758758>] (cpufreq_online) from [<c0758d98>] (cpufreq_add_dev+0x6c/0x78) [ 3.035976] [<c0758d98>] (cpufreq_add_dev) from [<c05b3188>] (subsys_interface_register+0xa0/0xec) [ 3.044951] [<c05b3188>] (subsys_interface_register) from [<c07574d4>] (cpufreq_register_driver+0x14c/0x20c) [ 3.054792] [<c07574d4>] (cpufreq_register_driver) from [<c075aee0>] (dt_cpufreq_probe+0x94/0x114) [ 3.063771] [<c075aee0>] (dt_cpufreq_probe) from [<c05b6a88>] (platform_drv_probe+0x48/0x98) [ 3.072225] [<c05b6a88>] (platform_drv_probe) from [<c05b4a38>] (really_probe+0x234/0x34c) [ 3.080502] [<c05b4a38>] (really_probe) from [<c05b4cc8>] (driver_probe_device+0x60/0x168) [ 3.088780] [<c05b4cc8>] (driver_probe_device) from [<c05b4f78>] (device_driver_attach+0x58/0x60) [ 3.097664] [<c05b4f78>] (device_driver_attach) from [<c05b5000>] (__driver_attach+0x80/0xbc) [ 3.106200] [<c05b5000>] (__driver_attach) from [<c05b2db0>] (bus_for_each_dev+0x74/0xb4) [ 3.114389] [<c05b2db0>] (bus_for_each_dev) from [<c05b3da4>] (bus_add_driver+0x164/0x1e8) [ 3.122666] [<c05b3da4>] (bus_add_driver) from [<c05b5b54>] (driver_register+0x7c/0x114) [ 3.130774] [<c05b5b54>] (driver_register) from [<c010306c>] (do_one_initcall+0x54/0x2a8) [ 3.138974] [<c010306c>] (do_one_initcall) from [<c0f01040>] (kernel_init_freeable+0x14c/0x1e8) [ 3.147695] [<c0f01040>] (kernel_init_freeable) from [<c0abbe88>] (kernel_init+0x8/0x10c) [ 3.155887] [<c0abbe88>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c) [ 3.163462] Exception stack(0xef0c9fb0 to 0xef0c9ff8) [ 3.168519] 9fa0: 00000000 00000000 00000000 00000000 [ 3.176706] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.184893] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 3.191695] ---[ end trace a7dc36f7a4ddbdb2 ]--- [ 3.197855] ------------[ cut here ]------------
Let me know if you can take a look at this.
Thanks
Jon
Signature · 1 line
nvpublic
Re: [PATCH v2 17/17] ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
Hello Jon,
13.11.2019 09:52, Jon Hunter пишет:
Quoted 91 lines · Dmitry Osipenko
Quoted 38 lines
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on cardhu-a04.
Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm/boot/dts/tegra30-cardhu-a04.dts +15
-0@@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30-cardhu.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /* This dts file support the cardhu A04 and later versions of board */@@ -127,4 +129,26 @@ nvidia,tegra-core-regulator; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 {arch/arm/boot/dts/tegra30-cardhu-a04.dts line 154
Quoted 10 lines
arch/arm/boot/dts/tegra30-cardhu-a04.dts +9
-0+ cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };Sorry for not testing this sooner, but this is generating the following WARNING on boot ...
[ 2.916019] ------------[ cut here ]------------ [ 2.920669] WARNING: CPU: 2 PID: 1 at /dvs/git/dirty/git-master_l4t-upstream/kernel/drivers/opp/of.c:688 _of_add_opp_table_v2.part.2+0x45c/0x4d4 [ 2.933713] Modules linked in: [ 2.936785] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc7-next-20191112-gfc6d6db1df2c #1 [ 2.945403] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [ 2.951706] [<c0112924>] (unwind_backtrace) from [<c010c9d0>] (show_stack+0x10/0x14) [ 2.959467] [<c010c9d0>] (show_stack) from [<c0aa4494>] (dump_stack+0xc0/0xd4) [ 2.966707] [<c0aa4494>] (dump_stack) from [<c0124750>] (__warn+0xe0/0xf8) [ 2.973593] [<c0124750>] (__warn) from [<c0124818>] (warn_slowpath_fmt+0xb0/0xb8) [ 2.981090] [<c0124818>] (warn_slowpath_fmt) from [<c0754be0>] (_of_add_opp_table_v2.part.2+0x45c/0x4d4) [ 2.990583] [<c0754be0>] (_of_add_opp_table_v2.part.2) from [<c0754c98>] (dev_pm_opp_of_add_table+0x40/0x15c) [ 3.000508] [<c0754c98>] (dev_pm_opp_of_add_table) from [<c0754de8>] (dev_pm_opp_of_cpumask_add_table+0x34/0xb4) [ 3.010704] [<c0754de8>] (dev_pm_opp_of_cpumask_add_table) from [<c075b058>] (cpufreq_init+0xf8/0x2cc) [ 3.020024] [<c075b058>] (cpufreq_init) from [<c0758758>] (cpufreq_online+0x260/0x824) [ 3.027953] [<c0758758>] (cpufreq_online) from [<c0758d98>] (cpufreq_add_dev+0x6c/0x78) [ 3.035976] [<c0758d98>] (cpufreq_add_dev) from [<c05b3188>] (subsys_interface_register+0xa0/0xec) [ 3.044951] [<c05b3188>] (subsys_interface_register) from [<c07574d4>] (cpufreq_register_driver+0x14c/0x20c) [ 3.054792] [<c07574d4>] (cpufreq_register_driver) from [<c075aee0>] (dt_cpufreq_probe+0x94/0x114) [ 3.063771] [<c075aee0>] (dt_cpufreq_probe) from [<c05b6a88>] (platform_drv_probe+0x48/0x98) [ 3.072225] [<c05b6a88>] (platform_drv_probe) from [<c05b4a38>] (really_probe+0x234/0x34c) [ 3.080502] [<c05b4a38>] (really_probe) from [<c05b4cc8>] (driver_probe_device+0x60/0x168) [ 3.088780] [<c05b4cc8>] (driver_probe_device) from [<c05b4f78>] (device_driver_attach+0x58/0x60) [ 3.097664] [<c05b4f78>] (device_driver_attach) from [<c05b5000>] (__driver_attach+0x80/0xbc) [ 3.106200] [<c05b5000>] (__driver_attach) from [<c05b2db0>] (bus_for_each_dev+0x74/0xb4) [ 3.114389] [<c05b2db0>] (bus_for_each_dev) from [<c05b3da4>] (bus_add_driver+0x164/0x1e8) [ 3.122666] [<c05b3da4>] (bus_add_driver) from [<c05b5b54>] (driver_register+0x7c/0x114) [ 3.130774] [<c05b5b54>] (driver_register) from [<c010306c>] (do_one_initcall+0x54/0x2a8) [ 3.138974] [<c010306c>] (do_one_initcall) from [<c0f01040>] (kernel_init_freeable+0x14c/0x1e8) [ 3.147695] [<c0f01040>] (kernel_init_freeable) from [<c0abbe88>] (kernel_init+0x8/0x10c) [ 3.155887] [<c0abbe88>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c) [ 3.163462] Exception stack(0xef0c9fb0 to 0xef0c9ff8) [ 3.168519] 9fa0: 00000000 00000000 00000000 00000000 [ 3.176706] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.184893] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 3.191695] ---[ end trace a7dc36f7a4ddbdb2 ]--- [ 3.197855] ------------[ cut here ]------------
Quoted 1 line
Let me know if you can take a look at this.
The warning happens because Cardhu now has CPU OPPs in the device-tree, but supported_hw isn't set for the OPPs and thus the count of available OPPs is 0.
This is expected to happen because patch "cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)" isn't applied yet.
It is possible to factor out the blacklisting of Tegra SoCs in cpufreq_dt_platdev_init() into a separate patch and request backporting of that change in order to avoid the warning noise for older kernel versions + newer device-tree. Please let me know if you think that it's worth to do the separation.
Jon Hunter
maintainerRe: [PATCH v2 17/17] ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
Quoted 100 lines · Dmitry Osipenko
Hello Jon,
13.11.2019 09:52, Jon Hunter пишет:
Quoted 91 lines · Dmitry Osipenko
Quoted 38 lines
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on cardhu-a04.
Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm/boot/dts/tegra30-cardhu-a04.dts +15
-0@@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30-cardhu.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /* This dts file support the cardhu A04 and later versions of board */@@ -127,4 +129,26 @@ nvidia,tegra-core-regulator; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 {arch/arm/boot/dts/tegra30-cardhu-a04.dts line 154
Quoted 10 lines
arch/arm/boot/dts/tegra30-cardhu-a04.dts +9
-0+ cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };Sorry for not testing this sooner, but this is generating the following WARNING on boot ...
[ 2.916019] ------------[ cut here ]------------ [ 2.920669] WARNING: CPU: 2 PID: 1 at /dvs/git/dirty/git-master_l4t-upstream/kernel/drivers/opp/of.c:688 _of_add_opp_table_v2.part.2+0x45c/0x4d4 [ 2.933713] Modules linked in: [ 2.936785] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc7-next-20191112-gfc6d6db1df2c #1 [ 2.945403] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [ 2.951706] [<c0112924>] (unwind_backtrace) from [<c010c9d0>] (show_stack+0x10/0x14) [ 2.959467] [<c010c9d0>] (show_stack) from [<c0aa4494>] (dump_stack+0xc0/0xd4) [ 2.966707] [<c0aa4494>] (dump_stack) from [<c0124750>] (__warn+0xe0/0xf8) [ 2.973593] [<c0124750>] (__warn) from [<c0124818>] (warn_slowpath_fmt+0xb0/0xb8) [ 2.981090] [<c0124818>] (warn_slowpath_fmt) from [<c0754be0>] (_of_add_opp_table_v2.part.2+0x45c/0x4d4) [ 2.990583] [<c0754be0>] (_of_add_opp_table_v2.part.2) from [<c0754c98>] (dev_pm_opp_of_add_table+0x40/0x15c) [ 3.000508] [<c0754c98>] (dev_pm_opp_of_add_table) from [<c0754de8>] (dev_pm_opp_of_cpumask_add_table+0x34/0xb4) [ 3.010704] [<c0754de8>] (dev_pm_opp_of_cpumask_add_table) from [<c075b058>] (cpufreq_init+0xf8/0x2cc) [ 3.020024] [<c075b058>] (cpufreq_init) from [<c0758758>] (cpufreq_online+0x260/0x824) [ 3.027953] [<c0758758>] (cpufreq_online) from [<c0758d98>] (cpufreq_add_dev+0x6c/0x78) [ 3.035976] [<c0758d98>] (cpufreq_add_dev) from [<c05b3188>] (subsys_interface_register+0xa0/0xec) [ 3.044951] [<c05b3188>] (subsys_interface_register) from [<c07574d4>] (cpufreq_register_driver+0x14c/0x20c) [ 3.054792] [<c07574d4>] (cpufreq_register_driver) from [<c075aee0>] (dt_cpufreq_probe+0x94/0x114) [ 3.063771] [<c075aee0>] (dt_cpufreq_probe) from [<c05b6a88>] (platform_drv_probe+0x48/0x98) [ 3.072225] [<c05b6a88>] (platform_drv_probe) from [<c05b4a38>] (really_probe+0x234/0x34c) [ 3.080502] [<c05b4a38>] (really_probe) from [<c05b4cc8>] (driver_probe_device+0x60/0x168) [ 3.088780] [<c05b4cc8>] (driver_probe_device) from [<c05b4f78>] (device_driver_attach+0x58/0x60) [ 3.097664] [<c05b4f78>] (device_driver_attach) from [<c05b5000>] (__driver_attach+0x80/0xbc) [ 3.106200] [<c05b5000>] (__driver_attach) from [<c05b2db0>] (bus_for_each_dev+0x74/0xb4) [ 3.114389] [<c05b2db0>] (bus_for_each_dev) from [<c05b3da4>] (bus_add_driver+0x164/0x1e8) [ 3.122666] [<c05b3da4>] (bus_add_driver) from [<c05b5b54>] (driver_register+0x7c/0x114) [ 3.130774] [<c05b5b54>] (driver_register) from [<c010306c>] (do_one_initcall+0x54/0x2a8) [ 3.138974] [<c010306c>] (do_one_initcall) from [<c0f01040>] (kernel_init_freeable+0x14c/0x1e8) [ 3.147695] [<c0f01040>] (kernel_init_freeable) from [<c0abbe88>] (kernel_init+0x8/0x10c) [ 3.155887] [<c0abbe88>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c) [ 3.163462] Exception stack(0xef0c9fb0 to 0xef0c9ff8) [ 3.168519] 9fa0: 00000000 00000000 00000000 00000000 [ 3.176706] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.184893] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 3.191695] ---[ end trace a7dc36f7a4ddbdb2 ]--- [ 3.197855] ------------[ cut here ]------------Quoted 1 line
Let me know if you can take a look at this.
The warning happens because Cardhu now has CPU OPPs in the device-tree, but
supported_hwisn't set for the OPPs and thus the count of available OPPs is 0.
Quoted 8 lines
This is expected to happen because patch "cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)" isn't applied yet.
It is possible to factor out the blacklisting of Tegra SoCs in
cpufreq_dt_platdev_init()into a separate patch and request backporting of that change in order to avoid the warning noise for older kernel versions + newer device-tree. Please let me know if you think that it's worth to do the separation.
Unfortunately, I think we are going to need to drop this patch. Booting Tegra30-cardhu-a04 with Thierry's for-5.5/arm/dt branch does not even boot. There is no crash log but it hangs on boot. This patch appears to be the culprit. What is odd is that Tegra30-cardhu-a04 boots fine with Thierry's for-next branch which includes this. However, this is causing lots of bisect problems. Updating the DT shouldn't break the boot.
Jon
Signature · 1 line
nvpublic
Re: [PATCH v2 17/17] ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
15.11.2019 15:52, Jon Hunter пишет:
Quoted 111 lines · Dmitry Osipenko
Quoted 100 lines
Hello Jon,
13.11.2019 09:52, Jon Hunter пишет:
Quoted 91 lines · Dmitry Osipenko
Quoted 38 lines
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on cardhu-a04.
Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm/boot/dts/tegra30-cardhu-a04.dts +15
-0@@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30-cardhu.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /* This dts file support the cardhu A04 and later versions of board */@@ -127,4 +129,26 @@ nvidia,tegra-core-regulator; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 {arch/arm/boot/dts/tegra30-cardhu-a04.dts line 154
Quoted 10 lines
arch/arm/boot/dts/tegra30-cardhu-a04.dts +9
-0+ cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };Sorry for not testing this sooner, but this is generating the following WARNING on boot ...
[ 2.916019] ------------[ cut here ]------------ [ 2.920669] WARNING: CPU: 2 PID: 1 at /dvs/git/dirty/git-master_l4t-upstream/kernel/drivers/opp/of.c:688 _of_add_opp_table_v2.part.2+0x45c/0x4d4 [ 2.933713] Modules linked in: [ 2.936785] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc7-next-20191112-gfc6d6db1df2c #1 [ 2.945403] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [ 2.951706] [<c0112924>] (unwind_backtrace) from [<c010c9d0>] (show_stack+0x10/0x14) [ 2.959467] [<c010c9d0>] (show_stack) from [<c0aa4494>] (dump_stack+0xc0/0xd4) [ 2.966707] [<c0aa4494>] (dump_stack) from [<c0124750>] (__warn+0xe0/0xf8) [ 2.973593] [<c0124750>] (__warn) from [<c0124818>] (warn_slowpath_fmt+0xb0/0xb8) [ 2.981090] [<c0124818>] (warn_slowpath_fmt) from [<c0754be0>] (_of_add_opp_table_v2.part.2+0x45c/0x4d4) [ 2.990583] [<c0754be0>] (_of_add_opp_table_v2.part.2) from [<c0754c98>] (dev_pm_opp_of_add_table+0x40/0x15c) [ 3.000508] [<c0754c98>] (dev_pm_opp_of_add_table) from [<c0754de8>] (dev_pm_opp_of_cpumask_add_table+0x34/0xb4) [ 3.010704] [<c0754de8>] (dev_pm_opp_of_cpumask_add_table) from [<c075b058>] (cpufreq_init+0xf8/0x2cc) [ 3.020024] [<c075b058>] (cpufreq_init) from [<c0758758>] (cpufreq_online+0x260/0x824) [ 3.027953] [<c0758758>] (cpufreq_online) from [<c0758d98>] (cpufreq_add_dev+0x6c/0x78) [ 3.035976] [<c0758d98>] (cpufreq_add_dev) from [<c05b3188>] (subsys_interface_register+0xa0/0xec) [ 3.044951] [<c05b3188>] (subsys_interface_register) from [<c07574d4>] (cpufreq_register_driver+0x14c/0x20c) [ 3.054792] [<c07574d4>] (cpufreq_register_driver) from [<c075aee0>] (dt_cpufreq_probe+0x94/0x114) [ 3.063771] [<c075aee0>] (dt_cpufreq_probe) from [<c05b6a88>] (platform_drv_probe+0x48/0x98) [ 3.072225] [<c05b6a88>] (platform_drv_probe) from [<c05b4a38>] (really_probe+0x234/0x34c) [ 3.080502] [<c05b4a38>] (really_probe) from [<c05b4cc8>] (driver_probe_device+0x60/0x168) [ 3.088780] [<c05b4cc8>] (driver_probe_device) from [<c05b4f78>] (device_driver_attach+0x58/0x60) [ 3.097664] [<c05b4f78>] (device_driver_attach) from [<c05b5000>] (__driver_attach+0x80/0xbc) [ 3.106200] [<c05b5000>] (__driver_attach) from [<c05b2db0>] (bus_for_each_dev+0x74/0xb4) [ 3.114389] [<c05b2db0>] (bus_for_each_dev) from [<c05b3da4>] (bus_add_driver+0x164/0x1e8) [ 3.122666] [<c05b3da4>] (bus_add_driver) from [<c05b5b54>] (driver_register+0x7c/0x114) [ 3.130774] [<c05b5b54>] (driver_register) from [<c010306c>] (do_one_initcall+0x54/0x2a8) [ 3.138974] [<c010306c>] (do_one_initcall) from [<c0f01040>] (kernel_init_freeable+0x14c/0x1e8) [ 3.147695] [<c0f01040>] (kernel_init_freeable) from [<c0abbe88>] (kernel_init+0x8/0x10c) [ 3.155887] [<c0abbe88>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c) [ 3.163462] Exception stack(0xef0c9fb0 to 0xef0c9ff8) [ 3.168519] 9fa0: 00000000 00000000 00000000 00000000 [ 3.176706] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.184893] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 3.191695] ---[ end trace a7dc36f7a4ddbdb2 ]--- [ 3.197855] ------------[ cut here ]------------Quoted 1 line
Let me know if you can take a look at this.
The warning happens because Cardhu now has CPU OPPs in the device-tree, but
supported_hwisn't set for the OPPs and thus the count of available OPPs is 0.Quoted 8 lines
This is expected to happen because patch "cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)" isn't applied yet.
It is possible to factor out the blacklisting of Tegra SoCs in
cpufreq_dt_platdev_init()into a separate patch and request backporting of that change in order to avoid the warning noise for older kernel versions + newer device-tree. Please let me know if you think that it's worth to do the separation.
Quoted 6 lines
Unfortunately, I think we are going to need to drop this patch. Booting Tegra30-cardhu-a04 with Thierry's for-5.5/arm/dt branch does not even boot. There is no crash log but it hangs on boot. This patch appears to be the culprit. What is odd is that Tegra30-cardhu-a04 boots fine with Thierry's for-next branch which includes this. However, this is causing lots of bisect problems. Updating the DT shouldn't break the boot.
The diff between "for-5.5/arm/dt" and "for-next" is quite small, you only need to try to revert one or two patches. Seems the only major change which could be somehow related to CPUFreq is that "for-5.5/arm/dt" doesn't have regulators coupling support, but I don't see how it could cause any effect since CPUFreq just doesn't load due to a missing setup of supported_hw.
Unfortunately for now I can't reproduce the hang with a similar setup that has OPPs in DT, doesn't have Tegra CPUFreq driver, doesn't blacklist Tegra in cpufreq-dt-platdev.c and doesn't have regulators coupling. I see the warning splats on boot and everything appears to be working fine.
It's likely that the hang is caused by something else than this patch. It's also a bit odd that you're accusing this patch while apparently it worked a day before.
Please give a try to the recent upstream linux-next. If it works, then probably there is nothing to worry about.
I'll factor out the blacklisting change and add it as a separate patch into the next revision of the series, marking the patch as "fixes" and "stable" in order to get rid of the warning on stable kernels.
I'm also fine with reverting of the DT changes for now, if you prefer that. But again, this DT change shouldn't cause any critical problems.
I need a detailed report or a way to reproduce the problem in order to solve it, please try to collect some more details. Try to compile the cpufreq-dt driver as a loadable module, enable tracing of clk and regulator events (tp_printk trace_event=regulator_set_voltage,clk_set_rate,clk_set_parent).
Jon Hunter
maintainerRe: [PATCH v2 17/17] ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
Quoted 125 lines · Dmitry Osipenko
15.11.2019 15:52, Jon Hunter пишет:
Quoted 111 lines · Dmitry Osipenko
Quoted 100 lines
Hello Jon,
13.11.2019 09:52, Jon Hunter пишет:
Quoted 91 lines · Dmitry Osipenko
Quoted 38 lines
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on cardhu-a04.
Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm/boot/dts/tegra30-cardhu-a04.dts +15
-0@@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30-cardhu.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /* This dts file support the cardhu A04 and later versions of board */@@ -127,4 +129,26 @@ nvidia,tegra-core-regulator; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 {arch/arm/boot/dts/tegra30-cardhu-a04.dts line 154
Quoted 10 lines
arch/arm/boot/dts/tegra30-cardhu-a04.dts +9
-0+ cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };Sorry for not testing this sooner, but this is generating the following WARNING on boot ...
[ 2.916019] ------------[ cut here ]------------ [ 2.920669] WARNING: CPU: 2 PID: 1 at /dvs/git/dirty/git-master_l4t-upstream/kernel/drivers/opp/of.c:688 _of_add_opp_table_v2.part.2+0x45c/0x4d4 [ 2.933713] Modules linked in: [ 2.936785] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc7-next-20191112-gfc6d6db1df2c #1 [ 2.945403] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [ 2.951706] [<c0112924>] (unwind_backtrace) from [<c010c9d0>] (show_stack+0x10/0x14) [ 2.959467] [<c010c9d0>] (show_stack) from [<c0aa4494>] (dump_stack+0xc0/0xd4) [ 2.966707] [<c0aa4494>] (dump_stack) from [<c0124750>] (__warn+0xe0/0xf8) [ 2.973593] [<c0124750>] (__warn) from [<c0124818>] (warn_slowpath_fmt+0xb0/0xb8) [ 2.981090] [<c0124818>] (warn_slowpath_fmt) from [<c0754be0>] (_of_add_opp_table_v2.part.2+0x45c/0x4d4) [ 2.990583] [<c0754be0>] (_of_add_opp_table_v2.part.2) from [<c0754c98>] (dev_pm_opp_of_add_table+0x40/0x15c) [ 3.000508] [<c0754c98>] (dev_pm_opp_of_add_table) from [<c0754de8>] (dev_pm_opp_of_cpumask_add_table+0x34/0xb4) [ 3.010704] [<c0754de8>] (dev_pm_opp_of_cpumask_add_table) from [<c075b058>] (cpufreq_init+0xf8/0x2cc) [ 3.020024] [<c075b058>] (cpufreq_init) from [<c0758758>] (cpufreq_online+0x260/0x824) [ 3.027953] [<c0758758>] (cpufreq_online) from [<c0758d98>] (cpufreq_add_dev+0x6c/0x78) [ 3.035976] [<c0758d98>] (cpufreq_add_dev) from [<c05b3188>] (subsys_interface_register+0xa0/0xec) [ 3.044951] [<c05b3188>] (subsys_interface_register) from [<c07574d4>] (cpufreq_register_driver+0x14c/0x20c) [ 3.054792] [<c07574d4>] (cpufreq_register_driver) from [<c075aee0>] (dt_cpufreq_probe+0x94/0x114) [ 3.063771] [<c075aee0>] (dt_cpufreq_probe) from [<c05b6a88>] (platform_drv_probe+0x48/0x98) [ 3.072225] [<c05b6a88>] (platform_drv_probe) from [<c05b4a38>] (really_probe+0x234/0x34c) [ 3.080502] [<c05b4a38>] (really_probe) from [<c05b4cc8>] (driver_probe_device+0x60/0x168) [ 3.088780] [<c05b4cc8>] (driver_probe_device) from [<c05b4f78>] (device_driver_attach+0x58/0x60) [ 3.097664] [<c05b4f78>] (device_driver_attach) from [<c05b5000>] (__driver_attach+0x80/0xbc) [ 3.106200] [<c05b5000>] (__driver_attach) from [<c05b2db0>] (bus_for_each_dev+0x74/0xb4) [ 3.114389] [<c05b2db0>] (bus_for_each_dev) from [<c05b3da4>] (bus_add_driver+0x164/0x1e8) [ 3.122666] [<c05b3da4>] (bus_add_driver) from [<c05b5b54>] (driver_register+0x7c/0x114) [ 3.130774] [<c05b5b54>] (driver_register) from [<c010306c>] (do_one_initcall+0x54/0x2a8) [ 3.138974] [<c010306c>] (do_one_initcall) from [<c0f01040>] (kernel_init_freeable+0x14c/0x1e8) [ 3.147695] [<c0f01040>] (kernel_init_freeable) from [<c0abbe88>] (kernel_init+0x8/0x10c) [ 3.155887] [<c0abbe88>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c) [ 3.163462] Exception stack(0xef0c9fb0 to 0xef0c9ff8) [ 3.168519] 9fa0: 00000000 00000000 00000000 00000000 [ 3.176706] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.184893] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 3.191695] ---[ end trace a7dc36f7a4ddbdb2 ]--- [ 3.197855] ------------[ cut here ]------------Quoted 1 line
Let me know if you can take a look at this.
The warning happens because Cardhu now has CPU OPPs in the device-tree, but
supported_hwisn't set for the OPPs and thus the count of available OPPs is 0.Quoted 8 lines
This is expected to happen because patch "cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)" isn't applied yet.
It is possible to factor out the blacklisting of Tegra SoCs in
cpufreq_dt_platdev_init()into a separate patch and request backporting of that change in order to avoid the warning noise for older kernel versions + newer device-tree. Please let me know if you think that it's worth to do the separation.Quoted 6 lines
Unfortunately, I think we are going to need to drop this patch. Booting Tegra30-cardhu-a04 with Thierry's for-5.5/arm/dt branch does not even boot. There is no crash log but it hangs on boot. This patch appears to be the culprit. What is odd is that Tegra30-cardhu-a04 boots fine with Thierry's for-next branch which includes this. However, this is causing lots of bisect problems. Updating the DT shouldn't break the boot.
The diff between "for-5.5/arm/dt" and "for-next" is quite small, you only need to try to revert one or two patches. Seems the only major change which could be somehow related to CPUFreq is that "for-5.5/arm/dt" doesn't have regulators coupling support, but I don't see how it could cause any effect since CPUFreq just doesn't load due to a missing setup of
supported_hw.
Quoted 7 lines
Unfortunately for now I can't reproduce the hang with a similar setup that has OPPs in DT, doesn't have Tegra CPUFreq driver, doesn't blacklist Tegra in
cpufreq-dt-platdev.cand doesn't have regulators coupling. I see the warning splats on boot and everything appears to be working fine.It's likely that the hang is caused by something else than this patch.
No, it is definitely this patch. 100% reproducible.
Quoted 2 lines
It's also a bit odd that you're accusing this patch while apparently it worked a day before.
No, the behaviour on top of -next is different to the "for-5.5/arm/dt" branch, which is what I am saying.
Quoted 2 lines
Please give a try to the recent upstream linux-next. If it works, then probably there is nothing to worry about.
No, there is plenty to be concerned about, with the latest -next we are getting these WARN splats on boot, which we need to avoid.
Quoted 6 lines
I'll factor out the blacklisting change and add it as a separate patch into the next revision of the series, marking the patch as "fixes" and "stable" in order to get rid of the warning on stable kernels.
I'm also fine with reverting of the DT changes for now, if you prefer that. But again, this DT change shouldn't cause any critical problems.
No it should not, but it does.
Quoted 5 lines
I need a detailed report or a way to reproduce the problem in order to solve it, please try to collect some more details. Try to compile the cpufreq-dt driver as a loadable module, enable tracing of clk and regulator events (
tp_printktrace_event=regulator_set_voltage,clk_set_rate,clk_set_parent).
I add some debug prints and on boot with "for-5.5/arm/dt" is dies while bringing CPU0 online for cpufreq ...
[ 2.863369] cpufreq_dt: dt_cpufreq_probe-347 [ 2.867917] cpufreq_dt: dt_cpufreq_probe-360 [ 2.872195] cpufreq_dt: dt_cpufreq_probe-370 [ 2.876509] cpufreq: cpufreq_register_driver-2632 [ 2.881219] cpufreq: cpufreq_register_driver-2636 [ 2.885989] cpufreq: trying to register driver cpufreq-dt [ 2.891395] cpufreq: cpufreq_register_driver-2651 [ 2.896131] cpufreq: cpufreq_register_driver-2661 [ 2.900839] cpufreq: cpufreq_register_driver-2665 [ 2.905610] cpufreq: cpufreq_register_driver-2672 [ 2.910329] cpu cpu0: cpufreq_add_dev: adding CPU0 [ 2.915152] cpufreq: cpufreq_online: bringing CPU0 online
So I think it is best to revert this for now.
Jon
Signature · 1 line
nvpublic
Re: [PATCH v2 17/17] ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
15.11.2019 20:31, Jon Hunter пишет:
Quoted 181 lines · Dmitry Osipenko
Quoted 125 lines
15.11.2019 15:52, Jon Hunter пишет:
Quoted 111 lines · Dmitry Osipenko
Quoted 100 lines
Hello Jon,
13.11.2019 09:52, Jon Hunter пишет:
Quoted 91 lines · Dmitry Osipenko
Quoted 38 lines
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on cardhu-a04.
Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm/boot/dts/tegra30-cardhu-a04.dts +15
-0@@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30-cardhu.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /* This dts file support the cardhu A04 and later versions of board */@@ -127,4 +129,26 @@ nvidia,tegra-core-regulator; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 {arch/arm/boot/dts/tegra30-cardhu-a04.dts line 154
Quoted 10 lines
arch/arm/boot/dts/tegra30-cardhu-a04.dts +9
-0+ cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };Sorry for not testing this sooner, but this is generating the following WARNING on boot ...
[ 2.916019] ------------[ cut here ]------------ [ 2.920669] WARNING: CPU: 2 PID: 1 at /dvs/git/dirty/git-master_l4t-upstream/kernel/drivers/opp/of.c:688 _of_add_opp_table_v2.part.2+0x45c/0x4d4 [ 2.933713] Modules linked in: [ 2.936785] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc7-next-20191112-gfc6d6db1df2c #1 [ 2.945403] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [ 2.951706] [<c0112924>] (unwind_backtrace) from [<c010c9d0>] (show_stack+0x10/0x14) [ 2.959467] [<c010c9d0>] (show_stack) from [<c0aa4494>] (dump_stack+0xc0/0xd4) [ 2.966707] [<c0aa4494>] (dump_stack) from [<c0124750>] (__warn+0xe0/0xf8) [ 2.973593] [<c0124750>] (__warn) from [<c0124818>] (warn_slowpath_fmt+0xb0/0xb8) [ 2.981090] [<c0124818>] (warn_slowpath_fmt) from [<c0754be0>] (_of_add_opp_table_v2.part.2+0x45c/0x4d4) [ 2.990583] [<c0754be0>] (_of_add_opp_table_v2.part.2) from [<c0754c98>] (dev_pm_opp_of_add_table+0x40/0x15c) [ 3.000508] [<c0754c98>] (dev_pm_opp_of_add_table) from [<c0754de8>] (dev_pm_opp_of_cpumask_add_table+0x34/0xb4) [ 3.010704] [<c0754de8>] (dev_pm_opp_of_cpumask_add_table) from [<c075b058>] (cpufreq_init+0xf8/0x2cc) [ 3.020024] [<c075b058>] (cpufreq_init) from [<c0758758>] (cpufreq_online+0x260/0x824) [ 3.027953] [<c0758758>] (cpufreq_online) from [<c0758d98>] (cpufreq_add_dev+0x6c/0x78) [ 3.035976] [<c0758d98>] (cpufreq_add_dev) from [<c05b3188>] (subsys_interface_register+0xa0/0xec) [ 3.044951] [<c05b3188>] (subsys_interface_register) from [<c07574d4>] (cpufreq_register_driver+0x14c/0x20c) [ 3.054792] [<c07574d4>] (cpufreq_register_driver) from [<c075aee0>] (dt_cpufreq_probe+0x94/0x114) [ 3.063771] [<c075aee0>] (dt_cpufreq_probe) from [<c05b6a88>] (platform_drv_probe+0x48/0x98) [ 3.072225] [<c05b6a88>] (platform_drv_probe) from [<c05b4a38>] (really_probe+0x234/0x34c) [ 3.080502] [<c05b4a38>] (really_probe) from [<c05b4cc8>] (driver_probe_device+0x60/0x168) [ 3.088780] [<c05b4cc8>] (driver_probe_device) from [<c05b4f78>] (device_driver_attach+0x58/0x60) [ 3.097664] [<c05b4f78>] (device_driver_attach) from [<c05b5000>] (__driver_attach+0x80/0xbc) [ 3.106200] [<c05b5000>] (__driver_attach) from [<c05b2db0>] (bus_for_each_dev+0x74/0xb4) [ 3.114389] [<c05b2db0>] (bus_for_each_dev) from [<c05b3da4>] (bus_add_driver+0x164/0x1e8) [ 3.122666] [<c05b3da4>] (bus_add_driver) from [<c05b5b54>] (driver_register+0x7c/0x114) [ 3.130774] [<c05b5b54>] (driver_register) from [<c010306c>] (do_one_initcall+0x54/0x2a8) [ 3.138974] [<c010306c>] (do_one_initcall) from [<c0f01040>] (kernel_init_freeable+0x14c/0x1e8) [ 3.147695] [<c0f01040>] (kernel_init_freeable) from [<c0abbe88>] (kernel_init+0x8/0x10c) [ 3.155887] [<c0abbe88>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c) [ 3.163462] Exception stack(0xef0c9fb0 to 0xef0c9ff8) [ 3.168519] 9fa0: 00000000 00000000 00000000 00000000 [ 3.176706] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.184893] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 3.191695] ---[ end trace a7dc36f7a4ddbdb2 ]--- [ 3.197855] ------------[ cut here ]------------Quoted 1 line
Let me know if you can take a look at this.
The warning happens because Cardhu now has CPU OPPs in the device-tree, but
supported_hwisn't set for the OPPs and thus the count of available OPPs is 0.Quoted 8 lines
This is expected to happen because patch "cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)" isn't applied yet.
It is possible to factor out the blacklisting of Tegra SoCs in
cpufreq_dt_platdev_init()into a separate patch and request backporting of that change in order to avoid the warning noise for older kernel versions + newer device-tree. Please let me know if you think that it's worth to do the separation.Quoted 6 lines
Unfortunately, I think we are going to need to drop this patch. Booting Tegra30-cardhu-a04 with Thierry's for-5.5/arm/dt branch does not even boot. There is no crash log but it hangs on boot. This patch appears to be the culprit. What is odd is that Tegra30-cardhu-a04 boots fine with Thierry's for-next branch which includes this. However, this is causing lots of bisect problems. Updating the DT shouldn't break the boot.
The diff between "for-5.5/arm/dt" and "for-next" is quite small, you only need to try to revert one or two patches. Seems the only major change which could be somehow related to CPUFreq is that "for-5.5/arm/dt" doesn't have regulators coupling support, but I don't see how it could cause any effect since CPUFreq just doesn't load due to a missing setup of
supported_hw.Quoted 7 lines
Unfortunately for now I can't reproduce the hang with a similar setup that has OPPs in DT, doesn't have Tegra CPUFreq driver, doesn't blacklist Tegra in
cpufreq-dt-platdev.cand doesn't have regulators coupling. I see the warning splats on boot and everything appears to be working fine.It's likely that the hang is caused by something else than this patch.
No, it is definitely this patch. 100% reproducible.
Quoted 2 lines
It's also a bit odd that you're accusing this patch while apparently it worked a day before.
No, the behaviour on top of -next is different to the "for-5.5/arm/dt" branch, which is what I am saying.
Quoted 2 lines
Please give a try to the recent upstream linux-next. If it works, then probably there is nothing to worry about.
No, there is plenty to be concerned about, with the latest -next we are getting these WARN splats on boot, which we need to avoid.
Quoted 6 lines
I'll factor out the blacklisting change and add it as a separate patch into the next revision of the series, marking the patch as "fixes" and "stable" in order to get rid of the warning on stable kernels.
I'm also fine with reverting of the DT changes for now, if you prefer that. But again, this DT change shouldn't cause any critical problems.
No it should not, but it does.
Quoted 5 lines
I need a detailed report or a way to reproduce the problem in order to solve it, please try to collect some more details. Try to compile the cpufreq-dt driver as a loadable module, enable tracing of clk and regulator events (
tp_printktrace_event=regulator_set_voltage,clk_set_rate,clk_set_parent).I add some debug prints and on boot with "for-5.5/arm/dt" is dies while bringing CPU0 online for cpufreq ...
[ 2.863369] cpufreq_dt: dt_cpufreq_probe-347 [ 2.867917] cpufreq_dt: dt_cpufreq_probe-360 [ 2.872195] cpufreq_dt: dt_cpufreq_probe-370 [ 2.876509] cpufreq: cpufreq_register_driver-2632 [ 2.881219] cpufreq: cpufreq_register_driver-2636 [ 2.885989] cpufreq: trying to register driver cpufreq-dt [ 2.891395] cpufreq: cpufreq_register_driver-2651 [ 2.896131] cpufreq: cpufreq_register_driver-2661 [ 2.900839] cpufreq: cpufreq_register_driver-2665 [ 2.905610] cpufreq: cpufreq_register_driver-2672 [ 2.910329] cpu cpu0: cpufreq_add_dev: adding CPU0 [ 2.915152] cpufreq: cpufreq_online: bringing CPU0 online
Quoted 1 line
So I think it is best to revert this for now.
I managed to reproduced the problem using unmodified "for-5.5/arm/dt":
# modprobe cpufreq-dt
[ 41.002512] regulator_set_voltage: name=vdd_core (1100000-1350000) [ 41.007822] regulator_set_voltage: name=vdd_core (1000000-1350000) [ 41.012475] regulator_set_voltage: name=vdd_cpu (925000-1250000) [ 41.017299] regulator_set_voltage: name=vdd_cpu (825000-1250000) [ 41.021842] regulator_set_voltage: name=vdd_core (950000-1350000) [ 41.025399] regulator_set_voltage: name=vdd_cpu (800000-1250000)
As you can see the voltage drops too much and I know what causes it. The OPP core was getting some fixes recently, while "for-5.5/arm/dt" uses older 5.4-rc1 as the base. The problem was introduced in 5.4-rc1 and then it was fixed by the commit [1] in 5.4-rc5.
The "for-next" branch has Tegra30 regulators coupling support and I actually worked around that OPP-core problem in the Tegra's coupler back in July [2] (see changelog). That explains why "for-next" branch works.
[2] https://lkml.org/lkml/2019/7/25/892
Thus the DT patch doesn't cause any problems. It just happened that the DT patch is a victim of the 5.4-rc1 OPP-core problem that is already fixed in rc5.
Jon, anyways thank you for the heads-up. I'll add a patch to blacklist the cpufreq-dt-platdev in the next iteration to silence the warnings.
Jon Hunter
maintainerRe: [PATCH v2 17/17] ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
Quoted 195 lines · Dmitry Osipenko
15.11.2019 20:31, Jon Hunter пишет:
Quoted 181 lines · Dmitry Osipenko
Quoted 125 lines
15.11.2019 15:52, Jon Hunter пишет:
Quoted 111 lines · Dmitry Osipenko
Quoted 100 lines
Hello Jon,
13.11.2019 09:52, Jon Hunter пишет:
Quoted 91 lines · Dmitry Osipenko
Quoted 38 lines
Utilize common Tegra30 CPU OPP table. CPU DVFS is available now on cardhu-a04.
Signed-off-by Dmitry Osipenko <[email protected]>--- arch/arm/boot/dts/tegra30-cardhu-a04.dts | 24 ++++++++++++++++++++++++ 1 file changed, 24 insertions(+)arch/arm/boot/dts/tegra30-cardhu-a04.dts +15
-0@@ -2,6 +2,8 @@ /dts-v1/; #include "tegra30-cardhu.dtsi" +#include "tegra30-cpu-opp.dtsi" +#include "tegra30-cpu-opp-microvolt.dtsi" /* This dts file support the cardhu A04 and later versions of board */@@ -127,4 +129,26 @@ nvidia,tegra-core-regulator; }; }; + + cpus { + cpu0: cpu@0 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@1 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@2 {arch/arm/boot/dts/tegra30-cardhu-a04.dts line 154
Quoted 10 lines
arch/arm/boot/dts/tegra30-cardhu-a04.dts +9
-0+ cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + + cpu@3 { + cpu-supply = <&vddctrl_reg>; + operating-points-v2 = <&cpu0_opp_table>; + }; + }; };Sorry for not testing this sooner, but this is generating the following WARNING on boot ...
[ 2.916019] ------------[ cut here ]------------ [ 2.920669] WARNING: CPU: 2 PID: 1 at /dvs/git/dirty/git-master_l4t-upstream/kernel/drivers/opp/of.c:688 _of_add_opp_table_v2.part.2+0x45c/0x4d4 [ 2.933713] Modules linked in: [ 2.936785] CPU: 2 PID: 1 Comm: swapper/0 Not tainted 5.4.0-rc7-next-20191112-gfc6d6db1df2c #1 [ 2.945403] Hardware name: NVIDIA Tegra SoC (Flattened Device Tree) [ 2.951706] [<c0112924>] (unwind_backtrace) from [<c010c9d0>] (show_stack+0x10/0x14) [ 2.959467] [<c010c9d0>] (show_stack) from [<c0aa4494>] (dump_stack+0xc0/0xd4) [ 2.966707] [<c0aa4494>] (dump_stack) from [<c0124750>] (__warn+0xe0/0xf8) [ 2.973593] [<c0124750>] (__warn) from [<c0124818>] (warn_slowpath_fmt+0xb0/0xb8) [ 2.981090] [<c0124818>] (warn_slowpath_fmt) from [<c0754be0>] (_of_add_opp_table_v2.part.2+0x45c/0x4d4) [ 2.990583] [<c0754be0>] (_of_add_opp_table_v2.part.2) from [<c0754c98>] (dev_pm_opp_of_add_table+0x40/0x15c) [ 3.000508] [<c0754c98>] (dev_pm_opp_of_add_table) from [<c0754de8>] (dev_pm_opp_of_cpumask_add_table+0x34/0xb4) [ 3.010704] [<c0754de8>] (dev_pm_opp_of_cpumask_add_table) from [<c075b058>] (cpufreq_init+0xf8/0x2cc) [ 3.020024] [<c075b058>] (cpufreq_init) from [<c0758758>] (cpufreq_online+0x260/0x824) [ 3.027953] [<c0758758>] (cpufreq_online) from [<c0758d98>] (cpufreq_add_dev+0x6c/0x78) [ 3.035976] [<c0758d98>] (cpufreq_add_dev) from [<c05b3188>] (subsys_interface_register+0xa0/0xec) [ 3.044951] [<c05b3188>] (subsys_interface_register) from [<c07574d4>] (cpufreq_register_driver+0x14c/0x20c) [ 3.054792] [<c07574d4>] (cpufreq_register_driver) from [<c075aee0>] (dt_cpufreq_probe+0x94/0x114) [ 3.063771] [<c075aee0>] (dt_cpufreq_probe) from [<c05b6a88>] (platform_drv_probe+0x48/0x98) [ 3.072225] [<c05b6a88>] (platform_drv_probe) from [<c05b4a38>] (really_probe+0x234/0x34c) [ 3.080502] [<c05b4a38>] (really_probe) from [<c05b4cc8>] (driver_probe_device+0x60/0x168) [ 3.088780] [<c05b4cc8>] (driver_probe_device) from [<c05b4f78>] (device_driver_attach+0x58/0x60) [ 3.097664] [<c05b4f78>] (device_driver_attach) from [<c05b5000>] (__driver_attach+0x80/0xbc) [ 3.106200] [<c05b5000>] (__driver_attach) from [<c05b2db0>] (bus_for_each_dev+0x74/0xb4) [ 3.114389] [<c05b2db0>] (bus_for_each_dev) from [<c05b3da4>] (bus_add_driver+0x164/0x1e8) [ 3.122666] [<c05b3da4>] (bus_add_driver) from [<c05b5b54>] (driver_register+0x7c/0x114) [ 3.130774] [<c05b5b54>] (driver_register) from [<c010306c>] (do_one_initcall+0x54/0x2a8) [ 3.138974] [<c010306c>] (do_one_initcall) from [<c0f01040>] (kernel_init_freeable+0x14c/0x1e8) [ 3.147695] [<c0f01040>] (kernel_init_freeable) from [<c0abbe88>] (kernel_init+0x8/0x10c) [ 3.155887] [<c0abbe88>] (kernel_init) from [<c01010e8>] (ret_from_fork+0x14/0x2c) [ 3.163462] Exception stack(0xef0c9fb0 to 0xef0c9ff8) [ 3.168519] 9fa0: 00000000 00000000 00000000 00000000 [ 3.176706] 9fc0: 00000000 00000000 00000000 00000000 00000000 00000000 00000000 00000000 [ 3.184893] 9fe0: 00000000 00000000 00000000 00000000 00000013 00000000 [ 3.191695] ---[ end trace a7dc36f7a4ddbdb2 ]--- [ 3.197855] ------------[ cut here ]------------Quoted 1 line
Let me know if you can take a look at this.
The warning happens because Cardhu now has CPU OPPs in the device-tree, but
supported_hwisn't set for the OPPs and thus the count of available OPPs is 0.Quoted 8 lines
This is expected to happen because patch "cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported now)" isn't applied yet.
It is possible to factor out the blacklisting of Tegra SoCs in
cpufreq_dt_platdev_init()into a separate patch and request backporting of that change in order to avoid the warning noise for older kernel versions + newer device-tree. Please let me know if you think that it's worth to do the separation.Quoted 6 lines
Unfortunately, I think we are going to need to drop this patch. Booting Tegra30-cardhu-a04 with Thierry's for-5.5/arm/dt branch does not even boot. There is no crash log but it hangs on boot. This patch appears to be the culprit. What is odd is that Tegra30-cardhu-a04 boots fine with Thierry's for-next branch which includes this. However, this is causing lots of bisect problems. Updating the DT shouldn't break the boot.
The diff between "for-5.5/arm/dt" and "for-next" is quite small, you only need to try to revert one or two patches. Seems the only major change which could be somehow related to CPUFreq is that "for-5.5/arm/dt" doesn't have regulators coupling support, but I don't see how it could cause any effect since CPUFreq just doesn't load due to a missing setup of
supported_hw.Quoted 7 lines
Unfortunately for now I can't reproduce the hang with a similar setup that has OPPs in DT, doesn't have Tegra CPUFreq driver, doesn't blacklist Tegra in
cpufreq-dt-platdev.cand doesn't have regulators coupling. I see the warning splats on boot and everything appears to be working fine.It's likely that the hang is caused by something else than this patch.
No, it is definitely this patch. 100% reproducible.
Quoted 2 lines
It's also a bit odd that you're accusing this patch while apparently it worked a day before.
No, the behaviour on top of -next is different to the "for-5.5/arm/dt" branch, which is what I am saying.
Quoted 2 lines
Please give a try to the recent upstream linux-next. If it works, then probably there is nothing to worry about.
No, there is plenty to be concerned about, with the latest -next we are getting these WARN splats on boot, which we need to avoid.
Quoted 6 lines
I'll factor out the blacklisting change and add it as a separate patch into the next revision of the series, marking the patch as "fixes" and "stable" in order to get rid of the warning on stable kernels.
I'm also fine with reverting of the DT changes for now, if you prefer that. But again, this DT change shouldn't cause any critical problems.
No it should not, but it does.
Quoted 5 lines
I need a detailed report or a way to reproduce the problem in order to solve it, please try to collect some more details. Try to compile the cpufreq-dt driver as a loadable module, enable tracing of clk and regulator events (
tp_printktrace_event=regulator_set_voltage,clk_set_rate,clk_set_parent).I add some debug prints and on boot with "for-5.5/arm/dt" is dies while bringing CPU0 online for cpufreq ...
[ 2.863369] cpufreq_dt: dt_cpufreq_probe-347 [ 2.867917] cpufreq_dt: dt_cpufreq_probe-360 [ 2.872195] cpufreq_dt: dt_cpufreq_probe-370 [ 2.876509] cpufreq: cpufreq_register_driver-2632 [ 2.881219] cpufreq: cpufreq_register_driver-2636 [ 2.885989] cpufreq: trying to register driver cpufreq-dt [ 2.891395] cpufreq: cpufreq_register_driver-2651 [ 2.896131] cpufreq: cpufreq_register_driver-2661 [ 2.900839] cpufreq: cpufreq_register_driver-2665 [ 2.905610] cpufreq: cpufreq_register_driver-2672 [ 2.910329] cpu cpu0: cpufreq_add_dev: adding CPU0 [ 2.915152] cpufreq: cpufreq_online: bringing CPU0 onlineQuoted 1 line
So I think it is best to revert this for now.
I managed to reproduced the problem using unmodified "for-5.5/arm/dt":
# modprobe cpufreq-dt[ 41.002512] regulator_set_voltage: name=vdd_core (1100000-1350000) [ 41.007822] regulator_set_voltage: name=vdd_core (1000000-1350000) [ 41.012475] regulator_set_voltage: name=vdd_cpu (925000-1250000) [ 41.017299] regulator_set_voltage: name=vdd_cpu (825000-1250000) [ 41.021842] regulator_set_voltage: name=vdd_core (950000-1350000) [ 41.025399] regulator_set_voltage: name=vdd_cpu (800000-1250000)
Quoted 4 lines
As you can see the voltage drops too much and I know what causes it. The OPP core was getting some fixes recently, while "for-5.5/arm/dt" uses older 5.4-rc1 as the base. The problem was introduced in 5.4-rc1 and then it was fixed by the commit [1] in 5.4-rc5.
OK, great. Thanks for tracking this down.
Quoted 7 lines
The "for-next" branch has Tegra30 regulators coupling support and I actually worked around that OPP-core problem in the Tegra's coupler back in July [2] (see changelog). That explains why "for-next" branch works.
Quoted 5 lines
[2] https://lkml.org/lkml/2019/7/25/892
Thus the DT patch doesn't cause any problems. It just happened that the DT patch is a victim of the 5.4-rc1 OPP-core problem that is already fixed in rc5.
OK, and so that explains what I am seeing.
Quoted 2 lines
Jon, anyways thank you for the heads-up. I'll add a patch to blacklist the cpufreq-dt-platdev in the next iteration to silence the warnings.
Yes if we could get the WARN fixed-up, that would make me happy :-)
Cheers!
Jon
Signature · 1 line
nvpublic
Thierry Reding
AppliedQuoted 48 lines · Dmitry Osipenko
Hello,
This series moves intermediate-clk handling from tegra20-cpufreq into tegra-clk driver, this allows us to switch to generic cpufreq-dt driver which brings voltage scaling, per-hardware OPPs and Tegra30 support out of the box. All boards need to adopt CPU OPPs in their device-trees in order to get cpufreq support. This series adds OPPs only to selective boards because there is assumption in a current device-trees that CPU voltage is set for 1GHz freq and this won't work for those CPUs that can go over 1GHz and thus require voltage regulators to be set up for voltage scaling support (CC'ed Marcel for Toradex boards). We could probably add delete-node for OPPs over 1GHz if there are not actively maintained boards.
NOTE(!): the voltage scaling functionality depends on a reviewed and yet unapplied series [0], thus [0] needs to be applied first.
[0] https://lkml.org/lkml/2019/7/25/892
Changelog:
v2: - Kept modularity of the tegra20-cpufreq as was requested by Viresh Kumar
in a review comment to v1.- Added acks from Viresh Kumar.
- Added tested-by from Nicolas Chauvet to the "trimslice" patch. Nicolas told me on IRC that it works fine.
- Fixed compilation of the "Add custom CCLK implementation" patch. The error happened because v1 was based on top of yet unreviewed/unapplied patch "clk: tegra: divider: Support enable-bit for Super clocks". Thanks to Peter Geis for reporting the problem.
- Replaced Tegra30 "beaver" board with "cardhu-a04" because turned out that's what NVIDIA uses in the testing farm.
Dmitry Osipenko (17):
clk: tegra: Add custom CCLK implementation
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra20: Support custom CCLK implementation
clk: tegra30: Support custom CCLK implementation
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported
now)
ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
ARM: dts: tegra20: Add CPU clock
Quoted 8 lines
ARM: dts: tegra30: Add CPU clock
ARM: dts: tegra20: Add CPU Operating Performance Points
ARM: dts: tegra30: Add CPU Operating Performance Points
ARM: dts: tegra20: paz00: Set up voltage regulators for DVFS
ARM: dts: tegra20: paz00: Add CPU Operating Performance Points
ARM: dts: tegra20: trimslice: Add CPU Operating Performance Points
ARM: dts: tegra30: cardhu-a04: Set up voltage regulators for DVFS
ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
I've applied patches 9-17 (the DT bits) to for-5.5/arm/dt. I'll hold back on applying the others until Peter is happy with them.
Thierry
29.10.2019 17:09, Thierry Reding пишет:
Quoted 58 lines · Dmitry Osipenko
Quoted 48 lines
Hello,
This series moves intermediate-clk handling from tegra20-cpufreq into tegra-clk driver, this allows us to switch to generic cpufreq-dt driver which brings voltage scaling, per-hardware OPPs and Tegra30 support out of the box. All boards need to adopt CPU OPPs in their device-trees in order to get cpufreq support. This series adds OPPs only to selective boards because there is assumption in a current device-trees that CPU voltage is set for 1GHz freq and this won't work for those CPUs that can go over 1GHz and thus require voltage regulators to be set up for voltage scaling support (CC'ed Marcel for Toradex boards). We could probably add delete-node for OPPs over 1GHz if there are not actively maintained boards.
NOTE(!): the voltage scaling functionality depends on a reviewed and yet unapplied series [0], thus [0] needs to be applied first.
[0] https://lkml.org/lkml/2019/7/25/892
Changelog:
v2: - Kept modularity of the tegra20-cpufreq as was requested by Viresh Kumar
in a review comment to v1.- Added acks from Viresh Kumar.
- Added tested-by from Nicolas Chauvet to the "trimslice" patch. Nicolas told me on IRC that it works fine.
- Fixed compilation of the "Add custom CCLK implementation" patch. The error happened because v1 was based on top of yet unreviewed/unapplied patch "clk: tegra: divider: Support enable-bit for Super clocks". Thanks to Peter Geis for reporting the problem.
- Replaced Tegra30 "beaver" board with "cardhu-a04" because turned out that's what NVIDIA uses in the testing farm.
Dmitry Osipenko (17):
clk: tegra: Add custom CCLK implementation
clk: tegra: pll: Add pre/post rate-change hooks
clk: tegra: cclk: Add helpers for handling PLLX rate changes
clk: tegra20: Support custom CCLK implementation
clk: tegra30: Support custom CCLK implementation
dt-bindings: cpufreq: Add binding for NVIDIA Tegra20/30
cpufreq: tegra20: Use generic cpufreq-dt driver (Tegra30 supported
now)
ARM: tegra: Create tegra20-cpufreq platform device on Tegra30
ARM: dts: tegra20: Add CPU clockQuoted 8 lines
ARM: dts: tegra30: Add CPU clock
ARM: dts: tegra20: Add CPU Operating Performance Points
ARM: dts: tegra30: Add CPU Operating Performance Points
ARM: dts: tegra20: paz00: Set up voltage regulators for DVFS
ARM: dts: tegra20: paz00: Add CPU Operating Performance Points
ARM: dts: tegra20: trimslice: Add CPU Operating Performance Points
ARM: dts: tegra30: cardhu-a04: Set up voltage regulators for DVFS
ARM: dts: tegra30: cardhu-a04: Add CPU Operating Performance Points
Quoted 2 lines
I've applied patches 9-17 (the DT bits) to for-5.5/arm/dt. I'll hold back on applying the others until Peter is happy with them.
Thanks, I'll update the patches and re-add OPPs for the Beaver board since you have it.