ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
PATCH 1/2 ARM: tegra: Switch CPU to PLLP on resume from LP1 on Tegra30/114/124
The early-resume code shall not switch CPU to PLLX because PLLX configuration could be unstable or PLLX should be simply disabled if CPU enters into suspend running off some other PLL (the case if CPUFREQ driver is active). The actual burst policy is restored by the clock drivers.
--- arch/arm/mach-tegra/sleep-tegra30.S | 7 ++----- 1 file changed, 2 insertions(+), 5 deletions(-)
arch/arm/mach-tegra/sleep-tegra30.S +2 -5
@@ -383,11 +383,8 @@ _pll_m_c_x_done: ldr r4, [r5, #0x1C] @ restore SCLK_BURST str r4, [r0, #CLK_RESET_SCLK_BURST] - cmp r10, #TEGRA30 - movweq r4, #:lower16:((1 << 28) | (0x8)) @ burst policy is PLLX - movteq r4, #:upper16:((1 << 28) | (0x8)) - movwne r4, #:lower16:((1 << 28) | (0xe)) - movtne r4, #:upper16:((1 << 28) | (0xe)) + movw r4, #:lower16:((1 << 28) | (0x4)) @ burst policy is PLLP + movt r4, #:upper16:((1 << 28) | (0x4)) str r4, [r0, #CLK_RESET_CCLK_BURST] /* Restore pad power state to normal */
Signature · 1 line
2.23.0
PATCH 2/2 ARM: tegra: Don't enable PLLX while resuming from LP1 on Tegra30
PLLX may be kept disabled if cpufreq driver selects some other clock for CPU. In that case PLLX will be disabled later in the resume path by the CLK driver, which also can enable PLLX if necessary by itself. Thus there is no need to enable PLLX early during resume. Tegra114/124 CLK drivers do not manage PLLX on resume and thus they are left untouched by this patch.
--- arch/arm/mach-tegra/sleep-tegra30.S | 11 ++++++++++- 1 file changed, 10 insertions(+), 1 deletion(-)
arch/arm/mach-tegra/sleep-tegra30.S +10 -1
@@ -358,7 +358,6 @@ _no_pll_iddq_exit: pll_enable r1, r0, CLK_RESET_PLLM_BASE, CLK_RESET_PLLM_MISC pll_enable r1, r0, CLK_RESET_PLLC_BASE, CLK_RESET_PLLC_MISC - pll_enable r1, r0, CLK_RESET_PLLX_BASE, CLK_RESET_PLLX_MISC _pll_m_c_x_done: pll_enable r1, r0, CLK_RESET_PLLP_BASE, CLK_RESET_PLLP_MISC
@@ -368,8 +367,18 @@ _pll_m_c_x_done: pll_locked r1, r0, CLK_RESET_PLLP_BASE pll_locked r1, r0, CLK_RESET_PLLA_BASE pll_locked r1, r0, CLK_RESET_PLLC_BASE + + /* + * CPUFreq driver could select other PLL for CPU. PLLX will be + * enabled by the Tegra30 CLK driver on an as-needed basis, see + * tegra30_cpu_clock_resume(). + */ + cmp r10, #TEGRA30 + beq _pll_m_c_x_locked + pll_locked r1, r0, CLK_RESET_PLLX_BASE +_pll_m_c_x_locked: mov32 r7, TEGRA_TMRUS_BASE ldr r1, [r7] add r1, r1, #LOCK_DELAY
Signature · 1 line
2.23.0