Add QUP SE instances configuration
Subsystems (4)
cover Add QUP SE instances configuration
This change depends on below series
https://patchwork.kernel.org/project/linux-arm-msm/list/?series=192087
Roja Rani Yarubandi (1):
arm64: dts: sc7180: Add qupv3_0 and qupv3_1
arch/arm64/boot/dts/qcom/sc7180-idp.dts | 152 +++++- arch/arm64/boot/dts/qcom/sc7180.dtsi | 683 +++++++++++++++++++++++- 2 files changed, 828 insertions(+), 7 deletions(-)
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QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
PATCH 1/1 arm64: dts: sc7180: Add qupv3_0 and qupv3_1
Add QUP SE instances configuration for sc7180.
Signed-off-by Roja Rani Yarubandi <[email protected]>
--- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 152 +++++- arch/arm64/boot/dts/qcom/sc7180.dtsi | 683 +++++++++++++++++++++++- 2 files changed, 828 insertions(+), 7 deletions(-)
arch/arm64/boot/dts/qcom/sc7180-idp.dts +149 -3
@@ -17,7 +17,8 @@ compatible = "qcom,sc7180-idp"; aliases { - serial0 = &uart10; + hsuart0 = &uart3; + serial0 = &uart8; }; chosen {
@@ -231,17 +232,101 @@ }; }; +&qupv3_id_0 { + status = "okay"; +}; + &qupv3_id_1 { status = "okay"; }; -&uart10 { +&uart3 { + status = "okay"; +}; + +&uart8 { status = "okay"; }; /* PINCTRL - additions to nodes defined in sc7180.dtsi */ -&qup_uart10_default { +&qup_i2c2_default { + pinconf { + pins = "gpio15", "gpio16"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c4_default { + pinconf { + pins = "gpio115", "gpio116"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_i2c7_default { + pinconf { + pins = "gpio6", "gpio7"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_i2c9_default { + pinconf { + pins = "gpio46", "gpio47"; + drive-strength = <2>; + + /* Has external pullup */ + bias-disable; + }; +}; + +&qup_uart3_default { + pinconf-cts { + /* + * Configure a pull-down on 38 (CTS) to match the pull of + * the Bluetooth module. + */ + pins = "gpio38"; + bias-pull-down; + output-high; + }; + + pinconf-rts { + /* We'll drive 39 (RTS), so no pull */ + pins = "gpio39"; + drive-strength = <2>; + bias-disable; + }; + + pinconf-tx { + /* We'll drive 40 (TX), so no pull */ + pins = "gpio40"; + drive-strength = <2>; + bias-disable; + output-high; + }; + + pinconf-rx { + /* + * Configure a pull-up on 41 (RX). This is needed to avoid + * garbage data when the TX pin of the Bluetooth module is + * in tri-state (module powered off or not driving the + * signal yet). + */ + pins = "gpio41"; + bias-pull-up; + }; +}; + +&qup_uart8_default { pinconf-tx { pins = "gpio44"; drive-strength = <2>;
@@ -254,3 +339,64 @@ bias-pull-up; }; }; + +&qup_spi0_default { + pinconf { + pins = "gpio34", "gpio35", "gpio36", "gpio37"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_spi6_default { + pinconf { + pins = "gpio59", "gpio60", "gpio61", "gpio62"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qup_spi10_default { + pinconf { + pins = "gpio86", "gpio87", "gpio88", "gpio89"; + drive-strength = <2>; + bias-disable; + }; +}; + +&qspi { + status = "okay"; + pinctrl-names = "default"; + pinctrl-0 = <&qspi_clk &qspi_cs0 &qspi_data01>; + + flash@0 { + compatible = "jedec,spi-nor"; + reg = <0>; + spi-max-frequency = <25000000>; + spi-tx-bus-width = <2>; + spi-rx-bus-width = <2>; + }; +}; + +&qspi_cs0 { + pinconf { + pins = "gpio68"; + bias-disable; + }; +}; + +&qspi_clk { + pinconf { + pins = "gpio63"; + bias-disable; + }; +}; + +&qspi_data01 { + pinconf { + pins = "gpio64", "gpio65"; + + /* High-Z when no transfers; nice to park the lines */ + bias-pull-up; + }; +};
arch/arm64/boot/dts/qcom/sc7180.dtsi +679 -4
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Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 1/1] arm64: dts: sc7180: Add qupv3_0 and qupv3_1
Quoted 13 lines · Roja Rani Yarubandi
Add QUP SE instances configuration for sc7180.
Signed-off-by Roja Rani Yarubandi <[email protected]>--- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 152 +++++- arch/arm64/boot/dts/qcom/sc7180.dtsi | 683 +++++++++++++++++++++++- 2 files changed, 828 insertions(+), 7 deletions(-)arch/arm64/boot/dts/qcom/sc7180-idp.dts +0
-0
arch/arm64/boot/dts/qcom/sc7180-idp.dts line 20
Quoted 4 lines
arch/arm64/boot/dts/qcom/sc7180-idp.dts +0
-1@@ -17,7 +17,8 @@ compatible = "qcom,sc7180-idp"; aliases { - serial0 = &uart10;
I will fix this up in the patch that added this when I respin. I seemed to have overlooked the fact that each QUP instance on sc7180 has only 6 SEs (and not 8)
Quoted 2 lines
arch/arm64/boot/dts/qcom/sc7180-idp.dts +2
-0+ hsuart0 = &uart3; + serial0 = &uart8;
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH 1/1] arm64: dts: sc7180: Add qupv3_0 and qupv3_1
In reply to Roja Rani Yarubandiarch/arm64/boot/dts/qcom/sc7180-idp.dts
Quoted 12 lines · Roja Rani Yarubandi
Add QUP SE instances configuration for sc7180.
Signed-off-by Roja Rani Yarubandi <[email protected]>--- arch/arm64/boot/dts/qcom/sc7180-idp.dts | 152 +++++- arch/arm64/boot/dts/qcom/sc7180.dtsi | 683 +++++++++++++++++++++++- 2 files changed, 828 insertions(+), 7 deletions(-)arch/arm64/boot/dts/qcom/sc7180-idp.dts +0
-0
[]..
arch/arm64/boot/dts/qcom/sc7180-idp.dts
Quoted 3 lines
tlmm: pinctrl@3500000 {arch/arm64/boot/dts/qcom/sc7180-idp.dts +0
-0@@ -230,12 +623,294 @@
[]..
Quoted 37 lines
arch/arm64/boot/dts/qcom/sc7180-idp.dts +37
-0+ + qup_i2c0_default: qup-i2c0-default { + pinmux { + pins = "gpio34", "gpio35"; + function = "qup00"; + }; + }; + + qup_i2c1_default: qup-i2c1-default { + pinmux { + pins = "gpio0", "gpio1"; + function = "qup01"; + }; + }; + + qup_i2c2_default: qup-i2c2-default { + pinmux { + pins = "gpio15", "gpio16"; + function = "qup02"; + }; + }; + + qup_i2c3_default: qup-i2c3-default { + pinmux { + pins = "gpio38", "gpio39"; + function = "qup03"; + }; + }; + + qup_i2c4_default: qup-i2c4-default { + pinmux { + pins = "gpio115", "gpio116"; + function = "qup04"; + }; + }; + + qup_i2c5_default: qup-i2c5-default {
arch/arm64/boot/dts/qcom/sc7180-idp.dts line 669
Quoted 10 lines
arch/arm64/boot/dts/qcom/sc7180-idp.dts +10
-0+ pinmux { + pins = "gpio25", "gpio26"; + function = "qup05"; + }; + }; + + qup_i2c6_default: qup-i2c6-default { + pinmux { + pins = "gpio59", "gpio60"; + function = "qup06";
The pinctrl driver has no functions named qup06/07/08/09 These are the qup functions listed
FUNCTION(qup00),
FUNCTION(qup01),
FUNCTION(qup02),
FUNCTION(qup03),
FUNCTION(qup04),
FUNCTION(qup05),
FUNCTION(qup10),
FUNCTION(qup11),
FUNCTION(qup12),
FUNCTION(qup13),
FUNCTION(qup14),
FUNCTION(qup15),Quoted 212 lines
arch/arm64/boot/dts/qcom/sc7180-idp.dts +203
-1+ }; + }; + + qup_i2c7_default: qup-i2c7-default { + pinmux { + pins = "gpio6", "gpio7"; + function = "qup07"; + }; + }; + + qup_i2c8_default: qup-i2c8-default { + pinmux { + pins = "gpio42", "gpio43"; + function = "qup08"; + }; + }; + + qup_i2c9_default: qup-i2c9-default { + pinmux { + pins = "gpio46", "gpio47"; + function = "qup09"; + }; + }; + + qup_i2c10_default: qup-i2c10-default { + pinmux { + pins = "gpio86", "gpio87"; + function = "qup10"; + }; + }; + + qup_i2c11_default: qup-i2c11-default { + pinmux { + pins = "gpio53", "gpio54"; + function = "qup11"; + }; + }; + + qup_spi0_default: qup-spi0-default { + pinmux { + pins = "gpio34", "gpio35", + "gpio36", "gpio37"; + function = "qup00"; + }; + }; + + qup_spi1_default: qup-spi1-default { + pinmux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3", + "gpio12", "gpio94"; + function = "qup01"; + }; + }; + + qup_spi3_default: qup-spi3-default { + pinmux { + pins = "gpio38", "gpio39", + "gpio40", "gpio41"; + function = "qup03"; + }; + }; + + qup_spi5_default: qup-spi5-default { + pinmux { + pins = "gpio25", "gpio26", + "gpio27", "gpio28"; + function = "qup05"; + }; + }; + + qup_spi6_default: qup-spi6-default { + pinmux { + pins = "gpio59", "gpio60", + "gpio61", "gpio62", + "gpio68", "gpio72"; + function = "qup06"; + }; + }; + + qup_spi8_default: qup-spi8-default { + pinmux { + pins = "gpio42", "gpio43", + "gpio44", "gpio45"; + function = "qup08"; + }; + }; + + qup_spi10_default: qup-spi10-default { + pinmux { + pins = "gpio86", "gpio87", + "gpio88", "gpio89", + "gpio90", "gpio91"; + function = "qup10"; + }; + }; + + qup_spi11_default: qup-spi11-default { + pinmux { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + function = "qup11"; + }; + }; + + qup_uart0_default: qup-uart0-default { + pinmux { + pins = "gpio34", "gpio35", + "gpio36", "gpio37"; + function = "qup00"; + }; + }; + + qup_uart1_default: qup-uart1-default { + pinmux { + pins = "gpio0", "gpio1", + "gpio2", "gpio3"; + function = "qup01"; + }; + }; + + qup_uart2_default: qup-uart2-default { + pinmux { + pins = "gpio15", "gpio16"; + function = "qup02"; + }; + }; + + qup_uart3_default: qup-uart3-default { + pinmux { + pins = "gpio38", "gpio39", + "gpio40", "gpio41"; + function = "qup03"; + }; + }; + + qup_uart4_default: qup-uart4-default { + pinmux { + pins = "gpio115", "gpio116"; + function = "qup04"; + }; + }; + + qup_uart5_default: qup-uart5-default { + pinmux { + pins = "gpio25", "gpio26", + "gpio27", "gpio28"; + function = "qup05"; + }; + }; + + qup_uart6_default: qup-uart6-default { + pinmux { + pins = "gpio59", "gpio60", + "gpio61", "gpio62"; + function = "qup06"; + }; + }; + + qup_uart7_default: qup-uart7-default { + pinmux { + pins = "gpio6", "gpio7"; + function = "qup07"; + }; + }; + + qup_uart8_default: qup-uart8-default { pinmux { pins = "gpio44", "gpio45"; - function = "qup12"; + function = "qup08"; + }; + }; + + qup_uart9_default: qup-uart9-default { + pinmux { + pins = "gpio46", "gpio47"; + function = "qup09"; }; }; + + qup_uart10_default: qup-uart10-default { + pinmux { + pins = "gpio86", "gpio87", + "gpio88", "gpio89"; + function = "qup10"; + }; + }; + + qup_uart11_default: qup-uart11-default { + pinmux { + pins = "gpio53", "gpio54", + "gpio55", "gpio56"; + function = "qup11"; + }; + }; + }; + + qspi: spi@88dc000 { + compatible = "qcom,qspi-v1"; + reg = <0 0x088dc000 0 0x600>; + #address-cells = <1>; + #size-cells = <0>; + interrupts = <GIC_SPI 119 IRQ_TYPE_LEVEL_HIGH>; + clocks = <&gcc GCC_QSPI_CNOC_PERIPH_AHB_CLK>, + <&gcc GCC_QSPI_CORE_CLK>; + clock-names = "iface", "core"; + status = "disabled"; }; spmi_bus: spmi@c440000 {
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation