reset: npcm: add NPCM reset driver support

This patch set adds reset controller support
for the Nuvoton NPCM Baseboard Management Controller (BMC).

Apart of controlling all NPCM BMC reset module lines the NPCM reset driver support NPCM BMC software reset to restarting the NPCM BMC.

Supporting NPCM USB-PHY reset as follow:

NPCM BMC USB-PHY connected to two modules USB device (UDC) and USB host.

If we will restart the USB-PHY at the UDC probe and later the USB host probe will restart USB-PHY again it will disable the UDC and vice versa.

The solution is to reset the USB-PHY at the reset probe stage before the UDC and the USB host are initializing.

NPCM reset driver tested on NPCM750 evaluation board.

Addressed comments from:.
- Philipp Zabel : https://lkml.org/lkml/2019/10/29/712

                                   https://lkml.org/lkml/2019/10/29/713
                                   https://lkml.org/lkml/2019/10/29/731

- kbuild test robot : https://lkml.org/lkml/2019/10/30/29

Changes since version 2:
- Remove unnecessary details in the dt-binding documentation.
- Modify device tree binding constants.
- initialize gcr_regmap parameter to NULL.
- Add of_xlate support.
- Enable NPCM reset driver by default.
- Remove unused header include.
- Using devm_platform_ioremap_resource instead of_address_to_resource and devm_ioremap_resource.
- Modify number of resets.
- Using devm_reset_controller_register instead reset_controller_register.
- Remove unnecessary probe print.

Changes since version 1:
- Check if gcr_regmap parameter initialized before using it.

Tomer Maimon (3):
dt-binding: reset: add NPCM reset controller documentation
dt-bindings: reset: Add binding constants for NPCM7xx reset controller
reset: npcm: add NPCM reset controller driver

 .../bindings/reset/nuvoton,npcm-reset.txt     |  32 ++
 drivers/reset/Kconfig                         |   7 +
 drivers/reset/Makefile                        |   1 +
 drivers/reset/reset-npcm.c                    | 281 ++++++++++++++++++
 .../dt-bindings/reset/nuvoton,npcm7xx-reset.h |  91 ++++++
 5 files changed, 412 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt
 create mode 100644 drivers/reset/reset-npcm.c
 create mode 100644 include/dt-bindings/reset/nuvoton,npcm7xx-reset.h

--
2.22.0

===========================================================================================
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Added device tree binding documentation for Nuvoton BMC NPCM reset controller.

---
 .../bindings/reset/nuvoton,npcm-reset.txt     | 32 +++++++++++++++++++
 1 file changed, 32 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/reset/nuvoton,npcm-reset.txt

new file mode 100644
index 000000000000..6e802703af60
@@ -0,0 +1,32 @@
+Nuvoton NPCM Reset controller
+
+Required properties:
+- compatible : "nuvoton,npcm750-reset" for NPCM7XX BMC
+- reg : specifies physical base address and size of the register.
+- #reset-cells: must be set to 2
+
+Optional property:
+- nuvoton,sw-reset-number - Contains the software reset number to restart the SoC.
+  NPCM7xx contain four software reset that represent numbers 1 to 4.
+
+  If 'nuvoton,sw-reset-number' is not specfied software reset is disabled.
+
+Example:
+       rstc: rstc@f0801000 {
+               compatible = "nuvoton,npcm750-reset";
+               reg = <0xf0801000 0x70>;
+               #reset-cells = <2>;
+               nuvoton,sw-reset-number = <2>;
+       };
+
+Specifying reset lines connected to IP NPCM7XX modules
+======================================================
+example:
+
+        spi0: spi@..... {
+                ...
+                resets = <&rstc NPCM7XX_RESET_IPSRST2 NPCM7XX_RESET_PSPI1>;
+                ...
+        };
+
+The index could be found in <dt-bindings/reset/nuvoton,npcm7xx-reset.h>.

--
2.22.0

===========================================================================================
The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

'dt-bindings' for the subject.

We can't accept patches with this footer.

Rob

Add device tree binding constants for Nuvoton BMC NPCM7xx reset controller.

---
 .../dt-bindings/reset/nuvoton,npcm7xx-reset.h | 91 +++++++++++++++++++
 1 file changed, 91 insertions(+)
 create mode 100644 include/dt-bindings/reset/nuvoton,npcm7xx-reset.h

new file mode 100644
index 000000000000..df088e68a9ba
@@ -0,0 +1,91 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+// Copyright (c) 2019 Nuvoton Technology corporation.
+
+#ifndef _DT_BINDINGS_NPCM7XX_RESET_H
+#define _DT_BINDINGS_NPCM7XX_RESET_H
+
+#define NPCM7XX_RESET_IPSRST1          0x20
+#define NPCM7XX_RESET_IPSRST2          0x24
+#define NPCM7XX_RESET_IPSRST3          0x34
+
+/* Reset lines on IP1 reset module (NPCM7XX_RESET_IPSRST1) */
+#define NPCM7XX_RESET_FIU3             1
+#define NPCM7XX_RESET_UDC1             5
+#define NPCM7XX_RESET_EMC1             6
+#define NPCM7XX_RESET_UART_2_3         7
+#define NPCM7XX_RESET_UDC2             8
+#define NPCM7XX_RESET_PECI             9
+#define NPCM7XX_RESET_AES              10
+#define NPCM7XX_RESET_UART_0_1         11
+#define NPCM7XX_RESET_MC               12
+#define NPCM7XX_RESET_SMB2             13
+#define NPCM7XX_RESET_SMB3             14
+#define NPCM7XX_RESET_SMB4             15
+#define NPCM7XX_RESET_SMB5             16
+#define NPCM7XX_RESET_PWM_M0           18
+#define NPCM7XX_RESET_TIMER_0_4                19
+#define NPCM7XX_RESET_TIMER_5_9                20
+#define NPCM7XX_RESET_EMC2             21
+#define NPCM7XX_RESET_UDC4             22
+#define NPCM7XX_RESET_UDC5             23
+#define NPCM7XX_RESET_UDC6             24
+#define NPCM7XX_RESET_UDC3             25
+#define NPCM7XX_RESET_ADC              27
+#define NPCM7XX_RESET_SMB6             28
+#define NPCM7XX_RESET_SMB7             29
+#define NPCM7XX_RESET_SMB0             30
+#define NPCM7XX_RESET_SMB1             31
+
+/* Reset lines on IP2 reset module (NPCM7XX_RESET_IPSRST2) */
+#define NPCM7XX_RESET_MFT0             0
+#define NPCM7XX_RESET_MFT1             1
+#define NPCM7XX_RESET_MFT2             2
+#define NPCM7XX_RESET_MFT3             3
+#define NPCM7XX_RESET_MFT4             4
+#define NPCM7XX_RESET_MFT5             5
+#define NPCM7XX_RESET_MFT6             6
+#define NPCM7XX_RESET_MFT7             7
+#define NPCM7XX_RESET_MMC              8
+#define NPCM7XX_RESET_SDHC             9
+#define NPCM7XX_RESET_GFX_SYS          10
+#define NPCM7XX_RESET_AHB_PCIBRG       11
+#define NPCM7XX_RESET_VDMA             12
+#define NPCM7XX_RESET_ECE              13
+#define NPCM7XX_RESET_VCD              14
+#define NPCM7XX_RESET_OTP              16
+#define NPCM7XX_RESET_SIOX1            18
+#define NPCM7XX_RESET_SIOX2            19
+#define NPCM7XX_RESET_3DES             21
+#define NPCM7XX_RESET_PSPI1            22
+#define NPCM7XX_RESET_PSPI2            23
+#define NPCM7XX_RESET_GMAC2            25
+#define NPCM7XX_RESET_USB_HOST         26
+#define NPCM7XX_RESET_GMAC1            28
+#define NPCM7XX_RESET_CP               31
+
+/* Reset lines on IP3 reset module (NPCM7XX_RESET_IPSRST3) */
+#define NPCM7XX_RESET_PWM_M1           0
+#define NPCM7XX_RESET_SMB12            1
+#define NPCM7XX_RESET_SPIX             2
+#define NPCM7XX_RESET_SMB13            3
+#define NPCM7XX_RESET_UDC0             4
+#define NPCM7XX_RESET_UDC7             5
+#define NPCM7XX_RESET_UDC8             6
+#define NPCM7XX_RESET_UDC9             7
+#define NPCM7XX_RESET_PCI_MAILBOX      9
+#define NPCM7XX_RESET_SMB14            12
+#define NPCM7XX_RESET_SHA              13
+#define NPCM7XX_RESET_SEC_ECC          14
+#define NPCM7XX_RESET_PCIE_RC          15
+#define NPCM7XX_RESET_TIMER_10_14      16
+#define NPCM7XX_RESET_RNG              17
+#define NPCM7XX_RESET_SMB15            18
+#define NPCM7XX_RESET_SMB8             19
+#define NPCM7XX_RESET_SMB9             20
+#define NPCM7XX_RESET_SMB10            21
+#define NPCM7XX_RESET_SMB11            22
+#define NPCM7XX_RESET_ESPI             23
+#define NPCM7XX_RESET_USB_PHY_1                24
+#define NPCM7XX_RESET_USB_PHY_2                25
+
+#endif

--
2.22.0

===========================================================================================
The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.

Add Nuvoton NPCM BMC reset controller driver.

---
 drivers/reset/Kconfig      |   7 +
 drivers/reset/Makefile     |   1 +
 drivers/reset/reset-npcm.c | 281 +++++++++++++++++++++++++++++++++++++
 3 files changed, 289 insertions(+)
 create mode 100644 drivers/reset/reset-npcm.c

index 7b07281aa0ae..9e3eac30e7db 100644
@@ -89,6 +89,13 @@ config RESET_MESON_AUDIO_ARB
          This enables the reset driver for Audio Memory Arbiter of
          Amlogic's A113 based SoCs
 
+config RESET_NPCM
+       bool "NPCM BMC Reset Driver" if COMPILE_TEST
+       default ARCH_NPCM
+       help
+         This enables the reset controller driver for Nuvoton NPCM
+         BMC SoCs.
+
 config RESET_OXNAS
        bool
 

index cf60ce526064..00767c03f5f2 100644
@@ -14,6 +14,7 @@ obj-$(CONFIG_RESET_LANTIQ) += reset-lantiq.o
 obj-$(CONFIG_RESET_LPC18XX) += reset-lpc18xx.o
 obj-$(CONFIG_RESET_MESON) += reset-meson.o
 obj-$(CONFIG_RESET_MESON_AUDIO_ARB) += reset-meson-audio-arb.o
+obj-$(CONFIG_RESET_NPCM) += reset-npcm.o
 obj-$(CONFIG_RESET_OXNAS) += reset-oxnas.o
 obj-$(CONFIG_RESET_PISTACHIO) += reset-pistachio.o
 obj-$(CONFIG_RESET_QCOM_AOSS) += reset-qcom-aoss.o

--
2.22.0

===========================================================================================
The privileged confidential information contained in this email is intended for use only by the addressees as indicated by the original sender of this email. If you are not the addressee indicated in this email or are not responsible for delivery of the email to such a person, please kindly reply to the sender indicating this fact and delete all copies of it from your computer and network server immediately. Your cooperation is highly appreciated. It is advised that any unauthorized use of confidential information of Nuvoton is strictly prohibited; and any information in this email irrelevant to the official business of Nuvoton shall be deemed as neither given nor endorsed by Nuvoton.