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serial: cadence: fix serial_flush

PATCH Applied Lucas Stach 2 participants 2 messages Nov 1, 2019 – Nov 4, 2019

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Lucas Stach

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PATCH 1/1 serial: cadence: fix serial_flush

The TXEMPTY bit gets set as soon as the transmit FIFO gets empty, so flushing must wait until the bit is set instead of being unset.

Signed-off-by Lucas Stach <[email protected]>
---
 drivers/serial/serial_cadence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/serial/serial_cadence.c +1 -1
index 0501c400b129..6454888e3c5b 100644
@@ -199,7 +199,7 @@ static void cadence_serial_flush(struct console_device *cdev)
 					struct cadence_serial_priv, cdev);
 
 	while ((readl(priv->regs + CADENCE_UART_CHANNEL_STS) &
-		CADENCE_STS_TEMPTY) != 0)
+		CADENCE_STS_TEMPTY) == 0)
 		;
 }
Signature · 7 lines
2.23.0


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Applied
#1 lore raw
Quoted 7 lines · Lucas Stach

The TXEMPTY bit gets set as soon as the transmit FIFO gets empty, so flushing must wait until the bit is set instead of being unset.

Signed-off-by Lucas Stach <[email protected]>
---
 drivers/serial/serial_cadence.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Applied, thanks

Sascha

Signature · 9 lines
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