Zynq multi-image conversion and improvements

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deleted file mode 100644
index 3d35fe988090..000000000000
@@ -1,8 +0,0 @@
-#define PRE_IMAGE \
-	.pre_image : {					\
-		. = 0x20;				\
-		KEEP(*(.flash_header_0x0*))		\
-		. = 0xa0;				\
-		KEEP(*(.ps7reg_entry_0x0A0))		\
-		. = 0x8c0;				\
-	}

index 3b67e55a7115..ba4b67f479e9 100644
@@ -1,38 +1,27 @@
 #ifndef __MACH_FLASH_HEADER_H
 #define __MACH_FLASH_HEADER_H
 
-#include <asm-generic/sections.h>
+#include <stdint.h>
 
-#define __flash_header_section		__section(.flash_header_0x0)
-#define __ps7reg_entry_section		__section(.ps7reg_entry_0x0A0)
-#define __image_len_section		__section(.image_len_0x08c0)
-#define FLASH_HEADER_OFFSET		0x0
+#define REGINIT_OFFSET			0x0a0
 #define IMAGE_OFFSET			0x8c0
 
-#define DEST_BASE			0x8c0
-#define FLASH_HEADER_BASE	(DEST_BASE + FLASH_HEADER_OFFSET)
-
-struct zynq_reg_entry {
-	__le32 addr;
-	__le32 val;
-};
-
 #define WIDTH_DETECTION_MAGIC	0xAA995566
 #define IMAGE_IDENTIFICATION	0x584C4E58	/* "XLNX" */
 
 struct zynq_flash_header {
-	__le32 width_det;
-	__le32 image_id;
-	__le32 enc_stat;
-	__le32 user;
-	__le32 flash_offset;
-	__le32 length;
-	__le32 res0;
-	__le32 start_of_exec;
-	__le32 total_len;
-	__le32 res1;
-	__le32 checksum;
-	__le32 res2;
+	uint32_t width_det;
+	uint32_t image_id;
+	uint32_t enc_stat;
+	uint32_t user;
+	uint32_t flash_offset;
+	uint32_t length;
+	uint32_t res0;
+	uint32_t start_of_exec;
+	uint32_t total_len;
+	uint32_t res1;
+	uint32_t checksum;
+	uint32_t res2;
 };
 
 #endif /* __MACH_FLASH_HEADER_H */

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index b6ca8eb2be27..68b78a13a962 100644
@@ -7,8 +7,7 @@
 #define STRUCT_ALIGN() . = ALIGN(STRUCT_ALIGNMENT)
 
 #if defined CONFIG_X86 || \
-	defined CONFIG_ARCH_EP93XX || \
-	defined CONFIG_ARCH_ZYNQ
+	defined CONFIG_ARCH_EP93XX
 #include <mach/barebox.lds.h>
 #endif
 

283 lines not on this page · raw message

index bf214ca5d0d1..0a1c069472e9 100644
@@ -283,6 +283,11 @@ int main(int argc, char *argv[])
 		exit(EXIT_FAILURE);
 	}
 
+	if (st.st_size > 192 * 1024) {
+		fprintf(stderr, "Image too big, will not fit in OCRAM!\n");
+		exit(EXIT_FAILURE);
+	}
+
 	buf = calloc(st.st_size + IMAGE_OFFSET, sizeof(char));
 	if (!buf) {
 		fprintf(stderr, "Unable to allocate buffer\n");

index cf3c4ebd0c7e..ae279e4e64af 100644
@@ -27,8 +27,13 @@
 #define PLL_DDR_LOCK	(1 << 1)
 #define PLL_IO_LOCK	(1 << 2)
 
+extern char __dtb_zynq_zed_start[];
+
 void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
 {
+
+	void *fdt = __dtb_zynq_zed_start + get_runtime_offset();
+
 	/* open sesame */
 	writel(0x0000DF0D, ZYNQ_SLCR_UNLOCK);
 

@@ -257,5 +262,6 @@ void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
 	writel(0x0000767B, ZYNQ_SLCR_LOCK);
 
 	arm_cpu_lowlevel_init();
-	barebox_arm_entry(0, SZ_512M, NULL);
+
+	barebox_arm_entry(0, SZ_512M, fdt);
 }

index c4ab9efb639c..df1e606454b1 100644
@@ -69,7 +69,7 @@ struct macb_device {
 
 	int			phy_addr;
 
-	struct clk		*pclk;
+	struct clk		*pclk, *hclk, *txclk, *rxclk;
 	const struct device_d	*dev;
 	struct eth_device	netdev;
 

@@ -653,7 +653,7 @@ static int macb_probe(struct device_d *dev)
 	struct resource *iores;
 	struct eth_device *edev;
 	struct macb_device *macb;
-	const char *pclk_name;
+	const char *pclk_name, *hclk_name;
 	u32 ncfgr;
 
 	macb = xzalloc(sizeof(*macb));

@@ -689,6 +689,7 @@ static int macb_probe(struct device_d *dev)
 		macb->phy_addr = pdata->phy_addr;
 		macb->phy_flags = pdata->phy_flags;
 		pclk_name = "macb_clk";
+		hclk_name = NULL;
 	} else if (IS_ENABLED(CONFIG_OFDEVICE) && dev->device_node) {
 		int ret;
 		struct device_node *mdiobus;

@@ -705,6 +706,7 @@ static int macb_probe(struct device_d *dev)
 
 		macb->phy_addr = -1;
 		pclk_name = "pclk";
+		hclk_name = "hclk";
 	} else {
 		dev_err(dev, "macb: no platform_data\n");
 		return -ENODEV;

@@ -727,6 +729,24 @@ static int macb_probe(struct device_d *dev)
 
 	clk_enable(macb->pclk);
 
+	if (hclk_name) {
+		macb->hclk = clk_get(dev, pclk_name);
+		if (IS_ERR(macb->pclk)) {
+			dev_err(dev, "no hclk\n");
+			return PTR_ERR(macb->hclk);
+		}
+
+		clk_enable(macb->hclk);
+	}
+
+	macb->txclk = clk_get(dev, "tx_clk");
+	if (!IS_ERR(macb->txclk))
+		clk_enable(macb->txclk);
+
+	macb->rxclk = clk_get(dev, "rx_clk");
+	if (!IS_ERR(macb->rxclk))
+		clk_enable(macb->rxclk);
+
 	macb->is_gem = read_is_gem(macb);
 
 	if (macb_is_gem(macb))

index df1e606454b1..4850e60c49ab 100644
@@ -792,6 +792,7 @@ static const struct of_device_id macb_dt_ids[] = {
 	{ .compatible = "cdns,at91sam9260-macb",},
 	{ .compatible = "atmel,sama5d2-gem",},
 	{ .compatible = "atmel,sama5d3-gem",},
+	{ .compatible = "cdns,zynq-gem",},
 	{ .compatible = "cdns,zynqmp-gem",},
 	{ /* sentinel */ }
 };

similarity index 100%
rename from arch/arm/mach-zynq/clk-zynq7000.c
rename to drivers/clk/zynq/clkc.c

index f6112fd249ce..ec22b16c91cd 100644
@@ -48,7 +48,8 @@ static int zynq_init(void)
 	writel(val, 0xf8f00000);
 	dmb();
 
-	add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE, 0x4000, IORESOURCE_MEM, NULL);
+	add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE + 0x100,
+			   0x4000, IORESOURCE_MEM, NULL);
 	add_generic_device("smp_twd", 0, NULL, CORTEXA9_SCU_TIMER_BASE_ADDR,
 				0x4000, IORESOURCE_MEM, NULL);
 	restart_handler_register_fn(zynq_restart_soc);

index cd49d8478f58..ba441740c585 100644
@@ -360,38 +360,38 @@ static struct clk *zynq_cpu_subclk(const char *name,
 static int zynq_clock_probe(struct device_d *dev)
 {
 	struct resource *iores;
-	void __iomem *slcr_base;
+	void __iomem *clk_base;
 	unsigned long ps_clk_rate = 33333330;
 
 	iores = dev_request_mem_resource(dev, 0);
 	if (IS_ERR(iores))
 		return PTR_ERR(iores);
-	slcr_base = IOMEM(iores->start);
+	clk_base = IOMEM(iores->start);
 
 	clks[ps_clk]  = clk_fixed("ps_clk", ps_clk_rate);
 
-	clks[arm_pll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", slcr_base + 0x100);
-	clks[ddr_pll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", slcr_base + 0x104);
-	clks[io_pll]  = zynq_pll_clk(ZYNQ_PLL_IO,  "io_pll", slcr_base + 0x108);
+	clks[arm_pll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", clk_base + 0x0);
+	clks[ddr_pll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", clk_base + 0x4);
+	clks[io_pll]  = zynq_pll_clk(ZYNQ_PLL_IO,  "io_pll", clk_base + 0x8);
 
-	clks[uart_clk] = zynq_periph_clk("uart_clk", slcr_base + 0x154);
+	clks[uart_clk] = zynq_periph_clk("uart_clk", clk_base + 0x54);
 
-	clks[uart0] = clk_gate("uart0", "uart_clk", slcr_base + 0x154, 0, 0, 0);
-	clks[uart1] = clk_gate("uart1", "uart_clk", slcr_base + 0x154, 1, 0, 0);
+	clks[uart0] = clk_gate("uart0", "uart_clk", clk_base + 0x54, 0, 0, 0);
+	clks[uart1] = clk_gate("uart1", "uart_clk", clk_base + 0x54, 1, 0, 0);
 
-	clks[gem0] = clk_gate("gem0", "io_pll", slcr_base + 0x140, 0, 0, 0);
-	clks[gem1] = clk_gate("gem1", "io_pll", slcr_base + 0x144, 1, 0, 0);
+	clks[gem0] = clk_gate("gem0", "io_pll", clk_base + 0x40, 0, 0, 0);
+	clks[gem1] = clk_gate("gem1", "io_pll", clk_base + 0x44, 1, 0, 0);
 
-	clks[cpu_clk] = zynq_cpu_clk("cpu_clk", slcr_base + 0x120);
+	clks[cpu_clk] = zynq_cpu_clk("cpu_clk", clk_base + 0x20);
 
 	clks[cpu_6x4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X,
-					slcr_base + 0x120, slcr_base + 0x1C4);
+					clk_base + 0x20, clk_base + 0xC4);
 	clks[cpu_3x2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X,
-					slcr_base + 0x120, slcr_base + 0x1C4);
+					clk_base + 0x20, clk_base + 0xC4);
 	clks[cpu_2x] = zynq_cpu_subclk("cpu_2x", CPU_SUBCLK_2X,
-					slcr_base + 0x120, slcr_base + 0x1C4);
+					clk_base + 0x20, clk_base + 0xC4);
 	clks[cpu_1x] = zynq_cpu_subclk("cpu_1x", CPU_SUBCLK_1X,
-					slcr_base + 0x120, slcr_base + 0x1C4);
+					clk_base + 0x20, clk_base + 0xC4);
 
 	clk_register_clkdev(clks[cpu_3x2x], NULL, "arm_smp_twd");
 	clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");

index ba441740c585..07152e2ada3f 100644
@@ -48,6 +48,8 @@ enum zynq_pll_type {
 #define PLL_STATUS_DDR_PLL_STABLE	(1 << 1)
 #define PLL_STATUS_IO_PLL_STABLE	(1 << 2)
 #define PLL_CTRL_BYPASS_FORCE		(1 << 4)
+#define PLL_CTRL_PWRDOWN		(1 << 1)
+#define PLL_CTRL_RESET			(1 << 0)
 
 static struct clk *clks[clks_max];
 

@@ -75,7 +77,7 @@ static int zynq_pll_enable(struct clk *clk)
 	int timeout = 10000;
 
 	val = readl(pll->pll_ctrl);
-	val &= ~PLL_CTRL_BYPASS_FORCE;
+	val &= ~(PLL_CTRL_BYPASS_FORCE | PLL_CTRL_PWRDOWN | PLL_CTRL_RESET);
 	writel(val, pll->pll_ctrl);
 
 	while (timeout--) {

@@ -89,9 +91,18 @@ static int zynq_pll_enable(struct clk *clk)
 	return 0;
 }
 
+static int zynq_pll_is_enabled(struct clk *clk)
+{
+	struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
+	u32 val = readl(pll->pll_ctrl);
+
+	return !(val & (PLL_CTRL_PWRDOWN | PLL_CTRL_RESET));
+}
+
 static struct clk_ops zynq_pll_clk_ops = {
 	.recalc_rate = zynq_pll_recalc_rate,
 	.enable = zynq_pll_enable,
+	.is_enabled = zynq_pll_is_enabled,
 };
 
 static inline struct clk *zynq_pll_clk(enum zynq_pll_type type,

index 07152e2ada3f..2a855d286fcd 100644
@@ -29,10 +29,16 @@
 #include <mach/zynq7000-regs.h>
 #include <malloc.h>
 
-enum zynq_clks {
-	dummy, ps_clk, arm_pll, ddr_pll, io_pll, uart_clk, uart0, uart1,
-	cpu_clk, cpu_6x4x, cpu_3x2x, cpu_2x, cpu_1x,
-	gem_clk, gem0, gem1, clks_max
+enum zynq_clk {
+	armpll, ddrpll, iopll,
+	cpu_6or4x, cpu_3or2x, cpu_2x, cpu_1x,
+	ddr2x, ddr3x, dci,
+	lqspi, smc, pcap, gem0, gem1, fclk0, fclk1, fclk2, fclk3, can0, can1,
+	sdio0, sdio1, uart0, uart1, spi0, spi1, dma,
+	usb0_aper, usb1_aper, gem0_aper, gem1_aper,
+	sdio0_aper, sdio1_aper, spi0_aper, spi1_aper, can0_aper, can1_aper,
+	i2c0_aper, i2c1_aper, uart0_aper, uart1_aper, gpio_aper, lqspi_aper,
+	smc_aper, swdt, dbg_trc, dbg_apb, clk_max
 };
 
 enum zynq_pll_type {

@@ -51,7 +57,8 @@ enum zynq_pll_type {
 #define PLL_CTRL_PWRDOWN		(1 << 1)
 #define PLL_CTRL_RESET			(1 << 0)
 
-static struct clk *clks[clks_max];
+static struct clk *clks[clk_max];
+static struct clk_onecell_data clk_data;
 
 struct zynq_pll_clk {
 	struct clk	clk;

@@ -96,6 +103,7 @@ static int zynq_pll_is_enabled(struct clk *clk)
 	struct zynq_pll_clk *pll = to_zynq_pll_clk(clk);
 	u32 val = readl(pll->pll_ctrl);
 
+
 	return !(val & (PLL_CTRL_PWRDOWN | PLL_CTRL_RESET));
 }
 

@@ -379,46 +387,94 @@ static int zynq_clock_probe(struct device_d *dev)
 		return PTR_ERR(iores);
 	clk_base = IOMEM(iores->start);
 
-	clks[ps_clk]  = clk_fixed("ps_clk", ps_clk_rate);
+	clk_fixed("ps_clk", ps_clk_rate);
 
-	clks[arm_pll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", clk_base + 0x0);
-	clks[ddr_pll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", clk_base + 0x4);
-	clks[io_pll]  = zynq_pll_clk(ZYNQ_PLL_IO,  "io_pll", clk_base + 0x8);
+	clks[armpll] = zynq_pll_clk(ZYNQ_PLL_ARM, "arm_pll", clk_base + 0x0);
+	clks[ddrpll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", clk_base + 0x4);
+	clks[iopll] = zynq_pll_clk(ZYNQ_PLL_IO,  "io_pll", clk_base + 0x8);
 
-	clks[uart_clk] = zynq_periph_clk("uart_clk", clk_base + 0x54);
+	zynq_periph_clk("sdio_clk", clk_base + 0x50);
+	clks[sdio0] = clk_gate("sdio0", "sdio_clk", clk_base + 0x50, 0, 0, 0);
+	clks[sdio1] = clk_gate("sdio1", "sdio_clk", clk_base + 0x50, 1, 0, 0);
 
+	zynq_periph_clk("uart_clk", clk_base + 0x54);
 	clks[uart0] = clk_gate("uart0", "uart_clk", clk_base + 0x54, 0, 0, 0);
 	clks[uart1] = clk_gate("uart1", "uart_clk", clk_base + 0x54, 1, 0, 0);
 
+	zynq_periph_clk("spi_clk", clk_base + 0x58);
+	clks[spi0] = clk_gate("spi0", "spi_clk", clk_base + 0x58, 0, 0, 0);
+	clks[spi1] = clk_gate("spi1", "spi_clk", clk_base + 0x58, 1, 0, 0);
+
 	clks[gem0] = clk_gate("gem0", "io_pll", clk_base + 0x40, 0, 0, 0);
 	clks[gem1] = clk_gate("gem1", "io_pll", clk_base + 0x44, 1, 0, 0);
 
-	clks[cpu_clk] = zynq_cpu_clk("cpu_clk", clk_base + 0x20);
+	zynq_cpu_clk("cpu_clk", clk_base + 0x20);
 
-	clks[cpu_6x4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X,
+	clks[cpu_6or4x] = zynq_cpu_subclk("cpu_6x4x", CPU_SUBCLK_6X4X,
 					clk_base + 0x20, clk_base + 0xC4);
-	clks[cpu_3x2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X,
+	clks[cpu_3or2x] = zynq_cpu_subclk("cpu_3x2x", CPU_SUBCLK_3X2X,
 					clk_base + 0x20, clk_base + 0xC4);
 	clks[cpu_2x] = zynq_cpu_subclk("cpu_2x", CPU_SUBCLK_2X,
 					clk_base + 0x20, clk_base + 0xC4);
 	clks[cpu_1x] = zynq_cpu_subclk("cpu_1x", CPU_SUBCLK_1X,
 					clk_base + 0x20, clk_base + 0xC4);
 
-	clk_register_clkdev(clks[cpu_3x2x], NULL, "arm_smp_twd");
+	clks[dma] = clk_gate("dma", "cpu_2x", clk_base + 0x2C, 0, 0, 0);
+	clks[usb0_aper] = clk_gate("usb0_aper", "cpu_1x",
+				   clk_base + 0x2C, 2, 0, 0);
+	clks[usb1_aper] = clk_gate("usb1_aper", "cpu_1x",
+				   clk_base + 0x2C, 3, 0, 0);
+	clks[gem0_aper] = clk_gate("gem0_aper", "cpu_1x",
+				   clk_base + 0x2C, 6, 0, 0);
+	clks[gem1_aper] = clk_gate("gem1_aper", "cpu_1x",
+				   clk_base + 0x2C, 7, 0, 0);
+	clks[sdio0_aper] = clk_gate("sdio0_aper", "cpu_1x",
+				    clk_base + 0x2C, 10, 0, 0);
+	clks[sdio1_aper] = clk_gate("sdio1_aper", "cpu_1x",
+				    clk_base + 0x2C, 11, 0, 0);
+	clks[spi0_aper] = clk_gate("spi0_aper", "cpu_1x",
+				   clk_base + 0x2C, 14, 0, 0);
+	clks[spi1_aper] = clk_gate("spi1_aper", "cpu_1x",
+				   clk_base + 0x2C, 15, 0, 0);
+	clks[can0_aper] = clk_gate("can0_aper", "cpu_1x",
+				   clk_base + 0x2C, 16, 0, 0);
+	clks[can1_aper] = clk_gate("can1_aper", "cpu_1x",
+				   clk_base + 0x2C, 17, 0, 0);
+	clks[i2c0_aper] = clk_gate("i2c0_aper", "cpu_1x",
+				   clk_base + 0x2C, 18, 0, 0);
+	clks[i2c1_aper] = clk_gate("i2c1_aper", "cpu_1x",
+				   clk_base + 0x2C, 19, 0, 0);
+	clks[uart0_aper] = clk_gate("uart0_aper", "cpu_1x",
+				    clk_base + 0x2C, 20, 0, 0);
+	clks[uart1_aper] = clk_gate("uart1_aper", "cpu_1x",
+				    clk_base + 0x2C, 21, 0, 0);
+	clks[gpio_aper] = clk_gate("gpio_aper", "cpu_1x",
+				   clk_base + 0x2C, 22, 0, 0);
+	clks[lqspi_aper] = clk_gate("lqspi_aper", "cpu_1x",
+				    clk_base + 0x2C, 23, 0, 0);
+	clks[smc_aper] = clk_gate("smc_aper", "cpu_1x",
+				  clk_base + 0x2C, 24, 0, 0);
+
+	clk_register_clkdev(clks[cpu_3or2x], NULL, "arm_smp_twd");
 	clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");
 	clk_register_clkdev(clks[uart1], NULL, "zynq_serial1");
 	clk_register_clkdev(clks[gem0], NULL, "macb0");
 	clk_register_clkdev(clks[gem1], NULL, "macb1");
 
-	clkdev_add_physbase(clks[cpu_3x2x], CORTEXA9_SCU_TIMER_BASE_ADDR, NULL);
+	clkdev_add_physbase(clks[cpu_3or2x], CORTEXA9_SCU_TIMER_BASE_ADDR, NULL);
 	clkdev_add_physbase(clks[uart1], ZYNQ_UART1_BASE_ADDR, NULL);
 
+	clk_data.clks = clks;
+	clk_data.clk_num = ARRAY_SIZE(clks);
+	of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,
+			    &clk_data);
+
 	return 0;
 }
 
 static __maybe_unused struct of_device_id zynq_clock_dt_ids[] = {
 	{
-		.compatible = "xlnx,zynq-clock",
+		.compatible = "xlnx,ps7-clkc",
 	}, {
 		/* sentinel */
 	}

index 722bda302e1f..f53dde47c204 100644
@@ -17,38 +17,14 @@
 #include <environment.h>
 #include <generated/mach-types.h>
 #include <init.h>
-#include <mach/devices.h>
 #include <mach/zynq7000-regs.h>
 #include <linux/sizes.h>
 
-static int zedboard_mem_init(void)
-{
-	arm_add_mem_device("ram0", 0, SZ_512M);
-
-	return 0;
-}
-mem_initcall(zedboard_mem_init);
-
-static struct macb_platform_data macb_pdata = {
-	.phy_interface = PHY_INTERFACE_MODE_RGMII,
-	.phy_addr = 0x0,
-};
-
-static int zedboard_device_init(void)
-{
-	zynq_add_eth0(&macb_pdata);
-
-	return 0;
-}
-device_initcall(zedboard_device_init);
 
 static int zedboard_console_init(void)
 {
-	barebox_set_model("Avnet ZedBoard");
 	barebox_set_hostname("zedboard");
 
-	zynq_add_uart1();
-
 	return 0;
 }
 console_initcall(zedboard_console_init);

deleted file mode 100644
index 55e9433c517d..000000000000
@@ -1,13 +0,0 @@
-#include <common.h>
-#include <driver.h>
-#include <mach/devices.h>
-
-struct device_d *zynq_add_uart(resource_size_t base, int id)
-{
-	return add_generic_device("cadence-uart", id, NULL, base, 0x1000, IORESOURCE_MEM, NULL);
-}
-
-struct device_d *zynq_add_eth(resource_size_t base, int id, struct macb_platform_data *pdata)
-{
-	return add_generic_device("macb", id, NULL, base, 0x1000, IORESOURCE_MEM, pdata);
-}

deleted file mode 100644
index c9670b02f30c..000000000000
@@ -1,20 +0,0 @@
-#include <mach/zynq7000-regs.h>
-#include <platform_data/macb.h>
-
-struct device_d *zynq_add_uart(resource_size_t base, int id);
-struct device_d *zynq_add_eth(resource_size_t base, int id, struct macb_platform_data *pdata);
-
-static inline struct device_d *zynq_add_uart0(void)
-{
-	return zynq_add_uart((resource_size_t)ZYNQ_UART0_BASE_ADDR, 0);
-}
-
-static inline struct device_d *zynq_add_uart1(void)
-{
-	return zynq_add_uart((resource_size_t)ZYNQ_UART1_BASE_ADDR, 1);
-}
-
-static inline struct device_d *zynq_add_eth0(struct macb_platform_data *pdata)
-{
-	return zynq_add_eth((resource_size_t)ZYNQ_GEM0_BASE_ADDR, 0, pdata);
-}

index ec22b16c91cd..ad06c624d90b 100644
@@ -48,10 +48,6 @@ static int zynq_init(void)
 	writel(val, 0xf8f00000);
 	dmb();
 
-	add_generic_device("zynq-clock", 0, NULL, ZYNQ_SLCR_BASE + 0x100,
-			   0x4000, IORESOURCE_MEM, NULL);
-	add_generic_device("smp_twd", 0, NULL, CORTEXA9_SCU_TIMER_BASE_ADDR,
-				0x4000, IORESOURCE_MEM, NULL);
 	restart_handler_register_fn(zynq_restart_soc);
 
 	return 0;

index 2a855d286fcd..5418adee37ad 100644
@@ -455,15 +455,6 @@ static int zynq_clock_probe(struct device_d *dev)
 	clks[smc_aper] = clk_gate("smc_aper", "cpu_1x",
 				  clk_base + 0x2C, 24, 0, 0);
 
-	clk_register_clkdev(clks[cpu_3or2x], NULL, "arm_smp_twd");
-	clk_register_clkdev(clks[uart0], NULL, "zynq_serial0");
-	clk_register_clkdev(clks[uart1], NULL, "zynq_serial1");
-	clk_register_clkdev(clks[gem0], NULL, "macb0");
-	clk_register_clkdev(clks[gem1], NULL, "macb1");
-
-	clkdev_add_physbase(clks[cpu_3or2x], CORTEXA9_SCU_TIMER_BASE_ADDR, NULL);
-	clkdev_add_physbase(clks[uart1], ZYNQ_UART1_BASE_ADDR, NULL);
-
 	clk_data.clks = clks;
 	clk_data.clk_num = ARRAY_SIZE(clks);
 	of_clk_add_provider(dev->device_node, of_clk_src_onecell_get,

index ae279e4e64af..93e4da96ecd4 100644
@@ -29,7 +29,7 @@
 
 extern char __dtb_zynq_zed_start[];
 
-void __naked barebox_arm_reset_vector(uint32_t r0, uint32_t r1, uint32_t r2)
+ENTRY_FUNCTION(start_avnet_zedboard, r0, r1, r2)
 {
 
 	void *fdt = __dtb_zynq_zed_start + get_runtime_offset();

index 4ef8d8ad9585..1f2bf87e99ed 100644
@@ -37,6 +37,7 @@ static const char *bootsource_str[] = {
 	[BOOTSOURCE_USB] = "usb",
 	[BOOTSOURCE_NET] = "net",
 	[BOOTSOURCE_CAN] = "can",
+	[BOOTSOURCE_JTAG] = "jtag",
 };
 
 static enum bootsource bootsource = BOOTSOURCE_UNKNOWN;

index 29347aaeb042..92f7f27cd4fa 100644
@@ -17,6 +17,7 @@ enum bootsource {
 	BOOTSOURCE_USB,
 	BOOTSOURCE_NET,
 	BOOTSOURCE_CAN,
+	BOOTSOURCE_JTAG,
 };
 
 #define BOOTSOURCE_INSTANCE_UNKNOWN	-1

index dd02f5b4072a..eeecfe1ded43 100644
@@ -63,6 +63,7 @@
 #define ZYNQ_FPGA3_CLK_CTRL		0x0A0
 #define ZYNQ_CLK_621_TRUE		0x0C4
 #define ZYNQ_RST_CTRL_BASE		(ZYNQ_SLCR_BASE + 0x200)
+#define ZYNQ_SLCR_BOOT_MODE		(ZYNQ_SLCR_BASE + 0x25C)
 #define ZYNQ_PSS_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x000)
 #define ZYNQ_DDR_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x004)
 #define ZYNQ_TOPSW_RST_CTRL		(ZYNQ_RST_CTRL_BASE + 0x008)

index ad06c624d90b..79a6b908e000 100644
@@ -14,11 +14,12 @@
  */
 
 #include <asm/system.h>
-#include <io.h>
+#include <bootsource.h>
 #include <common.h>
 #include <init.h>
-#include <restart.h>
+#include <io.h>
 #include <mach/zynq7000-regs.h>
+#include <restart.h>
 
 static void __noreturn zynq_restart_soc(struct restart_handler *rst)
 {

@@ -30,6 +31,26 @@ static void __noreturn zynq_restart_soc(struct restart_handler *rst)
 	hang();
 }
 
+static enum bootsource zynq_bootsource_get(void)
+{
+	u32 boot_mode = readl(ZYNQ_SLCR_BOOT_MODE);
+
+	switch (boot_mode & 0x7) {
+	case 0x0:
+		return BOOTSOURCE_JTAG;
+	case 0x1:
+		return BOOTSOURCE_SPI;
+	case 0x2:
+		return BOOTSOURCE_NOR;
+	case 0x4:
+		return BOOTSOURCE_NAND;
+	case 0x5:
+		return BOOTSOURCE_MMC;
+	default:
+		return BOOTSOURCE_UNKNOWN;
+	}
+}
+
 static int zynq_init(void)
 {
 	u32 val;

@@ -50,6 +71,8 @@ static int zynq_init(void)
 
 	restart_handler_register_fn(zynq_restart_soc);
 
+	bootsource_set(zynq_bootsource_get());
+
 	return 0;
 }
 postcore_initcall(zynq_init);