dt-bindings: PCI: Convert Arm Versatile binding to DT schema

Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema.

Cc Bjorn Helgaas <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Andrew Murray <[email protected]>

Cc Zhou Wang <[email protected]>

Cc Will Deacon <[email protected]>

Cc David Daney <[email protected]>

Signed-off-by Rob Herring <[email protected]>

index 515b2f9542e5..000000000000

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -5

 
-Example:
-
-    pcie1: pcie@7f000000 {
-        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
-        device_type = "pci";

Hi Rob,

Quoted 27 lines · Rob Herring

Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema.

Cc Bjorn Helgaas <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Andrew Murray <[email protected]>

Cc Zhou Wang <[email protected]>

Cc Will Deacon <[email protected]>

Cc David Daney <[email protected]>

Signed-off-by Rob Herring <[email protected]>

index 515b2f9542e5..000000000000

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -10

 
-Example:
-
-    pcie1: pcie@7f000000 {
-        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
-        device_type = "pci";
-        reg = <0x0 0x7f000000 0x0 0xf00000>;
-        bus-range = <0x0 0xe>;
-        #address-cells = <3>;
-        #size-cells = <2>;
-        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt line 38

Quoted 5 lines

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -5

-                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
-                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
-
-        #interrupt-cells = <0x1>;
-        interrupt-map-mask = <0x0 0x0 0x0 0x0>;

An all-zeroes interrupt-map-mask seems to be very common on embedded SoCs, where all devices are mapped to a single interrupt.

However, schemas/pci/pci-bus.yaml says:

interrupt-map-mask:
items:
- description: PCI high address cell
minimum: 0
maximum: 0xf800
- description: PCI mid address cell
const: 0
- description: PCI low address cell
const: 0
- description: PCI IRQ cell
minimum: 1
maximum: 7

and thus complains about an all-zeroes mask, e.g.

    arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:

pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1

Quoted 28 lines · Geert Uytterhoeven

Quoted 27 lines · Rob Herring

Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema.

Cc Bjorn Helgaas <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Andrew Murray <[email protected]>

Cc Zhou Wang <[email protected]>

Cc Will Deacon <[email protected]>

Cc David Daney <[email protected]>

Signed-off-by Rob Herring <[email protected]>

index 515b2f9542e5..000000000000

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -10

 
-Example:
-
-    pcie1: pcie@7f000000 {
-        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
-        device_type = "pci";
-        reg = <0x0 0x7f000000 0x0 0xf00000>;
-        bus-range = <0x0 0xe>;
-        #address-cells = <3>;
-        #size-cells = <2>;
-        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,

Quoted 8 lines

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt line 38

Quoted 5 lines

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -5

-                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
-                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
-
-        #interrupt-cells = <0x1>;
-        interrupt-map-mask = <0x0 0x0 0x0 0x0>;

An all-zeroes interrupt-map-mask seems to be very common on embedded SoCs, where all devices are mapped to a single interrupt.

Indeed.

Quoted 15 lines

However, schemas/pci/pci-bus.yaml says:

interrupt-map-mask:
items:
- description: PCI high address cell
minimum: 0
maximum: 0xf800
- description: PCI mid address cell
const: 0
- description: PCI low address cell
const: 0
- description: PCI IRQ cell
minimum: 1
maximum: 7

Quoted 4 lines

and thus complains about an all-zeroes mask, e.g.

    arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:

pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1

Now fixed.

Quoted 55 lines · Rob Herring

Quoted 28 lines · Geert Uytterhoeven

Quoted 27 lines · Rob Herring

Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema.

Cc Bjorn Helgaas <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Andrew Murray <[email protected]>

Cc Zhou Wang <[email protected]>

Cc Will Deacon <[email protected]>

Cc David Daney <[email protected]>

Signed-off-by Rob Herring <[email protected]>

index 515b2f9542e5..000000000000

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -10

 
-Example:
-
-    pcie1: pcie@7f000000 {
-        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
-        device_type = "pci";
-        reg = <0x0 0x7f000000 0x0 0xf00000>;
-        bus-range = <0x0 0xe>;
-        #address-cells = <3>;
-        #size-cells = <2>;
-        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,

Quoted 8 lines

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt line 38

Quoted 5 lines

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -5

-                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
-                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
-
-        #interrupt-cells = <0x1>;
-        interrupt-map-mask = <0x0 0x0 0x0 0x0>;

An all-zeroes interrupt-map-mask seems to be very common on embedded SoCs, where all devices are mapped to a single interrupt.

Indeed.

Quoted 15 lines

However, schemas/pci/pci-bus.yaml says:

interrupt-map-mask:
items:
- description: PCI high address cell
minimum: 0
maximum: 0xf800
- description: PCI mid address cell
const: 0
- description: PCI low address cell
const: 0
- description: PCI IRQ cell
minimum: 1
maximum: 7

Quoted 6 lines

Quoted 4 lines

and thus complains about an all-zeroes mask, e.g.

    arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:

pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1

Now fixed.

Thank you, confirmed.

Hi Rob,

Quoted 56 lines · Geert Uytterhoeven

Quoted 55 lines · Rob Herring

Quoted 28 lines · Geert Uytterhoeven

Quoted 27 lines · Rob Herring

Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema.

Cc Bjorn Helgaas <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Andrew Murray <[email protected]>

Cc Zhou Wang <[email protected]>

Cc Will Deacon <[email protected]>

Cc David Daney <[email protected]>

Signed-off-by Rob Herring <[email protected]>

index 515b2f9542e5..000000000000

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -10

 
-Example:
-
-    pcie1: pcie@7f000000 {
-        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
-        device_type = "pci";
-        reg = <0x0 0x7f000000 0x0 0xf00000>;
-        bus-range = <0x0 0xe>;
-        #address-cells = <3>;
-        #size-cells = <2>;
-        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,

Quoted 8 lines

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt line 38

Quoted 5 lines

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -5

-                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
-                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
-
-        #interrupt-cells = <0x1>;
-        interrupt-map-mask = <0x0 0x0 0x0 0x0>;

An all-zeroes interrupt-map-mask seems to be very common on embedded SoCs, where all devices are mapped to a single interrupt.

Indeed.

Quoted 15 lines

However, schemas/pci/pci-bus.yaml says:

interrupt-map-mask:
items:
- description: PCI high address cell
minimum: 0
maximum: 0xf800
- description: PCI mid address cell
const: 0
- description: PCI low address cell
const: 0
- description: PCI IRQ cell
minimum: 1
maximum: 7

Quoted 8 lines

Quoted 6 lines

Quoted 4 lines

and thus complains about an all-zeroes mask, e.g.

    arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:

pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1

Now fixed.

Thank you, confirmed.

And with latest renesas-drivers, I started seeing:

    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:0: [0, 0, 0, 1] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:1: [5, 0, 113, 4] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:2: [2048, 0, 0, 1] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:3: [5, 0, 113, 4] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:4: [4096, 0, 0, 2] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:

interrupt-map:5: [5, 0, 113, 4] is too short

Looks like interrupt-map is split incorrectly: shouldn't each entry have 8 cells?

Quoted 81 lines · Geert Uytterhoeven

Quoted 56 lines · Geert Uytterhoeven

Quoted 55 lines · Rob Herring

Quoted 28 lines · Geert Uytterhoeven

Quoted 27 lines · Rob Herring

Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema.

Cc Bjorn Helgaas <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Andrew Murray <[email protected]>

Cc Zhou Wang <[email protected]>

Cc Will Deacon <[email protected]>

Cc David Daney <[email protected]>

Signed-off-by Rob Herring <[email protected]>

index 515b2f9542e5..000000000000

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -10

 
-Example:
-
-    pcie1: pcie@7f000000 {
-        compatible = "socionext,synquacer-pcie-ecam", "snps,dw-pcie-ecam";
-        device_type = "pci";
-        reg = <0x0 0x7f000000 0x0 0xf00000>;
-        bus-range = <0x0 0xe>;
-        #address-cells = <3>;
-        #size-cells = <2>;
-        ranges = <0x1000000 0x00 0x00010000 0x00 0x7ff00000 0x0 0x00010000>,

Quoted 8 lines

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt line 38

Quoted 5 lines

Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt deleted +0 -5

-                 <0x2000000 0x00 0x70000000 0x00 0x70000000 0x0 0x0f000000>,
-                 <0x3000000 0x3f 0x00000000 0x3f 0x00000000 0x1 0x00000000>;
-
-        #interrupt-cells = <0x1>;
-        interrupt-map-mask = <0x0 0x0 0x0 0x0>;

An all-zeroes interrupt-map-mask seems to be very common on embedded SoCs, where all devices are mapped to a single interrupt.

Indeed.

Quoted 15 lines

However, schemas/pci/pci-bus.yaml says:

interrupt-map-mask:
items:
- description: PCI high address cell
minimum: 0
maximum: 0xf800
- description: PCI mid address cell
const: 0
- description: PCI low address cell
const: 0
- description: PCI IRQ cell
minimum: 1
maximum: 7

Quoted 8 lines

Quoted 6 lines

Quoted 4 lines

and thus complains about an all-zeroes mask, e.g.

    arch/arm64/boot/dts/renesas/r8a7795-salvator-x.dt.yaml:

pcie@fe000000: interrupt-map-mask:0:3: 0 is less than the minimum of 1

Now fixed.

Thank you, confirmed.

And with latest renesas-drivers, I started seeing:

    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:0: [0, 0, 0, 1] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:1: [5, 0, 113, 4] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:2: [2048, 0, 0, 1] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:3: [5, 0, 113, 4] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:
interrupt-map:4: [4096, 0, 0, 2] is too short
    arch/arm/boot/dts/r8a7791-koelsch.dt.yaml: pci@ee0d0000:

interrupt-map:5: [5, 0, 113, 4] is too short

Quoted 2 lines

Looks like interrupt-map is split incorrectly: shouldn't each entry have 8 cells?

That must be with a current dtc which now splits the array before each phandle. That works for phandle+args, but not *-map properties. :( I

was trying to avoid a bunch of dts updates to add brackets. I think for now, I'll just drop the interrupt-map size constraint. It's not all that accurate anyways as it doesn't look at cell sizes.

Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema.

Cc Bjorn Helgaas <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Andrew Murray <[email protected]>

Cc Zhou Wang <[email protected]>

Cc Will Deacon <[email protected]>

Cc David Daney <[email protected]>

Signed-off-by Rob Herring <[email protected]>

---
 .../bindings/pci/arm,juno-r1-pcie.txt         |  10 --
 .../bindings/pci/designware-pcie-ecam.txt     |  42 -----
 .../bindings/pci/hisilicon-pcie.txt           |   4 +-
 .../bindings/pci/host-generic-pci.txt         | 101 ------------
 .../bindings/pci/host-generic-pci.yaml        | 150 ++++++++++++++++++
 .../bindings/pci/pci-thunder-ecam.txt         |  30 ----
 .../bindings/pci/pci-thunder-pem.txt          |   7 +-
 .../bindings/pci/plda,xpressrich3-axi.txt     |  12 --
 MAINTAINERS                                   |   2 +-
 9 files changed, 155 insertions(+), 203 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.txt
 create mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt

Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file +35 -0

+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    description: Depends on the layout of configuration space (CAM vs ECAM
+      respectively). May also have more specific compatibles.
+    anyOf:
+      - description:
+          PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
+        items:
+          - const: arm,juno-r1-pcie
+          - const: plda,xpressrich3-axi
+          - const: pci-host-ecam-generic
+      - description: |
+          ThunderX PCI host controller for pass-1.x silicon
+
+          Firmware-initialized PCI host controller to on-chip devices found on
+          some Cavium ThunderX processors.  These devices have ECAM-based config
+          access, but the BARs are all at fixed addresses.  We handle the fixed
+          addresses by synthesizing Enhanced Allocation (EA) capabilities for
+          these devices.
+        const: cavium,pci-host-thunder-ecam
+      - description: |
+          In some cases, firmware may already have configured the Synopsys
+          DesignWare PCIe controller in RC mode with static ATU window mappings
+          that cover all config, MMIO and I/O spaces in a [mostly] ECAM
+          compatible fashion. In this case, there is no need for the OS to
+          perform any low level setup of clocks, PHYs or device registers, nor
+          is there any reason for the driver to reconfigure ATU windows for
+          config and/or IO space accesses at runtime.
+
+          In cases where the IP was synthesized with a minimum ATU window size
+          of 64 KB, it cannot be supported by the generic ECAM driver, because
+          it requires special config space accessors that filter accesses to

Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file +9 -0

+  reg:
+    description:
+      The Configuration Space base address and size, as accessed from the parent
+      bus. The base address corresponds to the first bus in the "bus-range"
+      property. If no "bus-range" is specified, this will be bus 0 (the
+      default).
+    maxItems: 1
+
+  ranges:

Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file +13 -0

+required:
+  - compatible
+  - reg
+  - ranges
+
+if:
+  properties:
+    compatible:
+      contains:
+        const: arm,juno-r1-pcie
+then:
+  required:
+    - dma-coherent

Quoted 29 lines · Rob Herring

Convert the generic PCI host binding to DT schema. The derivative Juno, PLDA XpressRICH3-AXI, and Designware ECAM bindings all just vary in their compatible strings. The simplest way to convert those to schema is just add them into the common generic PCI host schema.

Cc Bjorn Helgaas <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Andrew Murray <[email protected]>

Cc Zhou Wang <[email protected]>

Cc Will Deacon <[email protected]>

Cc David Daney <[email protected]>

Signed-off-by Rob Herring <[email protected]>

---
 .../bindings/pci/arm,juno-r1-pcie.txt         |  10 --
 .../bindings/pci/designware-pcie-ecam.txt     |  42 -----
 .../bindings/pci/hisilicon-pcie.txt           |   4 +-
 .../bindings/pci/host-generic-pci.txt         | 101 ------------
 .../bindings/pci/host-generic-pci.yaml        | 150 ++++++++++++++++++
 .../bindings/pci/pci-thunder-ecam.txt         |  30 ----
 .../bindings/pci/pci-thunder-pem.txt          |   7 +-
 .../bindings/pci/plda,xpressrich3-axi.txt     |  12 --
 MAINTAINERS                                   |   2 +-
 9 files changed, 155 insertions(+), 203 deletions(-)
 delete mode 100644 Documentation/devicetree/bindings/pci/arm,juno-r1-pcie.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/designware-pcie-ecam.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.txt
 create mode 100644 Documentation/devicetree/bindings/pci/host-generic-pci.yaml
 delete mode 100644 Documentation/devicetree/bindings/pci/pci-thunder-ecam.txt
 delete mode 100644 Documentation/devicetree/bindings/pci/plda,xpressrich3-axi.txt

Documentation/devicetree/bindings/pci/host-generic-pci.yaml line 37

Quoted 6 lines

Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file +2 -0

...
 
+  Interrupt mapping is exactly as described in `Open Firmware Recommended
+

I think there's some text missing here.

Quoted 40 lines

Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file +40 -0

+allOf:
+  - $ref: /schemas/pci/pci-bus.yaml#
+
+properties:
+  compatible:
+    description: Depends on the layout of configuration space (CAM vs ECAM
+      respectively). May also have more specific compatibles.
+    anyOf:
+      - description:
+          PCIe host controller in Arm Juno based on PLDA XpressRICH3-AXI IP
+        items:
+          - const: arm,juno-r1-pcie
+          - const: plda,xpressrich3-axi
+          - const: pci-host-ecam-generic
+      - description: |
+          ThunderX PCI host controller for pass-1.x silicon
+
+          Firmware-initialized PCI host controller to on-chip devices found on
+          some Cavium ThunderX processors.  These devices have ECAM-based config
+          access, but the BARs are all at fixed addresses.  We handle the fixed
+          addresses by synthesizing Enhanced Allocation (EA) capabilities for
+          these devices.
+        const: cavium,pci-host-thunder-ecam
+      - description: |
+          In some cases, firmware may already have configured the Synopsys
+          DesignWare PCIe controller in RC mode with static ATU window mappings
+          that cover all config, MMIO and I/O spaces in a [mostly] ECAM
+          compatible fashion. In this case, there is no need for the OS to
+          perform any low level setup of clocks, PHYs or device registers, nor
+          is there any reason for the driver to reconfigure ATU windows for
+          config and/or IO space accesses at runtime.
+
+          In cases where the IP was synthesized with a minimum ATU window size
+          of 64 KB, it cannot be supported by the generic ECAM driver, because
+          it requires special config space accessors that filter accesses to
+          device #1 and beyond on the first bus.
+        items:
+          - enum:
+              - marvell,armada8k-pcie-ecam
+              - socionext,synquacer-pcie-ecam

Documentation/devicetree/bindings/pci/host-generic-pci.yaml line 82

Quoted 5 lines

Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file +5 -0

+          - const: snps,dw-pcie-ecam
+      - contains:
+          enum:
+            - pci-host-cam-generic
+            - pci-host-ecam-generic

I assume the description that talks about "Synopsys DesignWare" goes with "pci-host-cam-generic" and "pci-host-ecam-generic"?

I hope there
can be generic controllers using non-Synopsys IP, but I don't know quite how the description/items/contains parts are related.

Quoted 16 lines

Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file +15 -0

+  reg:
+    description:
+      The Configuration Space base address and size, as accessed from the parent
+      bus. The base address corresponds to the first bus in the "bus-range"
+      property. If no "bus-range" is specified, this will be bus 0 (the
+      default).
+    maxItems: 1
+
+  ranges:
+    description:
+      As described in IEEE Std 1275-1994, but must provide at least a
+      definition of non-prefetchable memory. One or both of prefetchable Memory
+      and IO Space may also be provided.
+    minItems: 1
+    maxItems: 3

Documentation/devicetree/bindings/pci/host-generic-pci.yaml line 102

Quoted 4 lines

Documentation/devicetree/bindings/pci/host-generic-pci.yaml new file +4 -0

+
+  dma-coherent:
+    description: The host controller bridges the AXI transactions into PCIe bus
+      in a manner that makes the DMA operations to appear coherent to the CPUs.

The "host-generic-pci.yaml" name sounds very generic, so I'm not quite sure how to read "AXI" -- that sounds like a feature of a specific platform? I think "dma-coherent" itself is not platform-specific.

Convert the Arm Versatile PCI host binding to a DT schema.

Cc Linus Walleij <[email protected]>

Cc Bjorn Helgaas <[email protected]>

Cc Lorenzo Pieralisi <[email protected]>

Cc Andrew Murray <[email protected]>

Signed-off-by Rob Herring <[email protected]>