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dt: amd-seattle: update SMMU, PCIe and cache descriptions

PATCH In review Ard Biesheuvel 2 participants 10 messages Dec 3, 2019 – Jan 28, 2020

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Ard Biesheuvel

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#0 lore raw

v3 cover dt: amd-seattle: update SMMU, PCIe and cache descriptions

Bring the DT descriptions for AMD Seattle up to date:
- upgrade the existing SMMU descriptions to the new binding, and add the missing descriptions of the PCIe and SATA SMMUs
- fix the description of the PCIe legacy interrupt routing
- remove the obsolete A0 Overdrive and Husky

Changes since v2:
- use Cortex-A57 specific compatible strings for CPUs and PMU
- use iommu@... not smmu@.... for SMMU DT node identifiers
- match the entire range of stream IDs 0x0..0x1f for the first SATA port, for compatibility with some B0 silicon revision based boards

Changes since v1:
- add missing dma-coherent properties to xgbe SMMU nodes
- add patch to disable GPIO and IPMI blocks on B0 silicon
- add patch to include DT descriptions of the CPU and cache topologies

Cc Brijesh Singh <[email protected]>
Cc Suravee Suthikulpanit <[email protected]>
Cc Tom Lendacky <[email protected]>
Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>

Ard Biesheuvel (8):
dt: amd-seattle: remove Husky platform
dt: amd-seattle: remove Overdrive revision A0 support
dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding
dt: amd-seattle: fix PCIe legacy interrupt routing
dt: amd-seattle: add a description of the PCIe SMMU
dt: amd-seattle: add description of the SATA/CCP SMMUs
dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0
dt: amd-seattle: add a description of the CPUs and caches

 arch/arm64/boot/dts/amd/Makefile              |   4 +-
 .../boot/dts/amd/amd-overdrive-rev-b0.dts     |  13 +-
 .../boot/dts/amd/amd-overdrive-rev-b1.dts     |   1 +
 arch/arm64/boot/dts/amd/amd-overdrive.dts     |  66 ------
 arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 224 ++++++++++++++++++
 arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi  |  70 ++++--
 .../boot/dts/amd/amd-seattle-xgbe-b.dtsi      |  22 +-
 arch/arm64/boot/dts/amd/husky.dts             |  84 -------
 8 files changed, 287 insertions(+), 197 deletions(-)
 delete mode 100644 arch/arm64/boot/dts/amd/amd-overdrive.dts
 create mode 100644 arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
 delete mode 100644 arch/arm64/boot/dts/amd/husky.dts
Signature · 1 line
2.17.1
author
#1 lore raw

PATCH v3 1/8 dt: amd-seattle: remove Husky platform

The Huskyboard never made it to production, and its successor the Celloboard was only shipped in very limited quantities with ACPI only firmware, so the historical significance of husky.dts is highly questionable. Let's drop it.

Signed-off-by Ard Biesheuvel <[email protected]>
---
 arch/arm64/boot/dts/amd/Makefile  |  3 +-
 arch/arm64/boot/dts/amd/husky.dts | 84 --------------------
 2 files changed, 1 insertion(+), 86 deletions(-)
arch/arm64/boot/dts/amd/Makefile +1 -2
index 6a6093064a32..5e27bc0321e9 100644
@@ -1,4 +1,3 @@
 # SPDX-License-Identifier: GPL-2.0
 dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb \
-			amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb \
-			husky.dtb
+			amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
arch/arm64/boot/dts/amd/husky.dts deleted +0 -84

84 lines not on this page · raw message

Signature · 1 line
2.17.1
author
#2 lore raw

PATCH v3 2/8 dt: amd-seattle: remove Overdrive revision A0 support

In reply to Ard Biesheuvel

Support for AMD Seattle silicon revision A0 is no longer relevant, since we no longer have a driver for the network controller, and the PCIe on these boards was very unreliable. So drop the DTS description of the A0 version of the overdrive board.

Signed-off-by Ard Biesheuvel <[email protected]>
---
 arch/arm64/boot/dts/amd/Makefile          |  3 +-
 arch/arm64/boot/dts/amd/amd-overdrive.dts | 66 --------------------
 2 files changed, 1 insertion(+), 68 deletions(-)
arch/arm64/boot/dts/amd/Makefile +1 -2
index 5e27bc0321e9..68103a8b0ef5 100644
@@ -1,3 +1,2 @@
 # SPDX-License-Identifier: GPL-2.0
-dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive.dtb \
-			amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
+dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
arch/arm64/boot/dts/amd/amd-overdrive.dts deleted +0 -66

66 lines not on this page · raw message

Signature · 1 line
2.17.1
author
#3 lore raw

PATCH v3 3/8 dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding

In reply to Ard Biesheuvel

Upgrade the DT descriptions of the AMD Seattle XGBE network controllers to use the current SMMU bindings.

Signed-off-by Ard Biesheuvel <[email protected]>
---
 arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi | 22 +++++++-------------
 1 file changed, 8 insertions(+), 14 deletions(-)
arch/arm64/boot/dts/amd/amd-seattle-xgbe-b.dtsi +8 -14
index d97498361ce3..9259e547e2e8 100644
@@ -55,7 +55,7 @@
 		clocks = <&xgmacclk0_dma_250mhz>, <&xgmacclk0_ptp_250mhz>;
 		clock-names = "dma_clk", "ptp_clk";
 		phy-mode = "xgmii";
-		#stream-id-cells = <16>;
+		iommus = <&xgmac0_smmu 0x00 0x17>; /* 0-7, 16-23 */
 		dma-coherent;
 	};
 

@@ -81,11 +81,11 @@
 		clocks = <&xgmacclk1_dma_250mhz>, <&xgmacclk1_ptp_250mhz>;
 		clock-names = "dma_clk", "ptp_clk";
 		phy-mode = "xgmii";
-		#stream-id-cells = <16>;
+		iommus = <&xgmac1_smmu 0x00 0x17>; /* 0-7, 16-23 */
 		dma-coherent;
 	};
 
-	xgmac0_smmu: smmu@e0600000 {
+	xgmac0_smmu: iommu@e0600000 {
 		 compatible = "arm,mmu-401";
 		 reg = <0 0xe0600000 0 0x10000>;
 		 #global-interrupts = <1>;

@@ -94,14 +94,11 @@
 			       */
 			      <0 336 4>,
 			      <0 336 4>;
-
-		 mmu-masters = <&xgmac0
-			  0  1  2  3  4  5  6  7
-			 16 17 18 19 20 21 22 23
-		 >;
+		#iommu-cells = <2>;
+		dma-coherent;
 	 };
 
-	 xgmac1_smmu: smmu@e0800000 {
+	 xgmac1_smmu: iommu@e0800000 {
 		 compatible = "arm,mmu-401";
 		 reg = <0 0xe0800000 0 0x10000>;
 		 #global-interrupts = <1>;

@@ -110,9 +107,6 @@
 			       */
 			      <0 335 4>,
 			      <0 335 4>;
-
-		 mmu-masters = <&xgmac1
-			  0  1  2  3  4  5  6  7
-			 16 17 18 19 20 21 22 23
-		 >;
+		#iommu-cells = <2>;
+		dma-coherent;
 	 };
Signature · 1 line
2.17.1
author
#4 lore raw

PATCH v3 4/8 dt: amd-seattle: fix PCIe legacy interrupt routing

In reply to Ard Biesheuvel

The AMD Seattle SOC can be configured to expose up to 3 PCIe root ports, each of which is wired to 4 dedicated SPI wired interrupts for legacy INTx support. Update the SOC DT description to reflect this.

Fix a stale comment about the size of the MMIO64 resource window while at it.

Signed-off-by Ard Biesheuvel <[email protected]>
---
 arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 22 ++++++++++++++------
 1 file changed, 16 insertions(+), 6 deletions(-)
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +16 -6
index b664e7af74eb..9fa6890fca35 100644
@@ -213,12 +213,22 @@
 			msi-parent = <&v2m0>;
 			reg = <0 0xf0000000 0 0x10000000>;
 
-			interrupt-map-mask = <0xf800 0x0 0x0 0x7>;
+			interrupt-map-mask = <0xff00 0x0 0x0 0x7>;
 			interrupt-map =
-				<0x1000 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
-				<0x1000 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
-				<0x1000 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
-				<0x1000 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>;
+				<0x1100 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x120 0x1>,
+				<0x1100 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x121 0x1>,
+				<0x1100 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x122 0x1>,
+				<0x1100 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x123 0x1>,
+
+				<0x1200 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x124 0x1>,
+				<0x1200 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x125 0x1>,
+				<0x1200 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x126 0x1>,
+				<0x1200 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x127 0x1>,
+
+				<0x1300 0x0 0x0 0x1 &gic0 0x0 0x0 0x0 0x128 0x1>,
+				<0x1300 0x0 0x0 0x2 &gic0 0x0 0x0 0x0 0x129 0x1>,
+				<0x1300 0x0 0x0 0x3 &gic0 0x0 0x0 0x0 0x12a 0x1>,
+				<0x1300 0x0 0x0 0x4 &gic0 0x0 0x0 0x0 0x12b 0x1>;
 
 			dma-coherent;
 			dma-ranges = <0x43000000 0x0 0x0 0x0 0x0 0x100 0x0>;

@@ -227,7 +237,7 @@
 				<0x01000000 0x00 0x00000000 0x00 0xefff0000 0x00 0x00010000>,
 				/* 32-bit MMIO (size=2G) */
 				<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
-				/* 64-bit MMIO (size= 124G) */
+				/* 64-bit MMIO (size= 508G) */
 				<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
 		};
Signature · 1 line
2.17.1
author
#5 lore raw

PATCH v3 5/8 dt: amd-seattle: add a description of the PCIe SMMU

In reply to Ard Biesheuvel

Add a description of the SMMU that covers the PCIe host bridge on AMD Seattle.

Signed-off-by Ard Biesheuvel <[email protected]>
---
 arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 10 ++++++++++
 1 file changed, 10 insertions(+)
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +10 -0
index 9fa6890fca35..124e58a76be0 100644
@@ -239,6 +239,16 @@
 				<0x02000000 0x00 0x40000000 0x00 0x40000000 0x00 0x80000000>,
 				/* 64-bit MMIO (size= 508G) */
 				<0x03000000 0x01 0x00000000 0x01 0x00000000 0x7f 0x00000000>;
+			iommu-map = <0x0 &pcie_smmu 0x0 0x10000>;
+		};
+
+		pcie_smmu: iommu@e0a00000 {
+			compatible = "arm,mmu-401";
+			reg = <0 0xe0a00000 0 0x10000>;
+			#global-interrupts = <1>;
+			interrupts = <0 333 4>, <0 333 4>;
+			#iommu-cells = <1>;
+			dma-coherent;
 		};
 
 		/* Perf CCN504 PMU */
Signature · 1 line
2.17.1
author
#6 lore raw

PATCH v3 6/8 dt: amd-seattle: add description of the SATA/CCP SMMUs

In reply to Ard Biesheuvel

Add descriptions of the SMMUs that cover the SATA controller(s) on the AMD Seattle SOC. The CCP crypto accelerator shares its SMMU with the second SATA controller, which is only enabled on B1 silicon.

Signed-off-by Ard Biesheuvel <[email protected]>
---
 arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi | 26 ++++++++++++++++++++
 1 file changed, 26 insertions(+)
arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +26 -0
index 124e58a76be0..547a6bf10f5e 100644
@@ -70,6 +70,7 @@
 			reg = <0 0xe0300000 0 0xf0000>;
 			interrupts = <0 355 4>;
 			clocks = <&sataclk_333mhz>;
+			iommus = <&sata0_smmu 0x0 0x1f>;
 			dma-coherent;
 		};
 

@@ -80,6 +81,27 @@
 			reg = <0 0xe0d00000 0 0xf0000>;
 			interrupts = <0 354 4>;
 			clocks = <&sataclk_333mhz>;
+			iommus = <&sata1_smmu 0x0e>,
+				 <&sata1_smmu 0x0f>,
+				 <&sata1_smmu 0x1e>;
+			dma-coherent;
+		};
+
+		sata0_smmu: iommu@e0200000 {
+			compatible = "arm,mmu-401";
+			reg = <0 0xe0200000 0 0x10000>;
+			#global-interrupts = <1>;
+			interrupts = <0 332 4>, <0 332 4>;
+			#iommu-cells = <2>;
+			dma-coherent;
+		};
+
+		sata1_smmu: iommu@e0c00000 {
+			compatible = "arm,mmu-401";
+			reg = <0 0xe0c00000 0 0x10000>;
+			#global-interrupts = <1>;
+			interrupts = <0 331 4>, <0 331 4>;
+			#iommu-cells = <1>;
 			dma-coherent;
 		};
 

@@ -201,6 +223,10 @@
 			reg = <0 0xe0100000 0 0x10000>;
 			interrupts = <0 3 4>;
 			dma-coherent;
+			iommus = <&sata1_smmu 0x00>,
+				 <&sata1_smmu 0x02>,
+				 <&sata1_smmu 0x40>,
+				 <&sata1_smmu 0x42>;
 		};
 
 		pcie0: pcie@f0000000 {
Signature · 1 line
2.17.1
author
#7 lore raw

PATCH v3 7/8 dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0

In reply to Ard Biesheuvel

Disable some peripherals that are not usable on B0 silicon based Overdrives.

Signed-off-by Ard Biesheuvel <[email protected]>
---
 arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts | 12 ------------
 1 file changed, 12 deletions(-)
arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts +0 -12
index 8e341be9a399..4997a74aeb67 100644
@@ -36,14 +36,6 @@
 	status = "ok";
 };
 
-&gpio2 {
-	status = "ok";
-};
-
-&gpio3 {
-	status = "ok";
-};
-
 &gpio4 {
 	status = "ok";
 };

@@ -79,10 +71,6 @@
 	};
 };
 
-&ipmi_kcs {
-	status = "ok";
-};
-
 &smb0 {
 	/include/ "amd-seattle-xgbe-b.dtsi"
 };
Signature · 1 line
2.17.1
author
#8 lore raw

PATCH v3 8/8 dt: amd-seattle: add a description of the CPUs and caches

In reply to Ard Biesheuvel

Add a DT description of the CPU and cache hierarchy as found on the AMD Seattle SOC. Given the tight coupling of the PMU with the CPUs, move the PMU node into the cpu .dtsi file as well, and add the missing affinity description.

Signed-off-by Ard Biesheuvel <[email protected]>
---
 arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts |   1 +
 arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts |   1 +
 arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi    | 224 ++++++++++++++++++++
 arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi     |  12 --
 4 files changed, 226 insertions(+), 12 deletions(-)
arch/arm64/boot/dts/amd/amd-overdrive-rev-b0.dts +1 -0
index 4997a74aeb67..c290d1ce2b03 100644
@@ -9,6 +9,7 @@
 /dts-v1/;
 
 /include/ "amd-seattle-soc.dtsi"
+/include/ "amd-seattle-cpus.dtsi"
 
 / {
 	model = "AMD Seattle (Rev.B0) Development Board (Overdrive)";
arch/arm64/boot/dts/amd/amd-overdrive-rev-b1.dts +1 -0
index 92cef05c6b74..e0926f6bb7c3 100644
@@ -9,6 +9,7 @@
 /dts-v1/;
 
 /include/ "amd-seattle-soc.dtsi"
+/include/ "amd-seattle-cpus.dtsi"
 
 / {
 	model = "AMD Seattle (Rev.B1) Development Board (Overdrive)";
arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi new file +224 -0

224 lines not on this page · raw message

arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi +0 -12
index 547a6bf10f5e..690020589d41 100644
@@ -38,18 +38,6 @@
 			     <1 10 0xff04>;
 	};
 
-	pmu {
-		compatible = "arm,armv8-pmuv3";
-		interrupts = <0 7 4>,
-			     <0 8 4>,
-			     <0 9 4>,
-			     <0 10 4>,
-			     <0 11 4>,
-			     <0 12 4>,
-			     <0 13 4>,
-			     <0 14 4>;
-	};
-
 	smb0: smb {
 		compatible = "simple-bus";
 		#address-cells = <2>;
Signature · 1 line
2.17.1
Tested-by on the v3 series
#9 lore raw
In reply to Ard Biesheuvel

Hi,

Quoted 5 lines · Ard Biesheuvel

Bring the DT descriptions for AMD Seattle up to date:
- upgrade the existing SMMU descriptions to the new binding, and add the missing descriptions of the PCIe and SATA SMMUs
- fix the description of the PCIe legacy interrupt routing
- remove the obsolete A0 Overdrive and Husky

This is long overdue, I've been playing with PCI passthrough on an AMD Seattle machine using these patches since you posted them on the mailing list. With these patches, PCI passthrough has been tested with the following devices: Intel 82574L Gigabit Ethernet card, Samsung 970 Pro NVME, Realtek 8168 Gigabit Ethernet card, NVIDIA Quadro P400, AMD Firepro W2100, Myricom 10 Gigabit Ethernet card and a Seagate Barracuda 1000GB drive with a generic PCIE SATA card.

For patches #3-#6 (that touch the SMMU):

Tested-by Alexandru Elisei <[email protected]>

Thanks,
Alex

Quoted 41 lines

Changes since v2:
- use Cortex-A57 specific compatible strings for CPUs and PMU
- use iommu@... not smmu@.... for SMMU DT node identifiers
- match the entire range of stream IDs 0x0..0x1f for the first SATA port, for compatibility with some B0 silicon revision based boards

Changes since v1:
- add missing dma-coherent properties to xgbe SMMU nodes
- add patch to disable GPIO and IPMI blocks on B0 silicon
- add patch to include DT descriptions of the CPU and cache topologies

Cc Brijesh Singh <[email protected]>
Cc Suravee Suthikulpanit <[email protected]>
Cc Tom Lendacky <[email protected]>
Cc Rob Herring <[email protected]>
Cc Mark Rutland <[email protected]>

Ard Biesheuvel (8):
dt: amd-seattle: remove Husky platform
dt: amd-seattle: remove Overdrive revision A0 support
dt: amd-seattle: upgrade AMD Seattle XGBE to new SMMU binding
dt: amd-seattle: fix PCIe legacy interrupt routing
dt: amd-seattle: add a description of the PCIe SMMU
dt: amd-seattle: add description of the SATA/CCP SMMUs
dt: amd-seattle: disable IPMI controller and some GPIO blocks on B0
dt: amd-seattle: add a description of the CPUs and caches

 arch/arm64/boot/dts/amd/Makefile              |   4 +-
 .../boot/dts/amd/amd-overdrive-rev-b0.dts     |  13 +-
 .../boot/dts/amd/amd-overdrive-rev-b1.dts     |   1 +
 arch/arm64/boot/dts/amd/amd-overdrive.dts     |  66 ------
 arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi | 224 ++++++++++++++++++
 arch/arm64/boot/dts/amd/amd-seattle-soc.dtsi  |  70 ++++--
 .../boot/dts/amd/amd-seattle-xgbe-b.dtsi      |  22 +-
 arch/arm64/boot/dts/amd/husky.dts             |  84 -------
 8 files changed, 287 insertions(+), 197 deletions(-)
 delete mode 100644 arch/arm64/boot/dts/amd/amd-overdrive.dts
 create mode 100644 arch/arm64/boot/dts/amd/amd-seattle-cpus.dtsi
 delete mode 100644 arch/arm64/boot/dts/amd/husky.dts