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clk: zynq: add QSPI reference clock

PATCH Applied Lucas Stach 2 participants 5 messages Dec 18, 2019 – Dec 20, 2019

Subsystems (5)
Arm (32-bit) Common clk SPI Arm/Zynq architecture +1 more subsystems
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Lucas Stach

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#0 lore raw

PATCH 1/4 clk: zynq: add QSPI reference clock

Signed-off-by Lucas Stach <[email protected]>
---
 drivers/clk/zynq/clkc.c | 3 +++
 1 file changed, 3 insertions(+)
drivers/clk/zynq/clkc.c +3 -0
index 30ca5a60faf3..a6d8ba92cabc 100644
@@ -414,6 +414,9 @@ static int zynq_clock_probe(struct device_d *dev)
 	clks[ddrpll] = zynq_pll_clk(ZYNQ_PLL_DDR, "ddr_pll", clk_base + 0x4);
 	clks[iopll] = zynq_pll_clk(ZYNQ_PLL_IO,  "io_pll", clk_base + 0x8);
 
+	zynq_periph_clk("lqspi_clk", clk_base + 0x4c);
+	clks[lqspi] = clk_gate("qspi0", "lqspi_clk", clk_base + 0x4c, 0, 0, 0);
+
 	zynq_periph_clk("sdio_clk", clk_base + 0x50);
 	clks[sdio0] = clk_gate("sdio0", "sdio_clk", clk_base + 0x50, 0, 0, 0);
 	clks[sdio1] = clk_gate("sdio1", "sdio_clk", clk_base + 0x50, 1, 0, 0);
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author
#1 lore raw

PATCH 2/4 spi: add Zynq QSPI controller driver

This adds the driver for the QSPI controller found on the Xilinx Zynq SoCs.

Signed-off-by Lucas Stach <[email protected]>
---
 drivers/spi/Kconfig     |   8 +
 drivers/spi/Makefile    |   1 +
 drivers/spi/zynq_qspi.c | 612 ++++++++++++++++++++++++++++++++++++++++
 3 files changed, 621 insertions(+)
 create mode 100644 drivers/spi/zynq_qspi.c
drivers/spi/Kconfig +8 -0
index 9d4b1cc4e358..3758a0fad943 100644
@@ -88,6 +88,14 @@ config DRIVER_SPI_DSPI
 	  This enables support for the Freescale DSPI controller in master
 	  mode. VF610 platform uses the controller.
 
+config SPI_ZYNQ_QSPI
+	tristate "Xilinx Zynq QSPI controller"
+	depends on ARCH_ZYNQ
+	depends on SPI_MEM
+	help
+	  This enables support for the Zynq Quad SPI controller in master mode.
+	  This controller only supports SPI memory interface.
+
 endif
 
 endmenu
drivers/spi/Makefile +1 -0
index c5d2de74e11c..75a89ef38ee8 100644
@@ -11,3 +11,4 @@ obj-$(CONFIG_DRIVER_SPI_ATMEL) += atmel_spi.o
 obj-$(CONFIG_SPI_ATMEL_QUADSPI) += atmel-quadspi.o
 obj-$(CONFIG_DRIVER_SPI_OMAP3) += omap3_spi.o
 obj-$(CONFIG_DRIVER_SPI_DSPI) += dspi_spi.o
+obj-$(CONFIG_SPI_ZYNQ_QSPI) += zynq_qspi.o
drivers/spi/zynq_qspi.c new file +612 -0

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author
#2 lore raw

PATCH 3/4 ARM: zynq: add QSPI DT node

In reply to Lucas Stach

The node is not available in the upstream DT, yet. Add it to the Barebox DT extensions.

Signed-off-by Lucas Stach <[email protected]>
---
 arch/arm/dts/zynq-7000.dtsi | 15 +++++++++++++++
 1 file changed, 15 insertions(+)
 create mode 100644 arch/arm/dts/zynq-7000.dtsi
arch/arm/dts/zynq-7000.dtsi new file +15 -0
new file mode 100644
index 000000000000..3791f743a47d
@@ -0,0 +1,15 @@
+
+&amba {
+	qspi: spi@e000d000 {
+		compatible = "xlnx,zynq-qspi-1.0";
+		reg = <0xe000d000 0x1000>;
+		interrupt-parent = <&intc>;
+		interrupts = <0 19 4>;
+		clocks = <&clkc 10>, <&clkc 43>;
+		clock-names = "ref_clk", "pclk";
+		status = "disabled";
+		
+		#address-cells = <1>;
+		#size-cells = <0>;
+	};
+};
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author
#3 lore raw

PATCH 4/4 ARM: zynq: zed: add QSPI flash support

In reply to Lucas Stach
Signed-off-by Lucas Stach <[email protected]>
---
 arch/arm/boards/avnet-zedboard/lowlevel.c |  9 +++++++++
 arch/arm/dts/zynq-zed.dts                 | 18 ++++++++++++++++++
 2 files changed, 27 insertions(+)
arch/arm/boards/avnet-zedboard/lowlevel.c +9 -0
index 9b90ef112b46..58f9e40d11c9 100644
@@ -241,9 +241,18 @@ static void avnet_zedboard_ps7_init(void)
 	/* UART1 pinmux */
 	writel(0x000002E1, ZYNQ_MIO_BASE + 0xC8);
 	writel(0x000002E0, ZYNQ_MIO_BASE + 0xCC);
+	/* QSPI pinmux */
+	writel(0x00001602, ZYNQ_MIO_BASE + 0x04);
+	writel(0x00000702, ZYNQ_MIO_BASE + 0x08);
+	writel(0x00000702, ZYNQ_MIO_BASE + 0x0c);
+	writel(0x00000702, ZYNQ_MIO_BASE + 0x10);
+	writel(0x00000702, ZYNQ_MIO_BASE + 0x14);
+	writel(0x00000702, ZYNQ_MIO_BASE + 0x18);
+	writel(0x00000602, ZYNQ_MIO_BASE + 0x20);
 
 	/* poor mans clkctrl */
 	writel(0x00001403, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_UART_CLK_CTRL);
+	writel(0x00000101, ZYNQ_CLOCK_CTRL_BASE + ZYNQ_LQSPI_CLK_CTRL);
 
 	/* GEM0 */
 	writel(0x00000001, 0xf8000138);
arch/arm/dts/zynq-zed.dts +18 -0
index 52d68332499a..a6b1da854bc4 100644
@@ -1,7 +1,25 @@
 #include <arm/zynq-zed.dts>
+#include "zynq-7000.dtsi"
 
 / {
 	chosen {
 		stdout-path = &uart1;
 	};
 };
+
+&qspi {
+	status = "okay";
+	num-cs = <1>;
+
+	qspi_flash: flash@0 {
+		compatible = "spansion,s25fl256s1", "jedec,spi-nor";
+		reg = <0>;
+		spi-tx-bus-width = <1>;
+		spi-rx-bus-width = <4>;
+		spi-max-frequency = <50000000>;
+		m25p,fast-read;
+
+		#address-cells = <1>;
+		#size-cells = <1>;
+	};
+};
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Applied
#4 lore raw
In reply to Lucas Stach
Quoted 4 lines · Lucas Stach
Signed-off-by Lucas Stach <[email protected]>
---
 drivers/clk/zynq/clkc.c | 3 +++
 1 file changed, 3 insertions(+)

Applied, thanks

Sascha

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