phy: ti: j721e-wiz: Add support for DisplayPort mode
Subsystems (2)
cover phy: ti: j721e-wiz: Add support for DisplayPort mode
The wiz wrapper need slightly different configuration when the wrapped serdes is used for DisplayPort. This series adds devicetree properties for selecting the mode for each individual serdes lane separately.
The patch series should apply on top of these series:
https://lkml.org/lkml/2019/10/23/589
https://lkml.org/lkml/2019/10/28/197
Jyri Sarha (3):
dt-bindings: phy: Add PHY_TYPE_DP definition
dt-bindings: phy: Add lane<n>-mode property to WIZ (SERDES wrapper)
phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver
.../bindings/phy/ti,phy-j721e-wiz.yaml | 12 ++++ drivers/phy/ti/phy-j721e-wiz.c | 55 +++++++++++++++++-- include/dt-bindings/phy/phy.h | 1 + 3 files changed, 64 insertions(+), 4 deletions(-)
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Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
PATCH 1/3 dt-bindings: phy: Add PHY_TYPE_DP definition
Add definition for DisplayPort phy type.
--- include/dt-bindings/phy/phy.h | 1 + 1 file changed, 1 insertion(+)
include/dt-bindings/phy/phy.h +1 -0
@@ -16,5 +16,6 @@#define PHY_TYPE_USB2 3#define PHY_TYPE_USB3 4#define PHY_TYPE_UFS 5 +#define PHY_TYPE_DP 6#endif /* _DT_BINDINGS_PHY */
Signature · 1 line
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Re: [PATCH 1/3] dt-bindings: phy: Add PHY_TYPE_DP definition
Quoted 9 lines · Jyri Sarha
Add definition for DisplayPort phy type.
Signed-off-by Jyri Sarha <[email protected]>Reviewed-by Roger Quadros <[email protected]>Reviewed-by Kishon Vijay Abraham I <[email protected]>--- include/dt-bindings/phy/phy.h | 1 + 1 file changed, 1 insertion(+)
PATCH 2/3 dt-bindings: phy: Add lane<n>-mode property to WIZ (SERDES wrapper)
In reply to Jyri SarhaAdd property to indicate the usage of SERDES lane controlled by the WIZ wrapper. The wrapper configuration has some variation depending on how each lane is going to be used.
--- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +12 -0
@@ -97,6 +97,18 @@ patternProperties: Torrent SERDES should follow the bindings specified in Documentation/devicetree/bindings/phy/phy-cadence-dp.txt + "^lane[1-4]-mode$": + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3, 4, 5, 6] + description: | + Integer describing static lane usage for the lane indicated in + the property name. For Sierra there may be properties lane0 and + lane1, for Torrent all lane[1-4]-mode properties may be + there. The constants to indicate the lane usage are defined in + "include/dt-bindings/phy/phy.h". The lane is assumed to be unused + if its lane<n>-use property does not exist. + required: - compatible - power-domains
Signature · 1 line
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Rob Herring
maintainerRe: [PATCH 2/3] dt-bindings: phy: Add lane<n>-mode property to WIZ (SERDES wrapper)
Quoted 18 lines · Jyri Sarha
Add property to indicate the usage of SERDES lane controlled by the WIZ wrapper. The wrapper configuration has some variation depending on how each lane is going to be used.
Signed-off-by Jyri Sarha <[email protected]>--- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +1
-0@@ -97,6 +97,18 @@ patternProperties: Torrent SERDES should follow the bindings specified in Documentation/devicetree/bindings/phy/phy-cadence-dp.txt + "^lane[1-4]-mode$":
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml patternProperties: · line 110
Quoted 10 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +10
-0+ allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3, 4, 5, 6] + description: | + Integer describing static lane usage for the lane indicated in + the property name. For Sierra there may be properties lane0 and + lane1, for Torrent all lane[1-4]-mode properties may be + there. The constants to indicate the lane usage are defined in + "include/dt-bindings/phy/phy.h". The lane is assumed to be unused + if its lane<n>-use property does not exist.
The defines were intended to be in 'phys' cells. Does putting both lane and mode in the client 'phys' properties not work?
Rob
Re: [PATCH 2/3] dt-bindings: phy: Add lane<n>-mode property to WIZ (SERDES wrapper)
Quoted 18 lines · Rob Herring
Quoted 17 lines · Jyri Sarha
Add property to indicate the usage of SERDES lane controlled by the WIZ wrapper. The wrapper configuration has some variation depending on how each lane is going to be used.
Signed-off-by Jyri Sarha <[email protected]>--- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +0
-0@@ -97,6 +97,18 @@ patternProperties: Torrent SERDES should follow the bindings specified in Documentation/devicetree/bindings/phy/phy-cadence-dp.txt
Quoted 15 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml patternProperties: · line 110
Quoted 11 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +11
-0+ "^lane[1-4]-mode$": + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3, 4, 5, 6] + description: | + Integer describing static lane usage for the lane indicated in + the property name. For Sierra there may be properties lane0 and + lane1, for Torrent all lane[1-4]-mode properties may be + there. The constants to indicate the lane usage are defined in + "include/dt-bindings/phy/phy.h". The lane is assumed to be unused + if its lane<n>-use property does not exist.The defines were intended to be in 'phys' cells. Does putting both lane and mode in the client 'phys' properties not work?
Let me first check if I understood you. So you are suggesting something like this:
dp-phy {
#phy-cells = <5>; /* 1 for phy-type and 4 for lanes = 5 */
...
};dp-bridge {
...
phys = <&dp-phy PHY_TYPE_DP 1 1 0 0>; /* lanes 0 and 1 for DP */
};Best regards,
Jyri
Signature · 2 lines
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Rob Herring
maintainerRe: [PATCH 2/3] dt-bindings: phy: Add lane<n>-mode property to WIZ (SERDES wrapper)
Quoted 39 lines · Jyri Sarha
Quoted 18 lines · Rob Herring
Quoted 17 lines · Jyri Sarha
Add property to indicate the usage of SERDES lane controlled by the WIZ wrapper. The wrapper configuration has some variation depending on how each lane is going to be used.
Signed-off-by Jyri Sarha <[email protected]>--- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +0
-0@@ -97,6 +97,18 @@ patternProperties: Torrent SERDES should follow the bindings specified in Documentation/devicetree/bindings/phy/phy-cadence-dp.txtQuoted 15 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml patternProperties: · line 110
Quoted 11 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +11
-0+ "^lane[1-4]-mode$": + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3, 4, 5, 6] + description: | + Integer describing static lane usage for the lane indicated in + the property name. For Sierra there may be properties lane0 and + lane1, for Torrent all lane[1-4]-mode properties may be + there. The constants to indicate the lane usage are defined in + "include/dt-bindings/phy/phy.h". The lane is assumed to be unused + if its lane<n>-use property does not exist.The defines were intended to be in 'phys' cells. Does putting both lane and mode in the client 'phys' properties not work?
Let me first check if I understood you. So you are suggesting something like this:
Quoted 8 lines
dp-phy { #phy-cells = <5>; /* 1 for phy-type and 4 for lanes = 5 */ ... };dp-bridge { ... phys = <&dp-phy PHY_TYPE_DP 1 1 0 0>; /* lanes 0 and 1 for DP */
Yes, but I think the lanes can be a single cell mask. And I'd probably make that the first cell which is generally "which PHY" and make type/mode the 2nd cell. I'd look for other users of PHY_TYPE_ defines and match what they've done if possible.
Rob
Re: [PATCH 2/3] dt-bindings: phy: Add lane<n>-mode property to WIZ (SERDES wrapper)
Quoted 45 lines · Rob Herring
Quoted 44 lines · Jyri Sarha
Quoted 18 lines · Rob Herring
Quoted 17 lines · Jyri Sarha
Add property to indicate the usage of SERDES lane controlled by the WIZ wrapper. The wrapper configuration has some variation depending on how each lane is going to be used.
Signed-off-by Jyri Sarha <[email protected]>--- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +0
-0@@ -97,6 +97,18 @@ patternProperties: Torrent SERDES should follow the bindings specified in Documentation/devicetree/bindings/phy/phy-cadence-dp.txtQuoted 15 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml patternProperties: · line 110
Quoted 11 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +11
-0+ "^lane[1-4]-mode$": + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3, 4, 5, 6] + description: | + Integer describing static lane usage for the lane indicated in + the property name. For Sierra there may be properties lane0 and + lane1, for Torrent all lane[1-4]-mode properties may be + there. The constants to indicate the lane usage are defined in + "include/dt-bindings/phy/phy.h". The lane is assumed to be unused + if its lane<n>-use property does not exist.The defines were intended to be in 'phys' cells. Does putting both lane and mode in the client 'phys' properties not work?
Let me first check if I understood you. So you are suggesting something like this:
dp-phy { #phy-cells = <5>; /* 1 for phy-type and 4 for lanes = 5 */ ... };
Quoted 9 lines
Quoted 3 lines
dp-bridge { ... phys = <&dp-phy PHY_TYPE_DP 1 1 0 0>; /* lanes 0 and 1 for DP */Yes, but I think the lanes can be a single cell mask. And I'd probably make that the first cell which is generally "which PHY" and make type/mode the 2nd cell. I'd look for other users of
PHY_TYPE_defines and match what they've done if possible.
I see. This will cause some head ache on the driver implementation side, as there is no way for the phy driver to peek the lane use or type from the phy client's device tree node. It also looks to me that the phy API[1] has to be extended quite a bit before the phy client can pass the lane usage information to the phy driver. It will cause some pain to implement the extension without breaking the phy API and causing a nasty cross dependency over all the phy client domains.
Also, there is not much point in putting the PHY_TYPE constant to the phy client's node, as normally the phy client driver will know quite well what PHY_TYPE to use. E.g. a SATA driver will always select PHY_TYPE_SATA and a PCIE driver will select PHY_TYPE_PCIE, etc.
Kishon, if we have to take this road it also starts to sound like we will have to move the phy client's phandle to point to the phy wrapper node, if we want to keep the actual phy driver wrapper agnostic. Then we can make the wrapper to act like a proxy that forwards the phy_ops calls to the actual phy driver. Luckily the per lane phy-type selection is not a blocker for our j721e DisplayPort functionality.
Best regards,
Jyri
[1] include/linux/phy/phy.h
Signature · 2 lines
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Re: [PATCH 2/3] dt-bindings: phy: Add lane<n>-mode property to WIZ (SERDES wrapper)
Hi,
Quoted 69 lines · Jyri Sarha
Quoted 45 lines · Rob Herring
Quoted 44 lines · Jyri Sarha
Quoted 18 lines · Rob Herring
Quoted 17 lines · Jyri Sarha
Add property to indicate the usage of SERDES lane controlled by the WIZ wrapper. The wrapper configuration has some variation depending on how each lane is going to be used.
Signed-off-by Jyri Sarha <[email protected]>--- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +0
-0@@ -97,6 +97,18 @@ patternProperties: Torrent SERDES should follow the bindings specified in Documentation/devicetree/bindings/phy/phy-cadence-dp.txtQuoted 15 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml patternProperties: · line 110
Quoted 11 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +11
-0+ "^lane[1-4]-mode$": + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3, 4, 5, 6] + description: | + Integer describing static lane usage for the lane indicated in + the property name. For Sierra there may be properties lane0 and + lane1, for Torrent all lane[1-4]-mode properties may be + there. The constants to indicate the lane usage are defined in + "include/dt-bindings/phy/phy.h". The lane is assumed to be unused + if its lane<n>-use property does not exist.The defines were intended to be in 'phys' cells. Does putting both lane and mode in the client 'phys' properties not work?
Let me first check if I understood you. So you are suggesting something like this:
dp-phy { #phy-cells = <5>; /* 1 for phy-type and 4 for lanes = 5 */ ... };Quoted 9 lines
Quoted 3 lines
dp-bridge { ... phys = <&dp-phy PHY_TYPE_DP 1 1 0 0>; /* lanes 0 and 1 for DP */Yes, but I think the lanes can be a single cell mask. And I'd probably make that the first cell which is generally "which PHY" and make type/mode the 2nd cell. I'd look for other users of
PHY_TYPE_defines and match what they've done if possible.I see. This will cause some head ache on the driver implementation side, as there is no way for the phy driver to peek the lane use or type from the phy client's device tree node. It also looks to me that the phy API[1] has to be extended quite a bit before the phy client can pass the lane usage information to the phy driver. It will cause some pain to implement the extension without breaking the phy API and causing a nasty cross dependency over all the phy client domains.
Also, there is not much point in putting the
PHY_TYPEconstant to the phy client's node, as normally the phy client driver will know quite well whatPHY_TYPEto use. E.g. a SATA driver will always selectPHY_TYPE_SATAand a PCIE driver will selectPHY_TYPE_PCIE, etc.
Quoted 6 lines
Kishon, if we have to take this road it also starts to sound like we will have to move the phy client's phandle to point to the phy wrapper node, if we want to keep the actual phy driver wrapper agnostic. Then we can make the wrapper to act like a proxy that forwards the
phy_opscalls to the actual phy driver. Luckily the per lane phy-type selection is not a blocker for our j721e DisplayPort functionality.
WIZ is a PHY wrapper and not a PHY in itself. I'm not inclined in modeling WIZ as a PHY and adding an additional level of indirection. This can add more challenges w.r.t PHY sequencing and can also lead to locking issues. That also doesn't accurately represent the HW bock.
Thanks
Kishon
Re: [PATCH 2/3] dt-bindings: phy: Add lane<n>-mode property to WIZ (SERDES wrapper)
Quoted 79 lines · Kishon Vijay Abraham I
Hi,
Quoted 69 lines · Jyri Sarha
Quoted 45 lines · Rob Herring
Quoted 44 lines · Jyri Sarha
Quoted 18 lines · Rob Herring
Quoted 17 lines · Jyri Sarha
Add property to indicate the usage of SERDES lane controlled by the WIZ wrapper. The wrapper configuration has some variation depending on how each lane is going to be used.
Signed-off-by Jyri Sarha <[email protected]>--- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +0
-0@@ -97,6 +97,18 @@ patternProperties: Torrent SERDES should follow the bindings specified in Documentation/devicetree/bindings/phy/phy-cadence-dp.txtQuoted 15 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml patternProperties: · line 110
Quoted 11 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +11
-0+ "^lane[1-4]-mode$": + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3, 4, 5, 6] + description: | + Integer describing static lane usage for the lane indicated in + the property name. For Sierra there may be properties lane0 and + lane1, for Torrent all lane[1-4]-mode properties may be + there. The constants to indicate the lane usage are defined in + "include/dt-bindings/phy/phy.h". The lane is assumed to be unused + if its lane<n>-use property does not exist.The defines were intended to be in 'phys' cells. Does putting both lane and mode in the client 'phys' properties not work?
Let me first check if I understood you. So you are suggesting something like this:
dp-phy { #phy-cells = <5>; /* 1 for phy-type and 4 for lanes = 5 */ ... };Quoted 9 lines
Quoted 3 lines
dp-bridge { ... phys = <&dp-phy PHY_TYPE_DP 1 1 0 0>; /* lanes 0 and 1 for DP */Yes, but I think the lanes can be a single cell mask. And I'd probably make that the first cell which is generally "which PHY" and make type/mode the 2nd cell. I'd look for other users of
PHY_TYPE_defines and match what they've done if possible.I see. This will cause some head ache on the driver implementation side, as there is no way for the phy driver to peek the lane use or type from the phy client's device tree node. It also looks to me that the phy API[1] has to be extended quite a bit before the phy client can pass the lane usage information to the phy driver. It will cause some pain to implement the extension without breaking the phy API and causing a nasty cross dependency over all the phy client domains.
Also, there is not much point in putting the
PHY_TYPEconstant to the phy client's node, as normally the phy client driver will know quite well whatPHY_TYPEto use. E.g. a SATA driver will always selectPHY_TYPE_SATAand a PCIE driver will selectPHY_TYPE_PCIE, etc.Quoted 6 lines
Kishon, if we have to take this road it also starts to sound like we will have to move the phy client's phandle to point to the phy wrapper node, if we want to keep the actual phy driver wrapper agnostic. Then we can make the wrapper to act like a proxy that forwards the
phy_opscalls to the actual phy driver. Luckily the per lane phy-type selection is not a blocker for our j721e DisplayPort functionality.
Quoted 5 lines
WIZ is a PHY wrapper and not a PHY in itself. I'm not inclined in modeling WIZ as a PHY and adding an additional level of indirection. This can add more challenges w.r.t PHY sequencing and can also lead to locking issues. That also doesn't accurately represent the HW bock.
Ok, then assuming the phy wrapper node's lane<n>-mode property can't be used and if the lane-mode information is only available at the phy client driver, we must somehow deliver the phy-mode information from the phy client driver to the phy wrapper driver.
Maybe a way for the phy wrapper driver to request the phy-mode from the actual phy driver, which in turn gets it from the phy client through phy_ops set_mode() call-back.
Then there is the extra twist of a single phy driver serving multiple phy clients using different lanes, but we do not need to cross that bridge for the current DisplayPort functionality.
Best regards,
Jyri
Signature · 2 lines
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
Rob Herring
maintainerRe: [PATCH 2/3] dt-bindings: phy: Add lane<n>-mode property to WIZ (SERDES wrapper)
In reply to Jyri SarhaQuoted 57 lines · Jyri Sarha
Quoted 45 lines · Rob Herring
Quoted 44 lines · Jyri Sarha
Quoted 18 lines · Rob Herring
Quoted 17 lines · Jyri Sarha
Add property to indicate the usage of SERDES lane controlled by the WIZ wrapper. The wrapper configuration has some variation depending on how each lane is going to be used.
Signed-off-by Jyri Sarha <[email protected]>--- .../devicetree/bindings/phy/ti,phy-j721e-wiz.yaml | 12 ++++++++++++ 1 file changed, 12 insertions(+)Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +0
-0@@ -97,6 +97,18 @@ patternProperties: Torrent SERDES should follow the bindings specified in Documentation/devicetree/bindings/phy/phy-cadence-dp.txtQuoted 15 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml patternProperties: · line 110
Quoted 11 lines
Documentation/devicetree/bindings/phy/ti,phy-j721e-wiz.yaml +11
-0+ "^lane[1-4]-mode$": + allOf: + - $ref: /schemas/types.yaml#/definitions/uint32 + - enum: [0, 1, 2, 3, 4, 5, 6] + description: | + Integer describing static lane usage for the lane indicated in + the property name. For Sierra there may be properties lane0 and + lane1, for Torrent all lane[1-4]-mode properties may be + there. The constants to indicate the lane usage are defined in + "include/dt-bindings/phy/phy.h". The lane is assumed to be unused + if its lane<n>-use property does not exist.The defines were intended to be in 'phys' cells. Does putting both lane and mode in the client 'phys' properties not work?
Let me first check if I understood you. So you are suggesting something like this:
dp-phy { #phy-cells = <5>; /* 1 for phy-type and 4 for lanes = 5 */ ... };Quoted 9 lines
Quoted 3 lines
dp-bridge { ... phys = <&dp-phy PHY_TYPE_DP 1 1 0 0>; /* lanes 0 and 1 for DP */Yes, but I think the lanes can be a single cell mask. And I'd probably make that the first cell which is generally "which PHY" and make type/mode the 2nd cell. I'd look for other users of
PHY_TYPE_defines and match what they've done if possible.
Quoted 3 lines
I see. This will cause some head ache on the driver implementation side, as there is no way for the phy driver to peek the lane use or type from the phy client's device tree node.
Yes, there is a way. Not really fast, but use for_each_node_with_property(node, "phys") and filter on ones matching your phy's node.
Quoted 5 lines
It also looks to me that the phy
API[1] has to be extended quite a bit before the phy client can pass the lane usage information to the phy driver. It will cause some pain to implement the extension without breaking the phy API and causing a nasty cross dependency over all the phy client domains.
Not really a concern from a binding standpoint. Bindings shouldn't be designed around some OS's current design or limitations.
There's already several cases using PHY_TYPE_* in phy cells, so I'm not sure what the issue is.
Quoted 4 lines
Also, there is not much point in putting the
PHY_TYPEconstant to the phy client's node, as normally the phy client driver will know quite well whatPHY_TYPEto use. E.g. a SATA driver will always selectPHY_TYPE_SATAand a PCIE driver will selectPHY_TYPE_PCIE, etc.
Good point. That could work as well.
Quoted 16 lines
Kishon, if we have to take this road it also starts to sound like we will have to move the phy client's phandle to point to the phy wrapper node, if we want to keep the actual phy driver wrapper agnostic. Then we can make the wrapper to act like a proxy that forwards the
phy_opscalls to the actual phy driver. Luckily the per lane phy-type selection is not a blocker for our j721e DisplayPort functionality.Best regards,
Jyri[1]
include/linux/phy/phy.h--
Texas Instruments Finland Oy, Porkkalankatu 22, 00180 Helsinki. Y-tunnus/Business ID: 0615521-4. Kotipaikka/Domicile: Helsinki
PATCH 3/3 phy: ti: j721e-wiz: Implement DisplayPort mode to the wiz driver
In reply to Jyri SarhaFor DisplayPort use we need to set WIZ_CONFIG_LANECTL register's P_STANDARD_MODE bits to "mode 3". In the DisplayPort use also the P_ENABLE bits of the same register are set to P_ENABLE instead of P_ENABLE_FORCE, so that the DisplayPort driver can enable and disable the lane as needed. The DisplayPort mode is selected according to lane<n>-mode -property. All other values of lane<n>-mode -property but PHY_TYPE_DP will set P_STANDARD_MODE bits to 0 and P_ENABLE bits to force enable.
--- drivers/phy/ti/phy-j721e-wiz.c | 55 +++++++++++++++++++++++++++++++--- 1 file changed, 51 insertions(+), 4 deletions(-)
drivers/phy/ti/phy-j721e-wiz.c +51 -4
@@ -20,6 +20,7 @@#include <linux/pm_runtime.h> #include <linux/regmap.h> #include <linux/reset-controller.h> +#include <dt-bindings/phy/phy.h> #define WIZ_SERDES_CTRL 0x404#define WIZ_SERDES_TOP_CTRL 0x408
@@ -78,6 +79,8 @@ static const struct reg_field p_enable[WIZ_MAX_LANES] = { REG_FIELD(WIZ_LANECTL(3), 30, 31), }; +enum p_enable {P_ENABLE =2 ,P_ENABLE_FORCE =1 ,P_ENABLE_DISABLE =0 }; +static const struct reg_field p_align[WIZ_MAX_LANES ] = {REG_FIELD (WIZ_LANECTL (0 ),29 ,29 ),REG_FIELD (WIZ_LANECTL (1 ),29 ,29 ),
@@ -220,6 +223,7 @@ struct wiz {struct reset_controller_dev wiz_phy_reset_dev;struct gpio_desc *gpio_typec_dir;int typec_dir_delay; +u32 lane_modes[WIZ_MAX_LANES ]; };static int wiz_reset (struct wiz *wiz)
@@ -242,12 +246,17 @@ static int wiz_reset(struct wiz *wiz)static int wiz_mode_select (struct wiz *wiz) {u32 num_lanes = wiz->num_lanes; +enum wiz_lane_standard_mode mode;int ret;int i;for (i =0 ; i < num_lanes; i++) { - ret =regmap_field_write (wiz->p_standard_mode[i], -LANE_MODE_GEN4 ); +if (wiz->lane_modes[i] ==PHY_TYPE_DP ) + mode =LANE_MODE_GEN1 ; +else + mode =LANE_MODE_GEN4 ; + + ret =regmap_field_write (wiz->p_standard_mode[i], mode);if (ret)return ret; }
@@ -713,7 +722,7 @@ static int wiz_phy_reset_assert(struct reset_controller_dev *rcdev,return ret; } - ret =regmap_field_write (wiz->p_enable[id -1 ], false); + ret =regmap_field_write (wiz->p_enable[id -1 ],P_ENABLE_DISABLE );return ret; }
@@ -740,7 +749,11 @@ static int wiz_phy_reset_deassert(struct reset_controller_dev *rcdev,return ret; } - ret =regmap_field_write (wiz->p_enable[id -1 ], true); +if (wiz->lane_modes[id -1 ] ==PHY_TYPE_DP ) + ret =regmap_field_write (wiz->p_enable[id -1 ],P_ENABLE ); +else + ret =regmap_field_write (wiz->p_enable[id -1 ],P_ENABLE_FORCE ); +return ret; }
@@ -767,6 +780,33 @@ static const struct of_device_id wiz_id_table[] = { };MODULE_DEVICE_TABLE (of, wiz_id_table); +static int wiz_get_lane_mode (struct device *dev,int lane_number, +u32 *lane_mode) +{ +char property_name[11 ];/* 11 is length of "lane0-mode\0" */ +int ret; + + ret =snprintf (property_name,sizeof (property_name),"lane%u-mode" , + lane_number); + +if (ret !=10 ) {/* 10 is length of "lane0-mode" */ +dev_err (dev,"%s: bad lane number %d (ret = %d)\n" , + __func__, lane_number, ret); +return -ENOTSUPP ; + } + + ret =of_property_read_u32 (dev->of_node, property_name, lane_mode); +if (ret == -EINVAL ) { + *lane_mode =PHY_NONE ; +return 0 ; + }else if (ret) { +dev_err (dev,"Getting \"%s\" property failed: %d\n" , + property_name, ret); + } + +return ret; +} +static int wiz_probe (struct platform_device *pdev) {struct reset_controller_dev *phy_reset_dev;
@@ -780,6 +820,7 @@ static int wiz_probe(struct platform_device *pdev)struct wiz *wiz;u32 num_lanes;int ret; +int i; wiz =devm_kzalloc (dev,sizeof (*wiz),GFP_KERNEL );if (!wiz)
@@ -850,6 +891,12 @@ static int wiz_probe(struct platform_device *pdev) } } +for (i =0 ; i < num_lanes; i++) { + ret =wiz_get_lane_mode (dev, i, &wiz->lane_modes[i]); +if (ret) +return ret; + } + wiz->dev = dev; wiz->regmap = regmap; wiz->num_lanes = num_lanes;
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