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gpio: mvebu: clear irq in edge cause register before unmask edge irq

PATCH In review Maxim 2 participants 3 messages Jan 15, 2020 – Jan 23, 2020

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Maxim

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#0 lore raw

PATCH 1/1 gpio: mvebu: clear irq in edge cause register before unmask edge irq

From: Maxim Kiselev <[email protected]>

When input GPIO set from 0 to 1, the interrupt bit asserted in the GPIO Interrupt Cause Register (ICR) even if the corresponding interrupt masked in the GPIO Interrupt Mask Register.

Because interrupt mask register only affects assertion of the interrupt bits in Main Interrupt Cause Register and it does not affect the setting of bits in the GPIO ICR.

So, there is problem, when we unmask interrupt with already asserted bit in the GPIO ICR, then false interrupt immediately occurs even if GPIO don't change their value since last unmask.

Signed-off-by Maxim Kiselev <[email protected]>
---
 drivers/gpio/gpio-mvebu.c | 1 +
 1 file changed, 1 insertion(+)
drivers/gpio/gpio-mvebu.c +1 -0
index 993bbeb3c006..bdae0c08f239 100644
@@ -432,6 +432,7 @@ static void mvebu_gpio_edge_irq_unmask(struct irq_data *d)
 	u32 mask = d->mask;
 
 	irq_gc_lock(gc);
+	mvebu_gpio_write_edge_cause(mvchip, ~mask);
 	ct->mask_cache_priv |= mask;
 	mvebu_gpio_write_edge_mask(mvchip, ct->mask_cache_priv);
 	irq_gc_unlock(gc);
Signature · 1 line
2.24.1
#1 lore raw
Quoted 10 lines · Maxim

From: Maxim Kiselev <[email protected]>

When input GPIO set from 0 to 1, the interrupt bit asserted in the GPIO Interrupt Cause Register (ICR) even if the corresponding interrupt masked in the GPIO Interrupt Mask Register.

Because interrupt mask register only affects assertion of the interrupt bits in Main Interrupt Cause Register and it does not affect the setting of bits in the GPIO ICR.

Quoted 5 lines

So, there is problem, when we unmask interrupt with already asserted bit in the GPIO ICR, then false interrupt immediately occurs even if GPIO don't change their value since last unmask.

Signed-off-by Maxim Kiselev <[email protected]>

This looks correct to me, a review from the MVEBU maintainers would be appreciated.

- Should it be applied to fixes as a regression fix?

- Should it be tagged for stable?

Yours.
Linus Walleij

#2 lore raw
In reply to Maxim
Quoted 10 lines · Maxim

From: Maxim Kiselev <[email protected]>

When input GPIO set from 0 to 1, the interrupt bit asserted in the GPIO Interrupt Cause Register (ICR) even if the corresponding interrupt masked in the GPIO Interrupt Mask Register.

Because interrupt mask register only affects assertion of the interrupt bits in Main Interrupt Cause Register and it does not affect the setting of bits in the GPIO ICR.

Quoted 5 lines

So, there is problem, when we unmask interrupt with already asserted bit in the GPIO ICR, then false interrupt immediately occurs even if GPIO don't change their value since last unmask.

Signed-off-by Maxim Kiselev <[email protected]>

Since there is no feedback from the MVEBU maintainers I have tentatively applied the patch for v5.6 so it gets some testing.

Yours,
Linus Walleij