Add support for suspend clk for Exynos5422 SoC

This patch adds new combatible strings for USBDRD3 for adding missing suspend clk, exynos5422 usbdrd3 support two clk USBD300 and SCLK_USBD300, so add missing suspemd_clk for Exynos542x DWC3 nodes.

Signed-off-by Anand Moon <[email protected]>

---
 arch/arm/boot/dts/exynos5420.dtsi | 8 ++++----
 arch/arm/boot/dts/exynos54xx.dtsi | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

arch/arm/boot/dts/exynos5420.dtsi +4 -4

index b672080e7469..bd505256a223 100644
@@ -1372,8 +1372,8 @@ &trng {
 };
 
 &usbdrd3_0 {
-	clocks = <&clock CLK_USBD300>;
-	clock-names = "usbdrd30";
+	clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>;
+	clock-names = "usbdrd30", "usbdrd30_susp_clk";
 };
 
 &usbdrd_phy0 {

@@ -1383,8 +1383,8 @@ &usbdrd_phy0 {
 };
 
 &usbdrd3_1 {
-	clocks = <&clock CLK_USBD301>;
-	clock-names = "usbdrd30";
+	clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>;
+	clock-names = "usbdrd30", "usbdrd30_susp_clk";
 };
 
 &usbdrd_dwc3_1 {

arch/arm/boot/dts/exynos54xx.dtsi +1 -1

index 8aa5117e58ce..0aac6255de5d 100644
@@ -143,7 +143,7 @@ hsi2c_7: i2c@12cd0000 {
 		};
 
 		usbdrd3_0: usb3-0 {
-			compatible = "samsung,exynos5250-dwusb3";
+			compatible = "samsung,exynos5420-dwusb3";
 			#address-cells = <1>;
 			#size-cells = <1>;
 			ranges;

Quoted 53 lines · Anand Moon

This patch adds new combatible strings for USBDRD3 for adding missing suspend clk, exynos5422 usbdrd3 support two clk USBD300 and SCLK_USBD300, so add missing suspemd_clk for Exynos542x DWC3 nodes.

Signed-off-by Anand Moon <[email protected]>

---
 arch/arm/boot/dts/exynos5420.dtsi | 8 ++++----
 arch/arm/boot/dts/exynos54xx.dtsi | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

arch/arm/boot/dts/exynos5420.dtsi +4 -4

index b672080e7469..bd505256a223 100644
@@ -1372,8 +1372,8 @@ &trng {
 };
 
 &usbdrd3_0 {
-     clocks = <&clock CLK_USBD300>;
-     clock-names = "usbdrd30";
+     clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>;
+     clock-names = "usbdrd30", "usbdrd30_susp_clk";
 };
 
 &usbdrd_phy0 {

@@ -1383,8 +1383,8 @@ &usbdrd_phy0 {
 };
 
 &usbdrd3_1 {
-     clocks = <&clock CLK_USBD301>;
-     clock-names = "usbdrd30";
+     clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>;
+     clock-names = "usbdrd30", "usbdrd30_susp_clk";
 };
 
 &usbdrd_dwc3_1 {

arch/arm/boot/dts/exynos54xx.dtsi +1 -1

index 8aa5117e58ce..0aac6255de5d 100644
@@ -143,7 +143,7 @@ hsi2c_7: i2c@12cd0000 {
              };
 
              usbdrd3_0: usb3-0 {
-                     compatible = "samsung,exynos5250-dwusb3";
+                     compatible = "samsung,exynos5420-dwusb3";
                      #address-cells = <1>;
                      #size-cells = <1>;
                      ranges;

@@ -165,7 +165,7 @@ usbdrd_phy0: phy@12100000 {
              };
 

arch/arm/boot/dts/exynos54xx.dtsi usbdrd_phy0: phy@12100000 { · line 168

Quoted 3 lines

arch/arm/boot/dts/exynos54xx.dtsi +1 -1

              usbdrd3_1: usb3-1 {
-                     compatible = "samsung,exynos5250-dwusb3";
+                     compatible = "samsung,exynos5420-dwusb3";

This affects also Exynos5410 but you do not add new clock there.

Best regards,
Krzysztof

Hi Krzysztof,

Thanks for your review comments.

Quoted 61 lines · Krzysztof Kozlowski

Quoted 51 lines · Anand Moon

This patch adds new combatible strings for USBDRD3 for adding missing suspend clk, exynos5422 usbdrd3 support two clk USBD300 and SCLK_USBD300, so add missing suspemd_clk for Exynos542x DWC3 nodes.

Signed-off-by Anand Moon <[email protected]>

---
 arch/arm/boot/dts/exynos5420.dtsi | 8 ++++----
 arch/arm/boot/dts/exynos54xx.dtsi | 4 ++--
 2 files changed, 6 insertions(+), 6 deletions(-)

arch/arm/boot/dts/exynos5420.dtsi +4 -4

index b672080e7469..bd505256a223 100644
@@ -1372,8 +1372,8 @@ &trng {
 };
 
 &usbdrd3_0 {
-     clocks = <&clock CLK_USBD300>;
-     clock-names = "usbdrd30";
+     clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>;
+     clock-names = "usbdrd30", "usbdrd30_susp_clk";
 };
 
 &usbdrd_phy0 {

@@ -1383,8 +1383,8 @@ &usbdrd_phy0 {
 };
 
 &usbdrd3_1 {
-     clocks = <&clock CLK_USBD301>;
-     clock-names = "usbdrd30";
+     clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>;
+     clock-names = "usbdrd30", "usbdrd30_susp_clk";
 };
 
 &usbdrd_dwc3_1 {

arch/arm/boot/dts/exynos54xx.dtsi +1 -1

index 8aa5117e58ce..0aac6255de5d 100644
@@ -143,7 +143,7 @@ hsi2c_7: i2c@12cd0000 {
              };
 
              usbdrd3_0: usb3-0 {
-                     compatible = "samsung,exynos5250-dwusb3";
+                     compatible = "samsung,exynos5420-dwusb3";
                      #address-cells = <1>;
                      #size-cells = <1>;
                      ranges;

arch/arm/boot/dts/exynos54xx.dtsi usbdrd_phy0: phy@12100000 { · line 168

Quoted 5 lines

arch/arm/boot/dts/exynos54xx.dtsi +1 -1

@@ -165,7 +165,7 @@ usbdrd_phy0: phy@12100000 {
              };
 
              usbdrd3_1: usb3-1 {
-                     compatible = "samsung,exynos5250-dwusb3";
+                     compatible = "samsung,exynos5420-dwusb3";

This affects also Exynos5410 but you do not add new clock there.

Quoted 3 lines

Best regards,
Krzysztof

Ok I will update this Exynos5410 dts.

Is samsung,exynos54xx-dwusb3 is valid compatible string for both the SoC.

Long time ago I tried to add suspend clk for dwc3 phy which was wrong appoch, see below.

[0] https://lore.kernel.org/patchwork/patch/837635/
[1] https://lore.kernel.org/patchwork/patch/837636/

This patch series tries to enable suspend clk using exynos dwc3 driver, for this I have added new compatible string "samsung,exynos5420-dwusb3" so that we could add new suspend clk in addition to the core clk. exynos dwc3 driver will help enable/disable these clk.

-Anand

Anand Moon (3):
devicetree: bindings: exynos: Add new compatible for Exynos5420 dwc3
clocks support
ARM: dts: exynos: Add missing usbdrd3 suspend clk
usb: dwc3: exynos: Add support for Exynos5422 suspend clk

 Documentation/devicetree/bindings/usb/exynos-usb.txt | 4 +++-
 arch/arm/boot/dts/exynos5420.dtsi                    | 8 ++++----
 arch/arm/boot/dts/exynos54xx.dtsi                    | 4 ++--
 drivers/usb/dwc3/dwc3-exynos.c                       | 9 +++++++++
 4 files changed, 18 insertions(+), 7 deletions(-)

--
2.25.0

Long time ago I tried to add suspend clk for dwc3 phy which was wrong appoch, see below.

[0] https://lore.kernel.org/patchwork/patch/837635/
[1] https://lore.kernel.org/patchwork/patch/837636/

This patch series tries to enable suspend clk using exynos dwc3 driver, for this I have added new compatible string "samsung,exynos5420-dwusb3" so that we could add new suspend clk in addition to the core clk. exynos dwc3 driver will help enable/disable these clk.

-Anand

Anand Moon (3):
devicetree: bindings: exynos: Add new compatible for Exynos5420 dwc3
clocks support
ARM: dts: exynos: Add missing usbdrd3 suspend clk
usb: dwc3: exynos: Add support for Exynos5422 suspend clk

 Documentation/devicetree/bindings/usb/exynos-usb.txt | 4 +++-
 arch/arm/boot/dts/exynos5420.dtsi                    | 8 ++++----
 arch/arm/boot/dts/exynos54xx.dtsi                    | 4 ++--
 drivers/usb/dwc3/dwc3-exynos.c                       | 9 +++++++++
 4 files changed, 18 insertions(+), 7 deletions(-)

Signature · 1 line

2.25.0

Quoted 6 lines · Anand Moon

Long time ago I tried to add suspend clk for dwc3 phy which was wrong appoch, see below.

[0] https://lore.kernel.org/patchwork/patch/837635/
[1] https://lore.kernel.org/patchwork/patch/837636/

You ignored parts of my review from these previous patches. I asked for describing WHY are you doing this and WHAT problem are you trying to solve. I asked for this multiple times. Unfortunately I cannot find the answers to my questions in this patchset...

Best regards,
Krzysztof

Hi Krzysztof,

Quoted 9 lines · Krzysztof Kozlowski

Quoted 6 lines · Anand Moon

Long time ago I tried to add suspend clk for dwc3 phy which was wrong appoch, see below.

[0] https://lore.kernel.org/patchwork/patch/837635/
[1] https://lore.kernel.org/patchwork/patch/837636/

Thanks for your review comments.

Quoted 7 lines

You ignored parts of my review from these previous patches. I asked for describing WHY are you doing this and WHAT problem are you trying to solve. I asked for this multiple times. Unfortunately I cannot find the answers to my questions in this patchset...

Best regards,
Krzysztof

I dont know how to resolve this issue, but I want to re-post some of my changes back for review. let me try again.

My future goal is to add #power-domain for FSYS and FSYS2 which I am trying to resolve some issue.
Also add run-time power management for USB3 drivers.

Here is the clk diagram for FSYS clk as per Exynos5422 user manual.
[0] https://imgur.com/gallery/zAiBoyh

As per the USB 3.0 Architecture T I.

2.13.1 PHY Power Management
The SS PHY has power states P0, P1, P2, and P3, corresponding to the SS LPM states of U0, U1, U2,and U3. In the P3 state,SS PHY does not drive the default functional clock,instead, the *susp_clk* is used in its place.

So enable the suspend clk help control the power management states for the DWC3 controller.