clk: keystone: Add new driver to handle ehrpwm tbclk
v3 cover clk: keystone: Add new driver to handle ehrpwm tbclk
On TI's AM654 and J721e SoCs, certain clocks can be gated/ungated by setting a single bit in SoC's System Control registers. Sometime more than one clock control can be in the same register. But these registers might also have bits to control other SoC functionalities.
For example, Time Base clock(TBclk) enable bits for various EPWM IPs are all in EPWM_CTRL Syscon registers on K2G SoC.
This series adds a new clk driver to support controlling tbclk. Registers which control clocks will be grouped into a syscon DT node, thus enabling sharing of register across clk drivers and other drivers.
v3:
Register syscon node as clk provider
v2:
Simplify driver to have only one clock node per group of syscon controller registers instead of one per clock instance.
v1: https://patchwork.kernel.org/cover/10848783/
Vignesh Raghavendra (2):
dt-bindings: clock: Add binding documentation for TI syscon gate clock
clk: keystone: Add new driver to handle syscon based clocks
.../bindings/clock/ti,am654-ehrpwm-tbclk.yaml | 35 ++++ drivers/clk/keystone/Kconfig | 8 + drivers/clk/keystone/Makefile | 1 + drivers/clk/keystone/syscon-clk.c | 172 ++++++++++++++++++ 4 files changed, 216 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml create mode 100644 drivers/clk/keystone/syscon-clk.c
Signature · 1 line
2.25.0
PATCH v3 1/2 dt-bindings: clock: Add binding documentation for TI syscon gate clock
Add dt bindings for TI syscon gate clock driver that is used to control EHRPWM's TimeBase clock (TBCLK) on TI's AM654 SoC.
--- .../bindings/clock/ti,am654-ehrpwm-tbclk.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file +35 -0
@@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,am654-ehrpwm-tbclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI syscon gate clock driver + +maintainers: + - Vignesh Raghavendra <[email protected]> + +properties: + compatible: + items: + - const: ti,am654-ehrpwm-tbclk + - const: syscon + + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +examples: + - | + ehrpwm_tbclk: syscon@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + };
Signature · 1 line
2.25.0
Rob Herring
maintainerRe: [PATCH v3 1/2] dt-bindings: clock: Add binding documentation for TI syscon gate clock
Quoted 15 lines · Vignesh Raghavendra
Add dt bindings for TI syscon gate clock driver that is used to control EHRPWM's TimeBase clock (TBCLK) on TI's AM654 SoC.
Signed-off-by Vignesh Raghavendra <[email protected]>--- .../bindings/clock/ti,am654-ehrpwm-tbclk.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yamlDocumentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file +0
-0
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml line 7
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Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file +7
-0@@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,am654-ehrpwm-tbclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI syscon gate clock driver
Bindings are for h/w blocks, not drivers.
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml line 16
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Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file +9
-0+ +maintainers: + - Vignesh Raghavendra <[email protected]> + +properties: + compatible: + items: + - const: ti,am654-ehrpwm-tbclk + - const: syscon
Why is this a syscon? Are there other functions or it's just the easy way to get a regmap.
Quoted 22 lines
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file +19
-0+ + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +examples: + - | + ehrpwm_tbclk: syscon@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + };Signature · 1 line
2.25.0
Re: [PATCH v3 1/2] dt-bindings: clock: Add binding documentation for TI syscon gate clock
Hi,
Quoted 10 lines · Rob Herring
Quoted 9 lines · Vignesh Raghavendra
Add dt bindings for TI syscon gate clock driver that is used to control EHRPWM's TimeBase clock (TBCLK) on TI's AM654 SoC.
Signed-off-by Vignesh Raghavendra <[email protected]>--- .../bindings/clock/ti,am654-ehrpwm-tbclk.yaml | 35 +++++++++++++++++++ 1 file changed, 35 insertions(+) create mode 100644 Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml
Quoted 16 lines
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml line 7
Quoted 13 lines
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file +7
-0@@ -0,0 +1,35 @@ +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause) +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/clock/ti,am654-ehrpwm-tbclk.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: TI syscon gate clock driverBindings are for h/w blocks, not drivers.
Will drop driver from the title and commit msg
Quoted 4 lines
Quoted 4 lines
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file +4
-0+ +maintainers: + - Vignesh Raghavendra <[email protected]> +
Quoted 9 lines
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml line 16
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Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file +5
-0+properties: + compatible: + items: + - const: ti,am654-ehrpwm-tbclk + - const: sysconWhy is this a syscon? Are there other functions or it's just the easy way to get a regmap.
Register that has tbclk enable/disable bit also contains bits to control other functionalities and would need to be shared. Therefore its modeled as syscon.
Regards
Vignesh
Quoted 22 lines
Quoted 22 lines
Documentation/devicetree/bindings/clock/ti,am654-ehrpwm-tbclk.yaml new file +19
-0+ + "#clock-cells": + const: 1 + + reg: + maxItems: 1 + +required: + - compatible + - "#clock-cells" + - reg + +examples: + - | + ehrpwm_tbclk: syscon@4140 { + compatible = "ti,am654-ehrpwm-tbclk", "syscon"; + reg = <0x4140 0x18>; + #clock-cells = <1>; + };Signature · 1 line
2.25.0
Signature · 2 lines
Regards Vignesh
PATCH v3 2/2 clk: keystone: Add new driver to handle syscon based clocks
In reply to Vignesh RaghavendraOn TI's AM654/J721e SoCs, certain clocks can be gatemld/ungated by setting a single bit in SoC's System Control Module registers. Sometime more than one clock control can be in the same register.
Add a driver to support such clocks using syscon framework. Driver currently supports controlling EHRPWM's TimeBase clock(TBCLK) for AM654 SoC.
--- drivers/clk/keystone/Kconfig | 8 ++ drivers/clk/keystone/Makefile | 1 + drivers/clk/keystone/syscon-clk.c | 172 ++++++++++++++++++++++++++++++ 3 files changed, 181 insertions(+) create mode 100644 drivers/clk/keystone/syscon-clk.c
drivers/clk/keystone/Kconfig +8 -0
@@ -26,3 +26,11 @@ config TI_SCI_CLK_PROBE_FROM_FW This is mostly only useful for debugging purposes, and will increase the boot time of the device. If you want the clocks probed from firmware, say Y. Otherwise, say N. + +config TI_SYSCON_CLK + tristate "Syscon based clock driver for K2/K3 SoCs" + depends on ARCH_KEYSTONE || ARCH_K3 || COMPILE_TEST + default (ARCH_KEYSTONE || ARCH_K3) + help + This adds clock driver support for syscon based gate + clocks on TI's K2 and K3 SoCs.
drivers/clk/keystone/Makefile +1 -0
@@ -1,3 +1,4 @@ # SPDX-License-Identifier: GPL-2.0-only obj-$(CONFIG_COMMON_CLK_KEYSTONE) += pll.o gate.o obj-$(CONFIG_TI_SCI_CLK) += sci-clk.o +obj-$(CONFIG_TI_SYSCON_CLK) += syscon-clk.o
drivers/clk/keystone/syscon-clk.c new file +172 -0
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Signature · 1 line
2.25.0