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Add clock drivers for SM8250 SoC

PATCH Applied Vinod Koul 5 participants 14 messages Feb 24, 2020 – Mar 9, 2020

Subsystems (4)
Device tree bindings Arm Qualcomm mailing list Common clk Qualcomm clock drivers
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Vinod Koul

author
#0 lore raw

v4 cover Add clock drivers for SM8250 SoC

This series adds clock drivers support for SM8250 SoC. As part of the device tree, the sm8250 dts file has basic nodes like CPU, PSCI, intc, timer and clock controller.

Required clock controller driver and RPMH cloks are added to support peripherals like USB.

All this configuration is added to support SM8250 to boot up to the serial console.

Changes in v4:
- Make qcom,gcc-sm8250.yaml license as dual GPL + BSD

Changes in v3:
- Dropped accepted patches by Steve
- Split the common rename patch to rename and refactor patches
- Rebase on clk/clk-qcom and move yaml binding to .../bindings/clock/qcom,gcc-sm8250.yaml
- Fix comments form Steve on gcc-sm8250 clk driver

Taniya Das (5):
clk: qcom: clk-alpha-pll: Use common names for defines
clk: qcom: clk-alpha-pll: Refactor trion PLL
clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs
dt-bindings: clock: Add SM8250 GCC clock bindings
clk: qcom: gcc: Add global clock controller driver for SM8250

 .../bindings/clock/qcom,gcc-sm8250.yaml       |   72 +
 drivers/clk/qcom/Kconfig                      |    7 +
 drivers/clk/qcom/Makefile                     |    1 +
 drivers/clk/qcom/clk-alpha-pll.c              |  264 +-
 drivers/clk/qcom/clk-alpha-pll.h              |   12 +
 drivers/clk/qcom/gcc-sm8250.c                 | 3690 +++++++++++++++++
 include/dt-bindings/clock/qcom,gcc-sm8250.h   |  271 ++
 7 files changed, 4268 insertions(+), 49 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
 create mode 100644 drivers/clk/qcom/gcc-sm8250.c
 create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h
Signature · 1 line
2.24.1
author
#1 lore raw

PATCH v4 1/5 clk: qcom: clk-alpha-pll: Use common names for defines

From: Taniya Das <[email protected]>

The PLL run and standby modes are similar across the PLLs, thus rename them to common names and update the use of these.

Signed-off-by Taniya Das <[email protected]>
Signed-off-by Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by Vinod Koul <[email protected]>
---
 drivers/clk/qcom/clk-alpha-pll.c | 40 ++++++++++++++------------------
 1 file changed, 17 insertions(+), 23 deletions(-)
drivers/clk/qcom/clk-alpha-pll.c +17 -23
index 6d946770a80f..0bdf6e45fac9 100644
@@ -134,15 +134,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 #define PLL_HUAYRA_N_MASK		0xff
 #define PLL_HUAYRA_ALPHA_WIDTH		16
 
-#define FABIA_OPMODE_STANDBY	0x0
-#define FABIA_OPMODE_RUN	0x1
-
-#define FABIA_PLL_OUT_MASK	0x7
-#define FABIA_PLL_RATE_MARGIN	500
-
-#define TRION_PLL_STANDBY	0x0
-#define TRION_PLL_RUN		0x1
-#define TRION_PLL_OUT_MASK	0x7
+#define PLL_STANDBY		0x0
+#define PLL_RUN			0x1
+#define PLL_OUT_MASK		0x7
+#define PLL_RATE_MARGIN		500
 
 #define pll_alpha_width(p)					\
 		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ?	\

@@ -766,7 +761,7 @@ static int trion_pll_is_enabled(struct clk_alpha_pll *pll,
 	if (ret)
 		return 0;
 
-	return ((opmode_regval & TRION_PLL_RUN) && (mode_regval & PLL_OUTCTRL));
+	return ((opmode_regval & PLL_RUN) && (mode_regval & PLL_OUTCTRL));
 }
 
 static int clk_trion_pll_is_enabled(struct clk_hw *hw)

@@ -796,7 +791,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
 	}
 
 	/* Set operation mode to RUN */
-	regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_RUN);
+	regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
 
 	ret = wait_for_pll_enable_lock(pll);
 	if (ret)

@@ -804,7 +799,7 @@ static int clk_trion_pll_enable(struct clk_hw *hw)
 
 	/* Enable the PLL outputs */
 	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
-				 TRION_PLL_OUT_MASK, TRION_PLL_OUT_MASK);
+				 PLL_OUT_MASK, PLL_OUT_MASK);
 	if (ret)
 		return ret;
 

@@ -837,12 +832,12 @@ static void clk_trion_pll_disable(struct clk_hw *hw)
 
 	/* Disable the PLL outputs */
 	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
-				 TRION_PLL_OUT_MASK, 0);
+				 PLL_OUT_MASK, 0);
 	if (ret)
 		return;
 
 	/* Place the PLL mode in STANDBY */
-	regmap_write(regmap, PLL_OPMODE(pll), TRION_PLL_STANDBY);
+	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
 	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
 }
 

@@ -1089,14 +1084,14 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
 		return ret;
 
 	/* Skip If PLL is already running */
-	if ((opmode_val & FABIA_OPMODE_RUN) && (val & PLL_OUTCTRL))
+	if ((opmode_val & PLL_RUN) && (val & PLL_OUTCTRL))
 		return 0;
 
 	ret = regmap_update_bits(regmap, PLL_MODE(pll), PLL_OUTCTRL, 0);
 	if (ret)
 		return ret;
 
-	ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
+	ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
 	if (ret)
 		return ret;
 

@@ -1105,7 +1100,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
 	if (ret)
 		return ret;
 
-	ret = regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_RUN);
+	ret = regmap_write(regmap, PLL_OPMODE(pll), PLL_RUN);
 	if (ret)
 		return ret;
 

@@ -1114,7 +1109,7 @@ static int alpha_pll_fabia_enable(struct clk_hw *hw)
 		return ret;
 
 	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll),
-				 FABIA_PLL_OUT_MASK, FABIA_PLL_OUT_MASK);
+				 PLL_OUT_MASK, PLL_OUT_MASK);
 	if (ret)
 		return ret;
 

@@ -1144,13 +1139,12 @@ static void alpha_pll_fabia_disable(struct clk_hw *hw)
 		return;
 
 	/* Disable main outputs */
-	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), FABIA_PLL_OUT_MASK,
-				 0);
+	ret = regmap_update_bits(regmap, PLL_USER_CTL(pll), PLL_OUT_MASK, 0);
 	if (ret)
 		return;
 
 	/* Place the PLL in STANDBY */
-	regmap_write(regmap, PLL_OPMODE(pll), FABIA_OPMODE_STANDBY);
+	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
 }
 
 static unsigned long alpha_pll_fabia_recalc_rate(struct clk_hw *hw,

@@ -1171,7 +1165,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
 	u32 l, alpha_width = pll_alpha_width(pll);
 	u64 a;
-	unsigned long rrate, max = rate + FABIA_PLL_RATE_MARGIN;
+	unsigned long rrate, max = rate + PLL_RATE_MARGIN;
 
 	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
 

@@ -1230,7 +1224,7 @@ static int alpha_pll_fabia_prepare(struct clk_hw *hw)
 	 * Due to a limited number of bits for fractional rate programming, the
 	 * rounded up rate could be marginally higher than the requested rate.
 	 */
-	if (rrate > (cal_freq + FABIA_PLL_RATE_MARGIN) || rrate < cal_freq)
+	if (rrate > (cal_freq + PLL_RATE_MARGIN) || rrate < cal_freq)
 		return -EINVAL;
 
 	/* Setup PLL for calibration frequency */
Signature · 1 line
2.24.1
maintainer Applied
#2 lore raw

Re: [PATCH v4 1/5] clk: qcom: clk-alpha-pll: Use common names for defines

Quoting Vinod Koul (2020-02-23 20:49:59)

Quoted 9 lines

From: Taniya Das <[email protected]>

The PLL run and standby modes are similar across the PLLs, thus rename them to common names and update the use of these.

Signed-off-by Taniya Das <[email protected]>
Signed-off-by Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by Vinod Koul <[email protected]>

---

Applied to clk-next

author
#3 lore raw

PATCH v4 2/5 clk: qcom: clk-alpha-pll: Refactor trion PLL

In reply to Vinod Koul

From: Taniya Das <[email protected]>

Remove duplicate function for calculating the round rate of PLL and also update the trion pll ops to use the common function.

Signed-off-by Taniya Das <[email protected]>
Signed-off-by Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by Vinod Koul <[email protected]>
---
 drivers/clk/qcom/clk-alpha-pll.c | 33 ++++++--------------------------
 1 file changed, 6 insertions(+), 27 deletions(-)
drivers/clk/qcom/clk-alpha-pll.c +6 -27
index 0bdf6e45fac9..0adec585eb4f 100644
@@ -845,33 +845,12 @@ static unsigned long
 clk_trion_pll_recalc_rate(struct clk_hw *hw, unsigned long parent_rate)
 {
 	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
-	struct regmap *regmap = pll->clkr.regmap;
-	u32 l, frac;
-	u64 prate = parent_rate;
-
-	regmap_read(regmap, PLL_L_VAL(pll), &l);
-	regmap_read(regmap, PLL_ALPHA_VAL(pll), &frac);
-
-	return alpha_pll_calc_rate(prate, l, frac, ALPHA_REG_16BIT_WIDTH);
-}
-
-static long clk_trion_pll_round_rate(struct clk_hw *hw, unsigned long rate,
-				     unsigned long *prate)
-{
-	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
-	unsigned long min_freq, max_freq;
-	u32 l;
-	u64 a;
-
-	rate = alpha_pll_round_rate(rate, *prate,
-				    &l, &a, ALPHA_REG_16BIT_WIDTH);
-	if (!pll->vco_table || alpha_pll_find_vco(pll, rate))
-		return rate;
+	u32 l, frac, alpha_width = pll_alpha_width(pll);
 
-	min_freq = pll->vco_table[0].min_freq;
-	max_freq = pll->vco_table[pll->num_vco - 1].max_freq;
+	regmap_read(pll->clkr.regmap, PLL_L_VAL(pll), &l);
+	regmap_read(pll->clkr.regmap, PLL_ALPHA_VAL(pll), &frac);
 
-	return clamp(rate, min_freq, max_freq);
+	return alpha_pll_calc_rate(parent_rate, l, frac, alpha_width);
 }
 
 const struct clk_ops clk_alpha_pll_fixed_ops = {

@@ -917,7 +896,7 @@ const struct clk_ops clk_trion_fixed_pll_ops = {
 	.disable = clk_trion_pll_disable,
 	.is_enabled = clk_trion_pll_is_enabled,
 	.recalc_rate = clk_trion_pll_recalc_rate,
-	.round_rate = clk_trion_pll_round_rate,
+	.round_rate = clk_alpha_pll_round_rate,
 };
 EXPORT_SYMBOL_GPL(clk_trion_fixed_pll_ops);
 

@@ -1173,7 +1152,7 @@ static int alpha_pll_fabia_set_rate(struct clk_hw *hw, unsigned long rate,
 	 * Due to limited number of bits for fractional rate programming, the
 	 * rounded up rate could be marginally higher than the requested rate.
 	 */
-	if (rrate > max || rrate < rate) {
+	if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
 		pr_err("%s: Rounded rate %lu not within range [%lu, %lu)\n",
 		       clk_hw_get_name(hw), rrate, rate, max);
 		return -EINVAL;
Signature · 1 line
2.24.1
maintainer Applied
#4 lore raw

Re: [PATCH v4 2/5] clk: qcom: clk-alpha-pll: Refactor trion PLL

Quoting Vinod Koul (2020-02-23 20:50:00)

Quoted 9 lines

From: Taniya Das <[email protected]>

Remove duplicate function for calculating the round rate of PLL and also update the trion pll ops to use the common function.

Signed-off-by Taniya Das <[email protected]>
Signed-off-by Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by Vinod Koul <[email protected]>

---

Applied to clk-next

author
#5 lore raw

PATCH v4 3/5 clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs

In reply to Vinod Koul

From: Taniya Das <[email protected]>

Add programming sequence support for managing the Lucid PLLs.

Signed-off-by Taniya Das <[email protected]>
Signed-off-by Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by Vinod Koul <[email protected]>
---
 drivers/clk/qcom/clk-alpha-pll.c | 193 +++++++++++++++++++++++++++++++
 drivers/clk/qcom/clk-alpha-pll.h |  12 ++
 2 files changed, 205 insertions(+)
drivers/clk/qcom/clk-alpha-pll.c +193 -0
index 0adec585eb4f..9b2dfa08acb2 100644
@@ -52,6 +52,7 @@
 #define PLL_CONFIG_CTL_U1(p)	((p)->offset + (p)->regs[PLL_OFF_CONFIG_CTL_U1])
 #define PLL_TEST_CTL(p)		((p)->offset + (p)->regs[PLL_OFF_TEST_CTL])
 #define PLL_TEST_CTL_U(p)	((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U])
+#define PLL_TEST_CTL_U1(p)     ((p)->offset + (p)->regs[PLL_OFF_TEST_CTL_U1])
 #define PLL_STATUS(p)		((p)->offset + (p)->regs[PLL_OFF_STATUS])
 #define PLL_OPMODE(p)		((p)->offset + (p)->regs[PLL_OFF_OPMODE])
 #define PLL_FRAC(p)		((p)->offset + (p)->regs[PLL_OFF_FRAC])

@@ -116,6 +117,22 @@ const u8 clk_alpha_pll_regs[][PLL_OFF_MAX_REGS] = {
 		[PLL_OFF_ALPHA_VAL] = 0x40,
 		[PLL_OFF_CAL_VAL] = 0x44,
 	},
+	[CLK_ALPHA_PLL_TYPE_LUCID] =  {
+		[PLL_OFF_L_VAL] = 0x04,
+		[PLL_OFF_CAL_L_VAL] = 0x08,
+		[PLL_OFF_USER_CTL] = 0x0c,
+		[PLL_OFF_USER_CTL_U] = 0x10,
+		[PLL_OFF_USER_CTL_U1] = 0x14,
+		[PLL_OFF_CONFIG_CTL] = 0x18,
+		[PLL_OFF_CONFIG_CTL_U] = 0x1c,
+		[PLL_OFF_CONFIG_CTL_U1] = 0x20,
+		[PLL_OFF_TEST_CTL] = 0x24,
+		[PLL_OFF_TEST_CTL_U] = 0x28,
+		[PLL_OFF_TEST_CTL_U1] = 0x2c,
+		[PLL_OFF_STATUS] = 0x30,
+		[PLL_OFF_OPMODE] = 0x38,
+		[PLL_OFF_ALPHA_VAL] = 0x40,
+	},
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 

@@ -139,6 +156,10 @@ EXPORT_SYMBOL_GPL(clk_alpha_pll_regs);
 #define PLL_OUT_MASK		0x7
 #define PLL_RATE_MARGIN		500
 
+/* LUCID PLL specific settings and offsets */
+#define LUCID_PLL_CAL_VAL	0x44
+#define LUCID_PCAL_DONE		BIT(26)
+
 #define pll_alpha_width(p)					\
 		((PLL_ALPHA_VAL_U(p) - PLL_ALPHA_VAL(p) == 4) ?	\
 				 ALPHA_REG_BITWIDTH : ALPHA_REG_16BIT_WIDTH)

@@ -1370,3 +1391,175 @@ const struct clk_ops clk_alpha_pll_postdiv_fabia_ops = {
 	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
 };
 EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_fabia_ops);
+
+/**
+ * clk_lucid_pll_configure - configure the lucid pll
+ *
+ * @pll: clk alpha pll
+ * @regmap: register map
+ * @config: configuration to apply for pll
+ */
+void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+			     const struct alpha_pll_config *config)
+{
+	if (config->l)
+		regmap_write(regmap, PLL_L_VAL(pll), config->l);
+
+	regmap_write(regmap, PLL_CAL_L_VAL(pll), LUCID_PLL_CAL_VAL);
+
+	if (config->alpha)
+		regmap_write(regmap, PLL_ALPHA_VAL(pll), config->alpha);
+
+	if (config->config_ctl_val)
+		regmap_write(regmap, PLL_CONFIG_CTL(pll),
+			     config->config_ctl_val);
+
+	if (config->config_ctl_hi_val)
+		regmap_write(regmap, PLL_CONFIG_CTL_U(pll),
+			     config->config_ctl_hi_val);
+
+	if (config->config_ctl_hi1_val)
+		regmap_write(regmap, PLL_CONFIG_CTL_U1(pll),
+			     config->config_ctl_hi1_val);
+
+	if (config->user_ctl_val)
+		regmap_write(regmap, PLL_USER_CTL(pll),
+			     config->user_ctl_val);
+
+	if (config->user_ctl_hi_val)
+		regmap_write(regmap, PLL_USER_CTL_U(pll),
+			     config->user_ctl_hi_val);
+
+	if (config->user_ctl_hi1_val)
+		regmap_write(regmap, PLL_USER_CTL_U1(pll),
+			     config->user_ctl_hi1_val);
+
+	if (config->test_ctl_val)
+		regmap_write(regmap, PLL_TEST_CTL(pll),
+			     config->test_ctl_val);
+
+	if (config->test_ctl_hi_val)
+		regmap_write(regmap, PLL_TEST_CTL_U(pll),
+			     config->test_ctl_hi_val);
+
+	if (config->test_ctl_hi1_val)
+		regmap_write(regmap, PLL_TEST_CTL_U1(pll),
+			     config->test_ctl_hi1_val);
+
+	regmap_update_bits(regmap, PLL_MODE(pll), PLL_UPDATE_BYPASS,
+			   PLL_UPDATE_BYPASS);
+
+	/* Disable PLL output */
+	regmap_update_bits(regmap, PLL_MODE(pll),  PLL_OUTCTRL, 0);
+
+	/* Set operation mode to OFF */
+	regmap_write(regmap, PLL_OPMODE(pll), PLL_STANDBY);
+
+	/* Place the PLL in STANDBY mode */
+	regmap_update_bits(regmap, PLL_MODE(pll), PLL_RESET_N, PLL_RESET_N);
+}
+EXPORT_SYMBOL_GPL(clk_lucid_pll_configure);
+
+/*
+ * The Lucid PLL requires a power-on self-calibration which happens when the
+ * PLL comes out of reset. Calibrate in case it is not completed.
+ */
+static int alpha_pll_lucid_prepare(struct clk_hw *hw)
+{
+	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+	u32 regval;
+	int ret;
+
+	/* Return early if calibration is not needed. */
+	regmap_read(pll->clkr.regmap, PLL_STATUS(pll), &regval);
+	if (regval & LUCID_PCAL_DONE)
+		return 0;
+
+	/* On/off to calibrate */
+	ret = clk_trion_pll_enable(hw);
+	if (!ret)
+		clk_trion_pll_disable(hw);
+
+	return ret;
+}
+
+static int alpha_pll_lucid_set_rate(struct clk_hw *hw, unsigned long rate,
+				    unsigned long prate)
+{
+	struct clk_alpha_pll *pll = to_clk_alpha_pll(hw);
+	unsigned long rrate;
+	u32 regval, l, alpha_width = pll_alpha_width(pll);
+	u64 a;
+	int ret;
+
+	rrate = alpha_pll_round_rate(rate, prate, &l, &a, alpha_width);
+
+	/*
+	 * Due to a limited number of bits for fractional rate programming, the
+	 * rounded up rate could be marginally higher than the requested rate.
+	 */
+	if (rrate > (rate + PLL_RATE_MARGIN) || rrate < rate) {
+		pr_err("Call set rate on the PLL with rounded rates!\n");
+		return -EINVAL;
+	}
+
+	regmap_write(pll->clkr.regmap, PLL_L_VAL(pll), l);
+	regmap_write(pll->clkr.regmap, PLL_ALPHA_VAL(pll), a);
+
+	/* Latch the PLL input */
+	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
+				 PLL_UPDATE, PLL_UPDATE);
+	if (ret)
+		return ret;
+
+	/* Wait for 2 reference cycles before checking the ACK bit. */
+	udelay(1);
+	regmap_read(pll->clkr.regmap, PLL_MODE(pll), &regval);
+	if (!(regval & ALPHA_PLL_ACK_LATCH)) {
+		pr_err("Lucid PLL latch failed. Output may be unstable!\n");
+		return -EINVAL;
+	}
+
+	/* Return the latch input to 0 */
+	ret = regmap_update_bits(pll->clkr.regmap, PLL_MODE(pll),
+				 PLL_UPDATE, 0);
+	if (ret)
+		return ret;
+
+	if (clk_hw_is_enabled(hw)) {
+		ret = wait_for_pll_enable_lock(pll);
+		if (ret)
+			return ret;
+	}
+
+	/* Wait for PLL output to stabilize */
+	udelay(100);
+	return 0;
+}
+
+const struct clk_ops clk_alpha_pll_lucid_ops = {
+	.prepare = alpha_pll_lucid_prepare,
+	.enable = clk_trion_pll_enable,
+	.disable = clk_trion_pll_disable,
+	.is_enabled = clk_trion_pll_is_enabled,
+	.recalc_rate = clk_trion_pll_recalc_rate,
+	.round_rate = clk_alpha_pll_round_rate,
+	.set_rate = alpha_pll_lucid_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_lucid_ops);
+
+const struct clk_ops clk_alpha_pll_fixed_lucid_ops = {
+	.enable = clk_trion_pll_enable,
+	.disable = clk_trion_pll_disable,
+	.is_enabled = clk_trion_pll_is_enabled,
+	.recalc_rate = clk_trion_pll_recalc_rate,
+	.round_rate = clk_alpha_pll_round_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_fixed_lucid_ops);
+
+const struct clk_ops clk_alpha_pll_postdiv_lucid_ops = {
+	.recalc_rate = clk_alpha_pll_postdiv_fabia_recalc_rate,
+	.round_rate = clk_alpha_pll_postdiv_fabia_round_rate,
+	.set_rate = clk_alpha_pll_postdiv_fabia_set_rate,
+};
+EXPORT_SYMBOL_GPL(clk_alpha_pll_postdiv_lucid_ops);
drivers/clk/qcom/clk-alpha-pll.h +12 -0
index fbc1f67c7a26..704674a153b6 100644
@@ -14,6 +14,7 @@ enum {
 	CLK_ALPHA_PLL_TYPE_BRAMMO,
 	CLK_ALPHA_PLL_TYPE_FABIA,
 	CLK_ALPHA_PLL_TYPE_TRION,
+	CLK_ALPHA_PLL_TYPE_LUCID,
 	CLK_ALPHA_PLL_TYPE_MAX,
 };
 

@@ -30,6 +31,7 @@ enum {
 	PLL_OFF_CONFIG_CTL_U1,
 	PLL_OFF_TEST_CTL,
 	PLL_OFF_TEST_CTL_U,
+	PLL_OFF_TEST_CTL_U1,
 	PLL_OFF_STATUS,
 	PLL_OFF_OPMODE,
 	PLL_OFF_FRAC,

@@ -94,10 +96,13 @@ struct alpha_pll_config {
 	u32 alpha_hi;
 	u32 config_ctl_val;
 	u32 config_ctl_hi_val;
+	u32 config_ctl_hi1_val;
 	u32 user_ctl_val;
 	u32 user_ctl_hi_val;
+	u32 user_ctl_hi1_val;
 	u32 test_ctl_val;
 	u32 test_ctl_hi_val;
+	u32 test_ctl_hi1_val;
 	u32 main_output_mask;
 	u32 aux_output_mask;
 	u32 aux2_output_mask;

@@ -123,10 +128,17 @@ extern const struct clk_ops clk_alpha_pll_fabia_ops;
 extern const struct clk_ops clk_alpha_pll_fixed_fabia_ops;
 extern const struct clk_ops clk_alpha_pll_postdiv_fabia_ops;
 
+extern const struct clk_ops clk_alpha_pll_lucid_ops;
+extern const struct clk_ops clk_alpha_pll_fixed_lucid_ops;
+extern const struct clk_ops clk_alpha_pll_postdiv_lucid_ops;
+
 void clk_alpha_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 			     const struct alpha_pll_config *config);
 void clk_fabia_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
 				const struct alpha_pll_config *config);
+void clk_lucid_pll_configure(struct clk_alpha_pll *pll, struct regmap *regmap,
+			     const struct alpha_pll_config *config);
+
 extern const struct clk_ops clk_trion_fixed_pll_ops;
 extern const struct clk_ops clk_trion_pll_postdiv_ops;
Signature · 1 line
2.24.1
author
#7 lore raw

PATCH v4 4/5 dt-bindings: clock: Add SM8250 GCC clock bindings

In reply to Vinod Koul

From: Taniya Das <[email protected]>

Add device tree bindings for global clock controller on SM8250 SoCs.

Signed-off-by Taniya Das <[email protected]>
Signed-off-by Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by Vinod Koul <[email protected]>
---
 .../bindings/clock/qcom,gcc-sm8250.yaml       |  72 +++++
 include/dt-bindings/clock/qcom,gcc-sm8250.h   | 271 ++++++++++++++++++
 2 files changed, 343 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
 create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h
Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml new file +72 -0
new file mode 100644
index 000000000000..2c40a8aa9815
@@ -0,0 +1,72 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/clock/qcom,gcc-sm8250.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Global Clock & Reset Controller Binding for SM8250
+
+maintainers:
+  - Stephen Boyd <[email protected]>
+  - Taniya Das <[email protected]>
+
+description: |
+  Qualcomm global clock control module which supports the clocks, resets and
+  power domains on SM8250.
+
+  See also:
+  - dt-bindings/clock/qcom,gcc-sm8250.h
+
+properties:
+  compatible:
+    const: qcom,gcc-sm8250
+
+  clocks:
+    items:
+      - description: Board XO source
+      - description: Sleep clock source
+
+  clock-names:
+    items:
+      - const: bi_tcxo
+      - const: sleep_clk
+
+  '#clock-cells':
+    const: 1
+
+  '#reset-cells':
+    const: 1
+
+  '#power-domain-cells':
+    const: 1
+
+  reg:
+    maxItems: 1
+
+  protected-clocks:
+    description:
+      Protected clock specifier list as per common clock binding.
+
+required:
+  - compatible
+  - clocks
+  - clock-names
+  - reg
+  - '#clock-cells'
+  - '#reset-cells'
+  - '#power-domain-cells'
+
+examples:
+  - |
+    #include <dt-bindings/clock/qcom,rpmh.h>
+    clock-controller@100000 {
+      compatible = "qcom,gcc-sm8250";
+      reg = <0 0x00100000 0 0x1f0000>;
+      clocks = <&rpmhcc RPMH_CXO_CLK>,
+               <&sleep_clk>;
+      clock-names = "bi_tcxo", "sleep_clk";
+      #clock-cells = <1>;
+      #reset-cells = <1>;
+      #power-domain-cells = <1>;
+    };
+...
include/dt-bindings/clock/qcom,gcc-sm8250.h new file +271 -0

271 lines not on this page · raw message

Signature · 1 line
2.24.1
maintainer Reviewed-by on v4 4/5
#8 lore raw

Re: [PATCH v4 4/5] dt-bindings: clock: Add SM8250 GCC clock bindings

Quoted 7 lines · Vinod Koul

From: Taniya Das <[email protected]>

Add device tree bindings for global clock controller on SM8250 SoCs.

Signed-off-by Taniya Das <[email protected]>
Signed-off-by Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by Vinod Koul <[email protected]>
Quoted 6 lines
---
 .../bindings/clock/qcom,gcc-sm8250.yaml       |  72 +++++
 include/dt-bindings/clock/qcom,gcc-sm8250.h   | 271 ++++++++++++++++++
 2 files changed, 343 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml
 create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h
Reviewed-by Rob Herring <[email protected]>
author
#10 lore raw

PATCH v4 5/5 clk: qcom: gcc: Add global clock controller driver for SM8250

In reply to Vinod Koul

From: Taniya Das <[email protected]>

Add the clocks supported in global clock controller, which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them.

Signed-off-by Taniya Das <[email protected]>
Signed-off-by Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by Vinod Koul <[email protected]>
---
 drivers/clk/qcom/Kconfig      |    7 +
 drivers/clk/qcom/Makefile     |    1 +
 drivers/clk/qcom/gcc-sm8250.c | 3690 +++++++++++++++++++++++++++++++++
 3 files changed, 3698 insertions(+)
 create mode 100644 drivers/clk/qcom/gcc-sm8250.c
drivers/clk/qcom/Kconfig +7 -0
index 15cdcdc9b3b8..af406a7c4aca 100644
@@ -366,6 +366,13 @@ config SM_GCC_8150
 	  Say Y if you want to use peripheral devices such as UART,
 	  SPI, I2C, USB, SD/UFS, PCIe etc.
 
+config SM_GCC_8250
+	tristate "SM8250 Global Clock Controller"
+	help
+	  Support for the global clock controller on SM8250 devices.
+	  Say Y if you want to use peripheral devices such as UART,
+	  SPI, I2C, USB, SD/UFS, PCIe etc.
+
 config SPMI_PMIC_CLKDIV
 	tristate "SPMI PMIC clkdiv Support"
 	depends on SPMI || COMPILE_TEST
drivers/clk/qcom/Makefile +1 -0
index 656a87e629d4..bd6556b829c0 100644
@@ -59,6 +59,7 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
 obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
+obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
 obj-$(CONFIG_SPMI_PMIC_CLKDIV) += clk-spmi-pmic-div.o
 obj-$(CONFIG_KPSS_XCC) += kpss-xcc.o
 obj-$(CONFIG_QCOM_HFPLL) += hfpll.o
drivers/clk/qcom/gcc-sm8250.c new file +3690 -0

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maintainer Applied
#11 lore raw

Re: [PATCH v4 5/5] clk: qcom: gcc: Add global clock controller driver for SM8250

Quoting Vinod Koul (2020-02-23 20:50:03)

Quoted 10 lines

From: Taniya Das <[email protected]>

Add the clocks supported in global clock controller, which clock the peripherals like BLSPs, SDCC, USB, MDSS etc. Register all the clocks to the clock framework for the clients to be able to request for them.

Signed-off-by Taniya Das <[email protected]>
Signed-off-by Venkata Narendra Kumar Gutta <[email protected]>
Signed-off-by Vinod Koul <[email protected]>

---

Applied to clk-next

Reviewed-by Tested-by on the v4 series
#12 lore raw
In reply to Vinod Koul
Quoted 34 lines · Vinod Koul

This series adds clock drivers support for SM8250 SoC. As part of the device tree, the sm8250 dts file has basic nodes like CPU, PSCI, intc, timer and clock controller.

Required clock controller driver and RPMH cloks are added to support peripherals like USB.

All this configuration is added to support SM8250 to boot up to the serial console.

Changes in v4:
- Make qcom,gcc-sm8250.yaml license as dual GPL + BSD

Changes in v3:
- Dropped accepted patches by Steve
- Split the common rename patch to rename and refactor patches
- Rebase on clk/clk-qcom and move yaml binding to .../bindings/clock/qcom,gcc-sm8250.yaml
- Fix comments form Steve on gcc-sm8250 clk driver

Taniya Das (5):
clk: qcom: clk-alpha-pll: Use common names for defines
clk: qcom: clk-alpha-pll: Refactor trion PLL
clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs
dt-bindings: clock: Add SM8250 GCC clock bindings
clk: qcom: gcc: Add global clock controller driver for SM8250

  .../bindings/clock/qcom,gcc-sm8250.yaml       |   72 +
  drivers/clk/qcom/Kconfig                      |    7 +
  drivers/clk/qcom/Makefile                     |    1 +
  drivers/clk/qcom/clk-alpha-pll.c              |  264 +-
  drivers/clk/qcom/clk-alpha-pll.h              |   12 +
  drivers/clk/qcom/gcc-sm8250.c                 | 3690 +++++++++++++++++
  include/dt-bindings/clock/qcom,gcc-sm8250.h   |  271 ++
  7 files changed, 4268 insertions(+), 49 deletions(-)
Quoted 4 lines

create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml create mode 100644 drivers/clk/qcom/gcc-sm8250.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h

Reviewed-by Bryan O'Donoghue <[email protected]>
Tested-by Bryan O'Donoghue <[email protected]>
Reviewed-by Tested-by on the v4 series
#13 lore raw
In reply to Vinod Koul
Quoted 34 lines · Vinod Koul

This series adds clock drivers support for SM8250 SoC. As part of the device tree, the sm8250 dts file has basic nodes like CPU, PSCI, intc, timer and clock controller.

Required clock controller driver and RPMH cloks are added to support peripherals like USB.

All this configuration is added to support SM8250 to boot up to the serial console.

Changes in v4:
- Make qcom,gcc-sm8250.yaml license as dual GPL + BSD

Changes in v3:
- Dropped accepted patches by Steve
- Split the common rename patch to rename and refactor patches
- Rebase on clk/clk-qcom and move yaml binding to .../bindings/clock/qcom,gcc-sm8250.yaml
- Fix comments form Steve on gcc-sm8250 clk driver

Taniya Das (5):
clk: qcom: clk-alpha-pll: Use common names for defines
clk: qcom: clk-alpha-pll: Refactor trion PLL
clk: qcom: clk-alpha-pll: Add support for controlling Lucid PLLs
dt-bindings: clock: Add SM8250 GCC clock bindings
clk: qcom: gcc: Add global clock controller driver for SM8250

  .../bindings/clock/qcom,gcc-sm8250.yaml       |   72 +
  drivers/clk/qcom/Kconfig                      |    7 +
  drivers/clk/qcom/Makefile                     |    1 +
  drivers/clk/qcom/clk-alpha-pll.c              |  264 +-
  drivers/clk/qcom/clk-alpha-pll.h              |   12 +
  drivers/clk/qcom/gcc-sm8250.c                 | 3690 +++++++++++++++++
  include/dt-bindings/clock/qcom,gcc-sm8250.h   |  271 ++
  7 files changed, 4268 insertions(+), 49 deletions(-)
Quoted 4 lines

create mode 100644 Documentation/devicetree/bindings/clock/qcom,gcc-sm8250.yaml create mode 100644 drivers/clk/qcom/gcc-sm8250.c
create mode 100644 include/dt-bindings/clock/qcom,gcc-sm8250.h

Resend from the right email address.

For the series:

Reviewed-by Bryan O'Donoghue <[email protected]>
Tested-by Bryan O'Donoghue <[email protected]>