ARM: dts: rainier: Set PCA9552 pin types
Subsystems (2)
PATCH v2 1/1 ARM: dts: rainier: Set PCA9552 pin types
All 16 pins of the PCA9552 at 7-bit address 0x61 should be set as type GPIO.
Signed-off-by Matthew Barth <[email protected]>
---
v2: Added leds-pca955x.h include
Added upstream to patch
---
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)
arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +17 -0
@@ -4,6 +4,7 @@ #include "aspeed-g6.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> / { model = "Rainier";
@@ -351,66 +352,82 @@ gpio at 0 { reg = <0>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 1 { reg = <1>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 2 { reg = <2>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 3 { reg = <3>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 4 { reg = <4>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 5 { reg = <5>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 6 { reg = <6>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 7 { reg = <7>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 8 { reg = <8>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 9 { reg = <9>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 10 { reg = <10>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 11 { reg = <11>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 12 { reg = <12>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 13 { reg = <13>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 14 { reg = <14>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 15 { reg = <15>; + type = <PCA955X_TYPE_GPIO>; }; };
Signature · 1 line
2.24.1
Quoted 4 lines · Matthew Barth
All 16 pins of the PCA9552 at 7-bit address
0x61should be set as type GPIO.Signed-off-by Matthew Barth <[email protected]>
Reviewed-by Eddie James <[email protected]>
Quoted 103 lines
---
v2: Addedleds-pca955x.hinclude
Added upstream to patch
------ arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +17
-0@@ -4,6 +4,7 @@ #include "aspeed-g6.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> / { model = "Rainier";@@ -351,66 +352,82 @@ gpio at 0 { reg = <0>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 1 { reg = <1>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 2 { reg = <2>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 3 { reg = <3>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 4 { reg = <4>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 5 { reg = <5>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 6 { reg = <6>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 7 { reg = <7>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 8 { reg = <8>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 9 { reg = <9>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 10 { reg = <10>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 11 { reg = <11>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 12 { reg = <12>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 13 { reg = <13>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 14 { reg = <14>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 15 { reg = <15>; + type = <PCA955X_TYPE_GPIO>; }; };
Quoted 8 lines · Matthew Barth
All 16 pins of the PCA9552 at 7-bit address
0x61should be set as type GPIO.Signed-off-by Matthew Barth <[email protected]>---
v2: Addedleds-pca955x.hinclude
Added upstream to patch
---
Reviewed-by Brandon Wyman <[email protected]>
Quoted 99 lines
--- arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts | 17 +++++++++++++++++ 1 file changed, 17 insertions(+)arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts +17
-0@@ -4,6 +4,7 @@ #include "aspeed-g6.dtsi" #include <dt-bindings/gpio/aspeed-gpio.h> +#include <dt-bindings/leds/leds-pca955x.h> / { model = "Rainier";@@ -351,66 +352,82 @@ gpio at 0 { reg = <0>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 1 { reg = <1>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 2 { reg = <2>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 3 { reg = <3>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 4 { reg = <4>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 5 { reg = <5>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 6 { reg = <6>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 7 { reg = <7>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 8 { reg = <8>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 9 { reg = <9>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 10 { reg = <10>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 11 { reg = <11>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 12 { reg = <12>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 13 { reg = <13>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 14 { reg = <14>; + type = <PCA955X_TYPE_GPIO>; }; gpio at 15 { reg = <15>; + type = <PCA955X_TYPE_GPIO>; }; };