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Add OSM L3 Interconnect Provider

PATCH In review Sibi Sankar 3 participants 15 messages Feb 27, 2020 – Mar 4, 2020

Subsystems (5)
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Sibi Sankar

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#0 lore raw

v5 cover Add OSM L3 Interconnect Provider

This patch series aims to add Operating State Manager (OSM) L3 interconnect provider support on SDM845 and SC7180 SoCs to handle bandwidth requests from CPU to scale L3 caches.

V5:
* addressed misc review comments from Georgi
* allow icc node ids to be used across multiple providers
* picked up Rob's R-b and Ack

V4:
* add SC7180 support
* use icc_std_aggregate
* use icc_nodes_remove
* fixup Evan's review comments.

v3:
* switched the dt-bindings to dual-license
* rebased to linux-next

v2:
* addressed review comments from Evan
* dropped unused gpu icc node on SDM845 SoC

Depends on:
SDM845 icc refactor: https://patchwork.kernel.org/cover/11372211/
SC7180 icc support: https://patchwork.kernel.org/cover/11404167/

Sibi Sankar (7):
interconnect: qcom: Allow icc node to be used across icc providers
dt-bindings: interconnect: Add OSM L3 DT bindings
interconnect: qcom: Add OSM L3 interconnect provider support
dt-bindings: interconnect: Add OSM L3 DT binding on SC7180
interconnect: qcom: Add OSM L3 support on SC7180
arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider
arm64: dts: qcom: sc7180: Add OSM L3 interconnect provider

 .../bindings/interconnect/qcom,osm-l3.yaml    |  62 ++++
 arch/arm64/boot/dts/qcom/sc7180.dtsi          |  11 +
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |  11 +
 drivers/interconnect/qcom/Kconfig             |   7 +
 drivers/interconnect/qcom/Makefile            |   2 +
 drivers/interconnect/qcom/osm-l3.c            | 276 ++++++++++++++++++
 drivers/interconnect/qcom/sc7180.h            |   2 +
 drivers/interconnect/qcom/sdm845.c            | 134 +--------
 drivers/interconnect/qcom/sdm845.h            | 142 +++++++++
 .../dt-bindings/interconnect/qcom,osm-l3.h    |  12 +
 10 files changed, 526 insertions(+), 133 deletions(-)
 create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
 create mode 100644 drivers/interconnect/qcom/osm-l3.c
 create mode 100644 drivers/interconnect/qcom/sdm845.h
 create mode 100644 include/dt-bindings/interconnect/qcom,osm-l3.h
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#1 lore raw

PATCH v5 1/7 interconnect: qcom: Allow icc node to be used across icc providers

Move the icc node ids to a common header, this will allow for referencing/linking of icc nodes to multiple icc providers on SDM845 SoCs.

Signed-off-by Sibi Sankar <[email protected]>
---
 drivers/interconnect/qcom/sdm845.c | 134 +--------------------------
 drivers/interconnect/qcom/sdm845.h | 140 +++++++++++++++++++++++++++++
 2 files changed, 141 insertions(+), 133 deletions(-)
 create mode 100644 drivers/interconnect/qcom/sdm845.h
drivers/interconnect/qcom/sdm845.c +1 -133
index ab968afeee594..b013b80caa452 100644
@@ -13,139 +13,7 @@
 
 #include "bcm-voter.h"
 #include "icc-rpmh.h"
-
-enum {
-	SDM845_MASTER_A1NOC_CFG = 1,
-	SDM845_MASTER_BLSP_1,
-	SDM845_MASTER_TSIF,
-	SDM845_MASTER_SDCC_2,
-	SDM845_MASTER_SDCC_4,
-	SDM845_MASTER_UFS_CARD,
-	SDM845_MASTER_UFS_MEM,
-	SDM845_MASTER_PCIE_0,
-	SDM845_MASTER_A2NOC_CFG,
-	SDM845_MASTER_QDSS_BAM,
-	SDM845_MASTER_BLSP_2,
-	SDM845_MASTER_CNOC_A2NOC,
-	SDM845_MASTER_CRYPTO,
-	SDM845_MASTER_IPA,
-	SDM845_MASTER_PCIE_1,
-	SDM845_MASTER_QDSS_ETR,
-	SDM845_MASTER_USB3_0,
-	SDM845_MASTER_USB3_1,
-	SDM845_MASTER_CAMNOC_HF0_UNCOMP,
-	SDM845_MASTER_CAMNOC_HF1_UNCOMP,
-	SDM845_MASTER_CAMNOC_SF_UNCOMP,
-	SDM845_MASTER_SPDM,
-	SDM845_MASTER_TIC,
-	SDM845_MASTER_SNOC_CNOC,
-	SDM845_MASTER_QDSS_DAP,
-	SDM845_MASTER_CNOC_DC_NOC,
-	SDM845_MASTER_APPSS_PROC,
-	SDM845_MASTER_GNOC_CFG,
-	SDM845_MASTER_LLCC,
-	SDM845_MASTER_TCU_0,
-	SDM845_MASTER_MEM_NOC_CFG,
-	SDM845_MASTER_GNOC_MEM_NOC,
-	SDM845_MASTER_MNOC_HF_MEM_NOC,
-	SDM845_MASTER_MNOC_SF_MEM_NOC,
-	SDM845_MASTER_SNOC_GC_MEM_NOC,
-	SDM845_MASTER_SNOC_SF_MEM_NOC,
-	SDM845_MASTER_GFX3D,
-	SDM845_MASTER_CNOC_MNOC_CFG,
-	SDM845_MASTER_CAMNOC_HF0,
-	SDM845_MASTER_CAMNOC_HF1,
-	SDM845_MASTER_CAMNOC_SF,
-	SDM845_MASTER_MDP0,
-	SDM845_MASTER_MDP1,
-	SDM845_MASTER_ROTATOR,
-	SDM845_MASTER_VIDEO_P0,
-	SDM845_MASTER_VIDEO_P1,
-	SDM845_MASTER_VIDEO_PROC,
-	SDM845_MASTER_SNOC_CFG,
-	SDM845_MASTER_A1NOC_SNOC,
-	SDM845_MASTER_A2NOC_SNOC,
-	SDM845_MASTER_GNOC_SNOC,
-	SDM845_MASTER_MEM_NOC_SNOC,
-	SDM845_MASTER_ANOC_PCIE_SNOC,
-	SDM845_MASTER_PIMEM,
-	SDM845_MASTER_GIC,
-	SDM845_SLAVE_A1NOC_SNOC,
-	SDM845_SLAVE_SERVICE_A1NOC,
-	SDM845_SLAVE_ANOC_PCIE_A1NOC_SNOC,
-	SDM845_SLAVE_A2NOC_SNOC,
-	SDM845_SLAVE_ANOC_PCIE_SNOC,
-	SDM845_SLAVE_SERVICE_A2NOC,
-	SDM845_SLAVE_CAMNOC_UNCOMP,
-	SDM845_SLAVE_A1NOC_CFG,
-	SDM845_SLAVE_A2NOC_CFG,
-	SDM845_SLAVE_AOP,
-	SDM845_SLAVE_AOSS,
-	SDM845_SLAVE_CAMERA_CFG,
-	SDM845_SLAVE_CLK_CTL,
-	SDM845_SLAVE_CDSP_CFG,
-	SDM845_SLAVE_RBCPR_CX_CFG,
-	SDM845_SLAVE_CRYPTO_0_CFG,
-	SDM845_SLAVE_DCC_CFG,
-	SDM845_SLAVE_CNOC_DDRSS,
-	SDM845_SLAVE_DISPLAY_CFG,
-	SDM845_SLAVE_GLM,
-	SDM845_SLAVE_GFX3D_CFG,
-	SDM845_SLAVE_IMEM_CFG,
-	SDM845_SLAVE_IPA_CFG,
-	SDM845_SLAVE_CNOC_MNOC_CFG,
-	SDM845_SLAVE_PCIE_0_CFG,
-	SDM845_SLAVE_PCIE_1_CFG,
-	SDM845_SLAVE_PDM,
-	SDM845_SLAVE_SOUTH_PHY_CFG,
-	SDM845_SLAVE_PIMEM_CFG,
-	SDM845_SLAVE_PRNG,
-	SDM845_SLAVE_QDSS_CFG,
-	SDM845_SLAVE_BLSP_2,
-	SDM845_SLAVE_BLSP_1,
-	SDM845_SLAVE_SDCC_2,
-	SDM845_SLAVE_SDCC_4,
-	SDM845_SLAVE_SNOC_CFG,
-	SDM845_SLAVE_SPDM_WRAPPER,
-	SDM845_SLAVE_SPSS_CFG,
-	SDM845_SLAVE_TCSR,
-	SDM845_SLAVE_TLMM_NORTH,
-	SDM845_SLAVE_TLMM_SOUTH,
-	SDM845_SLAVE_TSIF,
-	SDM845_SLAVE_UFS_CARD_CFG,
-	SDM845_SLAVE_UFS_MEM_CFG,
-	SDM845_SLAVE_USB3_0,
-	SDM845_SLAVE_USB3_1,
-	SDM845_SLAVE_VENUS_CFG,
-	SDM845_SLAVE_VSENSE_CTRL_CFG,
-	SDM845_SLAVE_CNOC_A2NOC,
-	SDM845_SLAVE_SERVICE_CNOC,
-	SDM845_SLAVE_LLCC_CFG,
-	SDM845_SLAVE_MEM_NOC_CFG,
-	SDM845_SLAVE_GNOC_SNOC,
-	SDM845_SLAVE_GNOC_MEM_NOC,
-	SDM845_SLAVE_SERVICE_GNOC,
-	SDM845_SLAVE_EBI1,
-	SDM845_SLAVE_MSS_PROC_MS_MPU_CFG,
-	SDM845_SLAVE_MEM_NOC_GNOC,
-	SDM845_SLAVE_LLCC,
-	SDM845_SLAVE_MEM_NOC_SNOC,
-	SDM845_SLAVE_SERVICE_MEM_NOC,
-	SDM845_SLAVE_MNOC_SF_MEM_NOC,
-	SDM845_SLAVE_MNOC_HF_MEM_NOC,
-	SDM845_SLAVE_SERVICE_MNOC,
-	SDM845_SLAVE_APPSS,
-	SDM845_SLAVE_SNOC_CNOC,
-	SDM845_SLAVE_SNOC_MEM_NOC_GC,
-	SDM845_SLAVE_SNOC_MEM_NOC_SF,
-	SDM845_SLAVE_IMEM,
-	SDM845_SLAVE_PCIE_0,
-	SDM845_SLAVE_PCIE_1,
-	SDM845_SLAVE_PIMEM,
-	SDM845_SLAVE_SERVICE_SNOC,
-	SDM845_SLAVE_QDSS_STM,
-	SDM845_SLAVE_TCU
-};
+#include "sdm845.h"
 
 DEFINE_QNODE(qhm_a1noc_cfg, SDM845_MASTER_A1NOC_CFG, 1, 4, SDM845_SLAVE_SERVICE_A1NOC);
 DEFINE_QNODE(qhm_qup1, SDM845_MASTER_BLSP_1, 1, 4, SDM845_SLAVE_A1NOC_SNOC);
drivers/interconnect/qcom/sdm845.h new file +140 -0

140 lines not on this page · raw message

Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#3 lore raw

PATCH v5 2/7 dt-bindings: interconnect: Add OSM L3 DT bindings

In reply to Sibi Sankar

Add bindings for Operating State Manager (OSM) L3 interconnect provider on SDM845 SoCs.

Reviewed-by Rob Herring <[email protected]>
Signed-off-by Sibi Sankar <[email protected]>
---
 .../bindings/interconnect/qcom,osm-l3.yaml    | 61 +++++++++++++++++++
 .../dt-bindings/interconnect/qcom,osm-l3.h    | 12 ++++
 2 files changed, 73 insertions(+)
 create mode 100644 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml
 create mode 100644 include/dt-bindings/interconnect/qcom,osm-l3.h
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml new file +61 -0
new file mode 100644
index 0000000000000..b4d46a1e92573
@@ -0,0 +1,61 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/interconnect/qcom,osm-l3.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: Qualcomm Operating State Manager (OSM) L3 Interconnect Provider
+
+maintainers:
+  - Sibi Sankar <[email protected]>
+
+description:
+  L3 cache bandwidth requirements on Qualcomm SoCs is serviced by the OSM.
+  The OSM L3 interconnect provider aggregates the L3 bandwidth requests
+  from CPU/GPU and relays it to the OSM.
+
+properties:
+  compatible:
+    enum:
+      - qcom,sdm845-osm-l3
+
+  reg:
+    maxItems: 1
+
+  clocks:
+    items:
+      - description: xo clock
+      - description: alternate clock
+
+  clock-names:
+    items:
+      - const: xo
+      - const: alternate
+
+  '#interconnect-cells':
+    const: 1
+
+required:
+  - compatible
+  - reg
+  - clocks
+  - clock-names
+  - '#interconnect-cells'
+
+additionalProperties: false
+
+examples:
+  - |
+
+    #define GPLL0               165
+    #define RPMH_CXO_CLK        0
+
+    osm_l3: interconnect@17d41000 {
+      compatible = "qcom,sdm845-osm-l3";
+      reg = <0x17d41000 0x1400>;
+
+      clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+      clock-names = "xo", "alternate";
+
+      #interconnect-cells = <1>;
+    };
include/dt-bindings/interconnect/qcom,osm-l3.h new file +12 -0
new file mode 100644
index 0000000000000..54858ff7674d7
@@ -0,0 +1,12 @@
+/* SPDX-License-Identifier: GPL-2.0 */
+/*
+ * Copyright (C) 2019 The Linux Foundation. All rights reserved.
+ */
+
+#ifndef __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
+#define __DT_BINDINGS_INTERCONNECT_QCOM_OSM_L3_H
+
+#define MASTER_OSM_L3_APPS	0
+#define SLAVE_OSM_L3		1
+
+#endif
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#4 lore raw

PATCH v5 3/7 interconnect: qcom: Add OSM L3 interconnect provider support

In reply to Sibi Sankar

On some Qualcomm SoCs, Operating State Manager (OSM) controls the resources of scaling L3 caches. Add a driver to handle bandwidth requests to OSM L3 from CPU on SDM845 SoCs.

Signed-off-by Sibi Sankar <[email protected]>
---
 drivers/interconnect/qcom/Kconfig  |   7 +
 drivers/interconnect/qcom/Makefile |   2 +
 drivers/interconnect/qcom/osm-l3.c | 261 +++++++++++++++++++++++++++++
 drivers/interconnect/qcom/sdm845.h |   2 +
 4 files changed, 272 insertions(+)
 create mode 100644 drivers/interconnect/qcom/osm-l3.c
drivers/interconnect/qcom/Kconfig +7 -0
index c8e74b0038c49..35402376427f4 100644
@@ -28,6 +28,13 @@ config INTERCONNECT_QCOM_MSM8974
 	 This is a driver for the Qualcomm Network-on-Chip on msm8974-based
 	 platforms.
 
+config INTERCONNECT_QCOM_OSM_L3
+	tristate "Qualcomm OSM L3 interconnect driver"
+	depends on INTERCONNECT_QCOM || COMPILE_TEST
+	help
+	  Say y here to support the Operating State Manager (OSM) interconnect
+	  driver which controls the scaling of L3 caches on Qualcomm SoCs.
+
 config INTERCONNECT_QCOM_QCS404
 	tristate "Qualcomm QCS404 interconnect driver"
 	depends on INTERCONNECT_QCOM
drivers/interconnect/qcom/Makefile +2 -0
index 532555812ef61..3a047fe6e45a2 100644
@@ -3,6 +3,7 @@
 icc-bcm-voter-objs			:= bcm-voter.o
 qnoc-msm8916-objs			:= msm8916.o
 qnoc-msm8974-objs			:= msm8974.o
+icc-osm-l3-objs				:= osm-l3.o
 qnoc-qcs404-objs			:= qcs404.o
 icc-rpmh-obj				:= icc-rpmh.o
 qnoc-sc7180-objs			:= sc7180.o

@@ -12,6 +13,7 @@ icc-smd-rpm-objs			:= smd-rpm.o
 obj-$(CONFIG_INTERCONNECT_QCOM_BCM_VOTER) += icc-bcm-voter.o
 obj-$(CONFIG_INTERCONNECT_QCOM_MSM8916) += qnoc-msm8916.o
 obj-$(CONFIG_INTERCONNECT_QCOM_MSM8974) += qnoc-msm8974.o
+obj-$(CONFIG_INTERCONNECT_QCOM_OSM_L3) += icc-osm-l3.o
 obj-$(CONFIG_INTERCONNECT_QCOM_QCS404) += qnoc-qcs404.o
 obj-$(CONFIG_INTERCONNECT_QCOM_RPMH) += icc-rpmh.o
 obj-$(CONFIG_INTERCONNECT_QCOM_SC7180) += qnoc-sc7180.o
drivers/interconnect/qcom/osm-l3.c new file +261 -0

261 lines not on this page · raw message

drivers/interconnect/qcom/sdm845.h +2 -0
index bc7e425ce9852..776e9c2acb278 100644
@@ -136,5 +136,7 @@
 #define SDM845_SLAVE_SERVICE_SNOC			128
 #define SDM845_SLAVE_QDSS_STM				129
 #define SDM845_SLAVE_TCU				130
+#define SDM845_MASTER_OSM_L3_APPS			131
+#define SDM845_SLAVE_OSM_L3				132
 
 #endif /* __DRIVERS_INTERCONNECT_QCOM_SDM845_H__ */
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
Reviewed-by on v5 3/7
#5 lore raw

Re: [PATCH v5 3/7] interconnect: qcom: Add OSM L3 interconnect provider support

Quoted 6 lines · Sibi Sankar

On some Qualcomm SoCs, Operating State Manager (OSM) controls the resources of scaling L3 caches. Add a driver to handle bandwidth requests to OSM L3 from CPU on SDM845 SoCs.

Signed-off-by Sibi Sankar <[email protected]>
Reviewed-by Evan Green <[email protected]>
author
#6 lore raw

PATCH v5 4/7 dt-bindings: interconnect: Add OSM L3 DT binding on SC7180

In reply to Sibi Sankar

Add OSM L3 interconnect provider binding on SC7180 SoCs.

Acked-by Rob Herring <[email protected]>
Signed-off-by Sibi Sankar <[email protected]>
---
 Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml | 1 +
 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/interconnect/qcom,osm-l3.yaml +1 -0
index b4d46a1e92573..91f70c9067d12 100644
@@ -17,6 +17,7 @@ description:
 properties:
   compatible:
     enum:
+      - qcom,sc7180-osm-l3
       - qcom,sdm845-osm-l3
 
   reg:
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#7 lore raw

PATCH v5 5/7 interconnect: qcom: Add OSM L3 support on SC7180

In reply to Sibi Sankar

Add Operating State Manager (OSM) L3 interconnect provider support on SC7180 SoCs.

Signed-off-by Sibi Sankar <[email protected]>
---
 drivers/interconnect/qcom/osm-l3.c | 15 +++++++++++++++
 drivers/interconnect/qcom/sc7180.h |  2 ++
 2 files changed, 17 insertions(+)
drivers/interconnect/qcom/osm-l3.c +15 -0
index bbf8133195972..a03c6d6833dfc 100644
@@ -14,6 +14,7 @@
 
 #include <dt-bindings/interconnect/qcom,osm-l3.h>
 
+#include "sc7180.h"
 #include "sdm845.h"
 
 #define LUT_MAX_ENTRIES			40U

@@ -82,6 +83,19 @@ const static struct qcom_icc_desc sdm845_icc_osm_l3 = {
 	.num_nodes = ARRAY_SIZE(sdm845_osm_l3_nodes),
 };
 
+DEFINE_QNODE(sc7180_osm_apps_l3, SC7180_MASTER_OSM_L3_APPS, 16, SC7180_SLAVE_OSM_L3);
+DEFINE_QNODE(sc7180_osm_l3, SC7180_SLAVE_OSM_L3, 16);
+
+static struct qcom_icc_node *sc7180_osm_l3_nodes[] = {
+	[MASTER_OSM_L3_APPS] = &sc7180_osm_apps_l3,
+	[SLAVE_OSM_L3] = &sc7180_osm_l3,
+};
+
+const static struct qcom_icc_desc sc7180_icc_osm_l3 = {
+	.nodes = sc7180_osm_l3_nodes,
+	.num_nodes = ARRAY_SIZE(sc7180_osm_l3_nodes),
+};
+
 static int qcom_icc_set(struct icc_node *src, struct icc_node *dst)
 {
 	struct qcom_osm_l3_icc_provider *qp;

@@ -242,6 +256,7 @@ static int qcom_osm_l3_probe(struct platform_device *pdev)
 }
 
 static const struct of_device_id osm_l3_of_match[] = {
+	{ .compatible = "qcom,sc7180-osm-l3", .data = &sc7180_icc_osm_l3 },
 	{ .compatible = "qcom,sdm845-osm-l3", .data = &sdm845_icc_osm_l3 },
 	{ }
 };
drivers/interconnect/qcom/sc7180.h +2 -0
index c2d8388bb8809..c6212a10c2f61 100644
@@ -145,5 +145,7 @@
 #define SC7180_SLAVE_SERVICE_SNOC			134
 #define SC7180_SLAVE_QDSS_STM				135
 #define SC7180_SLAVE_TCU				136
+#define SC7180_MASTER_OSM_L3_APPS			137
+#define SC7180_SLAVE_OSM_L3				138
 
 #endif
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#9 lore raw

PATCH v5 6/7 arm64: dts: qcom: sdm845: Add OSM L3 interconnect provider

In reply to Sibi Sankar

Add Operation State Manager (OSM) L3 interconnect provider on SDM845 SoCs.

Signed-off-by Sibi Sankar <[email protected]>
---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)
arch/arm64/boot/dts/qcom/sdm845.dtsi +11 -0
index ae7d6617d8b87..8105532f6fbde 100644
@@ -11,6 +11,7 @@
 #include <dt-bindings/clock/qcom,lpass-sdm845.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
 #include <dt-bindings/clock/qcom,videocc-sdm845.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interconnect/qcom,sdm845.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy-qcom-qusb2.h>

@@ -3323,6 +3324,16 @@ frame@17d10000 {
 			};
 		};
 
+		osm_l3: interconnect@17d41000 {
+			compatible = "qcom,sdm845-osm-l3";
+			reg = <0 0x17d41000 0 0x1400>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@17d43000 {
 			compatible = "qcom,cpufreq-hw";
 			reg = <0 0x17d43000 0 0x1400>, <0 0x17d45800 0 0x1400>;
Signature · 2 lines
The Qualcomm Innovation Center, Inc. is a member of the Code Aurora Forum,
a Linux Foundation Collaborative Project
author
#12 lore raw

PATCH v5 7/7 arm64: dts: qcom: sc7180: Add OSM L3 interconnect provider

In reply to Sibi Sankar

Add Operation State Manager (OSM) L3 interconnect provider on SC7180 SoCs.

Signed-off-by Sibi Sankar <[email protected]>
---
 arch/arm64/boot/dts/qcom/sc7180.dtsi | 11 +++++++++++
 1 file changed, 11 insertions(+)
arch/arm64/boot/dts/qcom/sc7180.dtsi +11 -0
index 3e28f340fa3e6..6997467608107 100644
@@ -7,6 +7,7 @@
 
 #include <dt-bindings/clock/qcom,gcc-sc7180.h>
 #include <dt-bindings/clock/qcom,rpmh.h>
+#include <dt-bindings/interconnect/qcom,osm-l3.h>
 #include <dt-bindings/interrupt-controller/arm-gic.h>
 #include <dt-bindings/phy/phy-qcom-qusb2.h>
 #include <dt-bindings/power/qcom-aoss-qmp.h>

@@ -1578,6 +1579,16 @@ apps_bcm_voter: bcm_voter {
 			};
 		};
 
+		osm_l3: interconnect@18321000 {
+			compatible = "qcom,sc7180-osm-l3";
+			reg = <0 0x18321000 0 0x1400>;
+
+			clocks = <&rpmhcc RPMH_CXO_CLK>, <&gcc GPLL0>;
+			clock-names = "xo", "alternate";
+
+			#interconnect-cells = <1>;
+		};
+
 		cpufreq_hw: cpufreq@18323000 {
 			compatible = "qcom,cpufreq-hw";
 			reg = <0 0x18323000 0 0x1400>, <0 0x18325800 0 0x1400>;
Signature · 2 lines
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