Add support for FSYS power domain and enable suspend clk for Exynos542x SoC

Add the new compatible string for Exynos5422 DWC3 to support enable/disable of core and suspend clk by DWC3 driver.
Also updated the clock names for compatible samsung,exynos5420-dwusb3.

Acked-by Rob Herring <[email protected]>

Signed-off-by Anand Moon <[email protected]>

Hi,

Quoted 6 lines · Anand Moon

Add the new compatible string for Exynos5422 DWC3 to support enable/disable of core and suspend clk by DWC3 driver.
Also updated the clock names for compatible samsung,exynos5420-dwusb3.

Acked-by Rob Herring <[email protected]>

Signed-off-by Anand Moon <[email protected]>

What is the dependency here?

checking file Documentation/devicetree/bindings/usb/exynos-usb.txt Hunk #2 FAILED at 84.
1 out of 2 hunks FAILED

Applying on top of v5.6-rc5

--
balbi

Hi,

Anand Moon <[email protected]> writes:

Quoted 6 lines

Add the new compatible string for Exynos5422 DWC3 to support enable/disable of core and suspend clk by DWC3 driver.
Also updated the clock names for compatible samsung,exynos5420-dwusb3.

Acked-by Rob Herring <[email protected]>

Signed-off-by Anand Moon <[email protected]>

What is the dependency here?

Add new compatible strings for USBDRD3 for adding missing suspend clk, exynos5422 usbdrd3 support two clk USBD300 and SCLK_USBD300, so add missing suspemd_clk for Exynos542x DWC3 nodes.

Signed-off-by Anand Moon <[email protected]>

---
fix the commit message

---
 arch/arm/boot/dts/exynos5410.dtsi | 8 ++++----
 arch/arm/boot/dts/exynos5420.dtsi | 8 ++++----
 arch/arm/boot/dts/exynos54xx.dtsi | 4 ++--
 3 files changed, 10 insertions(+), 10 deletions(-)

arch/arm/boot/dts/exynos5410.dtsi +4 -4

index 2eab80bf5f3a..19845dcd528f 100644
@@ -396,8 +396,8 @@ &trng {
 };
 
 &usbdrd3_0 {
-       clocks = <&clock CLK_USBD300>;
-       clock-names = "usbdrd30";
+       clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>;
+       clock-names = "usbdrd30", "usbdrd30_susp_clk";
 };
 
 &usbdrd_phy0 {

@@ -407,8 +407,8 @@ &usbdrd_phy0 {
 };
 
 &usbdrd3_1 {
-       clocks = <&clock CLK_USBD301>;
-       clock-names = "usbdrd30";
+       clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>;
+       clock-names = "usbdrd30", "usbdrd30_susp_clk";
 };
 
 &usbdrd_dwc3_1 {

arch/arm/boot/dts/exynos5420.dtsi +4 -4

index b672080e7469..bd505256a223 100644
@@ -1372,8 +1372,8 @@ &trng {
 };
 
 &usbdrd3_0 {
-       clocks = <&clock CLK_USBD300>;
-       clock-names = "usbdrd30";
+       clocks = <&clock CLK_USBD300>, <&clock CLK_SCLK_USBD300>;
+       clock-names = "usbdrd30", "usbdrd30_susp_clk";
 };
 
 &usbdrd_phy0 {

@@ -1383,8 +1383,8 @@ &usbdrd_phy0 {
 };
 
 &usbdrd3_1 {
-       clocks = <&clock CLK_USBD301>;
-       clock-names = "usbdrd30";
+       clocks = <&clock CLK_USBD301>, <&clock CLK_SCLK_USBD301>;
+       clock-names = "usbdrd30", "usbdrd30_susp_clk";
 };
 
 &usbdrd_dwc3_1 {

arch/arm/boot/dts/exynos54xx.dtsi +2 -3

index 8aa5117e58ce..0aac6255de5d 100644
@@ -143,7 +143,7 @@ hsi2c_7: i2c@12cd0000 {
                };
 
                usbdrd3_0: usb3-0 {
-                       compatible = "samsung,exynos5250-dwusb3";
+                       compatible = "samsung,exynos5420-dwusb3";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;

@@ -165,7 +165,7 @@ usbdrd_phy0: phy@12100000 {
                };
 
                usbdrd3_1: usb3-1 {
-                       compatible = "samsung,exynos5250-dwusb3";
+                       compatible = "samsung,exynos5420-dwusb3";
                        #address-cells = <1>;
                        #size-cells = <1>;
                        ranges;
--

2.25.1

Hi Krzysztof,

Quoted 6 lines · Anand Moon

Add new compatible strings for USBDRD3 for adding missing suspend clk, exynos5422 usbdrd3 support two clk USBD300 and SCLK_USBD300, so add missing suspemd_clk for Exynos542x DWC3 nodes.

Signed-off-by Anand Moon <[email protected]>

My assumption based on the FSYS clock source diagram below was bit wrong.
[0] https://imgur.com/gallery/zAiBoyh

And again re-looking into the driver source code, it turn out their are *6 clock*
Here is the correct mapping as per the Exynos5420 clock driver.

USB-(phy@12100000)
|___________________CLK_SCLK_USBD300
|___________________CLK_SCLK_USBPHY300

USB-(phy@12500000)
|___________________CLK_SCLK_USBD301
|___________________CLK_SCLK_USBPHY301

USB-(dwc3@12000000)
|___________________CLK_USBD300
USB-(dwc3@12400000)
|___________________CLK_USBD301

Note: As per Exynos 5422 user manual, There are some more USB CLK configuration missing in GATE_IP_FSYS. So we could enable another dwc3 clk, If needed I would like too add this missing clk code and enable this clk for dwc3 driver.

For some reason we already use CLK_USBD300 and CLK_USBD301
for PHY nodes, which lead to this confusion. So we need to update PHY clock CLK_USBD300 with CLK_SCLK_USBD300 and clock CLK_USBD301 with CLK_SCLK_USBD301.

Please share your thought on linking PHY nodes above and add new DWC3 clock and enable this clock.

Quoted 35 lines · Anand Moon

Hi Krzysztof,

Quoted 6 lines · Anand Moon

Add new compatible strings for USBDRD3 for adding missing suspend clk, exynos5422 usbdrd3 support two clk USBD300 and SCLK_USBD300, so add missing suspemd_clk for Exynos542x DWC3 nodes.

Signed-off-by Anand Moon <[email protected]>

My assumption based on the FSYS clock source diagram below was bit wrong.
[0] https://imgur.com/gallery/zAiBoyh

And again re-looking into the driver source code, it turn out their are *6 clock*
Here is the correct mapping as per the Exynos5420 clock driver.

USB-(phy@12100000)
|___________________CLK_SCLK_USBD300
|___________________CLK_SCLK_USBPHY300

USB-(phy@12500000)
|___________________CLK_SCLK_USBD301
|___________________CLK_SCLK_USBPHY301

USB-(dwc3@12000000)
|___________________CLK_USBD300
USB-(dwc3@12400000)
|___________________CLK_USBD301

Note: As per Exynos 5422 user manual, There are some more USB CLK configuration missing in GATE_IP_FSYS. So we could enable another dwc3 clk, If needed I would like too add this missing clk code and enable this clk for dwc3 driver.

Quoted 6 lines

For some reason we already use CLK_USBD300 and CLK_USBD301
for PHY nodes, which lead to this confusion. So we need to update PHY clock CLK_USBD300 with CLK_SCLK_USBD300 and clock CLK_USBD301 with CLK_SCLK_USBD301.

Please share your thought on linking PHY nodes above and add new DWC3 clock and enable this clock.

The real clock topology of Exynos5422 is not properly reflected in the kernel. However cleaning this up is quite big task.

Best regards,
Krzysztof

FSYS power domain support usbdrd3, pdma and usb2 power gaiting, hence move FSYS clk setting to sub-CMU block to support power domain on/off sequences for device nodes.

Signed-off-by Anand Moon <[email protected]>

---
New patch in the series

---
 drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 11 deletions(-)

drivers/clk/samsung/clk-exynos5420.c +0 -0

index c9e5a1fb6653..6c4c47dfcdce 100644

drivers/clk/samsung/clk-exynos5420.c +8 -5

 	/* FSYS Block */
 	GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
-	GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
-	GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
 	GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
 	GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
 	GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),

@@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
 	GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
 	GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
 			GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
-	GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
-	GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
-	GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
 	GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
 			SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 

@@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
 	{ DIV2_RATIO0, 0, 0x30 },	/* DIV dout_gscl_blk_300 */
 };
 
+/* USB3.0 */
+static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
+	DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
+	DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+	DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
+	DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+};
+

drivers/clk/samsung/clk-exynos5420.c +14 -0

+};
+
 static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
 	GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
 	     CLK_SET_RATE_PARENT, 0),

@@ -1376,12 +1387,23 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
 	.pd_name	= "MAU",
 };
 
+static const struct exynos5_subcmu_info exynos5x_fsys_subcmu = {
+	.div_clks       = exynos5x_fsys_div_clks,
+	.nr_div_clks    = ARRAY_SIZE(exynos5x_fsys_div_clks),
+	.gate_clks	= exynos5x_fsys_gate_clks,
+	.nr_gate_clks	= ARRAY_SIZE(exynos5x_fsys_gate_clks),
+	.suspend_regs	= exynos5x_fsys_suspend_regs,
+	.nr_suspend_regs = ARRAY_SIZE(exynos5x_fsys_suspend_regs),
+	.pd_name	= "FSYS",
+};
+
 static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
 	&exynos5x_disp_subcmu,
 	&exynos5x_gsc_subcmu,
 	&exynos5x_g3d_subcmu,
 	&exynos5x_mfc_subcmu,
 	&exynos5x_mscl_subcmu,
+	&exynos5x_fsys_subcmu,
 };
 
 static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {

@@ -1391,6 +1413,7 @@ static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
 	&exynos5x_mfc_subcmu,
 	&exynos5x_mscl_subcmu,
 	&exynos5800_mau_subcmu,
+	&exynos5x_fsys_subcmu,
 };
 
 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {

Signature · 1 line

2.25.1

Quoted 16 lines · Anand Moon

FSYS power domain support usbdrd3, pdma and usb2 power gaiting, hence move FSYS clk setting to sub-CMU block to support power domain on/off sequences for device nodes.

Signed-off-by Anand Moon <[email protected]>

---
New patch in the series

---
 drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 11 deletions(-)

drivers/clk/samsung/clk-exynos5420.c +0 -0

index c9e5a1fb6653..6c4c47dfcdce 100644

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { · line 866

Quoted 8 lines

drivers/clk/samsung/clk-exynos5420.c +0 -5

@@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
      DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
      DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 
-     /* USB3.0 */
-     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
-     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
-     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
-     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),

According to clock diagram these are still in CMU TOP, not FSYS.

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {

Quoted 5 lines

drivers/clk/samsung/clk-exynos5420.c +0 -1

-
      /* MMC */
      DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
      DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),

@@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {

/>

Quoted 34 lines

drivers/clk/samsung/clk-exynos5420.c +13 -5

      /* FSYS Block */
      GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
-     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
-     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
      GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
      GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
      GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),

@@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
      GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
      GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
                      GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
-     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
-     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
-     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
      GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
                      SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 

@@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
      { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
 };
 
+/* USB3.0 */
+static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
+     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
+     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
+     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+};
+
+static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
+     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
+     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
+     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),

drivers/clk/samsung/clk-exynos5420.c static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { · line 1267

Quoted 5 lines

drivers/clk/samsung/clk-exynos5420.c +5 -0

+     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
+};
+
+static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
+     { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */

This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which you are not suspending. They do not belong to this CMU.

Don't you need to save also parts of GATE_BUS_FSYS0?

drivers/clk/samsung/clk-exynos5420.c static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { · line 1269

Quoted 3 lines

drivers/clk/samsung/clk-exynos5420.c +2 -0

+     { SRC_TOP3, 0, BIT(24) },                 /* SW_MUX_PCLK_200_FSYS_SEL */
+     { SRC_TOP3, 0, BIT(28) },                 /* SW_MUX_ACLK_200_FSYS_SEL */

Name of clocks from the driver please, not from datasheet. Look at other examples.

Best regards,
Krzysztof

Quoted 40 lines

drivers/clk/samsung/clk-exynos5420.c +14 -1

+};
+
 static const struct samsung_gate_clock exynos5x_g3d_gate_clks[] __initconst = {
      GATE(CLK_G3D, "g3d", "mout_user_aclk_g3d", GATE_IP_G3D, 9,
           CLK_SET_RATE_PARENT, 0),

@@ -1376,12 +1387,23 @@ static const struct exynos5_subcmu_info exynos5800_mau_subcmu = {
      .pd_name        = "MAU",
 };
 
+static const struct exynos5_subcmu_info exynos5x_fsys_subcmu = {
+     .div_clks       = exynos5x_fsys_div_clks,
+     .nr_div_clks    = ARRAY_SIZE(exynos5x_fsys_div_clks),
+     .gate_clks      = exynos5x_fsys_gate_clks,
+     .nr_gate_clks   = ARRAY_SIZE(exynos5x_fsys_gate_clks),
+     .suspend_regs   = exynos5x_fsys_suspend_regs,
+     .nr_suspend_regs = ARRAY_SIZE(exynos5x_fsys_suspend_regs),
+     .pd_name        = "FSYS",
+};
+
 static const struct exynos5_subcmu_info *exynos5x_subcmus[] = {
      &exynos5x_disp_subcmu,
      &exynos5x_gsc_subcmu,
      &exynos5x_g3d_subcmu,
      &exynos5x_mfc_subcmu,
      &exynos5x_mscl_subcmu,
+     &exynos5x_fsys_subcmu,
 };
 
 static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {

@@ -1391,6 +1413,7 @@ static const struct exynos5_subcmu_info *exynos5800_subcmus[] = {
      &exynos5x_mfc_subcmu,
      &exynos5x_mscl_subcmu,
      &exynos5800_mau_subcmu,
+     &exynos5x_fsys_subcmu,
 };
 
 static const struct samsung_pll_rate_table exynos5420_pll2550x_24mhz_tbl[] __initconst = {
--

2.25.1

Hi Krzysztof,

Thanks for your review comments.

Quoted 69 lines · Krzysztof Kozlowski

Quoted 16 lines · Anand Moon

FSYS power domain support usbdrd3, pdma and usb2 power gaiting, hence move FSYS clk setting to sub-CMU block to support power domain on/off sequences for device nodes.

Signed-off-by Anand Moon <[email protected]>

---
New patch in the series

---
 drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 11 deletions(-)

drivers/clk/samsung/clk-exynos5420.c +0 -0

index c9e5a1fb6653..6c4c47dfcdce 100644

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { · line 866

Quoted 8 lines

drivers/clk/samsung/clk-exynos5420.c +0 -5

@@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
      DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
      DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 
-     /* USB3.0 */
-     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
-     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
-     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
-     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),

According to clock diagram these are still in CMU TOP, not FSYS.

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {

Quoted 5 lines

drivers/clk/samsung/clk-exynos5420.c +0 -1

-
      /* MMC */
      DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
      DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),

@@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {

/>

Quoted 34 lines

drivers/clk/samsung/clk-exynos5420.c +13 -5

      /* FSYS Block */
      GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
-     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
-     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
      GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
      GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
      GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),

@@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
      GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
      GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
                      GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
-     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
-     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
-     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
      GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
                      SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 

@@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
      { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
 };
 
+/* USB3.0 */
+static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
+     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
+     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
+     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+};
+
+static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
+     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
+     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
+     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),

Quoted 9 lines

drivers/clk/samsung/clk-exynos5420.c static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { · line 1267

Quoted 5 lines

drivers/clk/samsung/clk-exynos5420.c +5 -0

+     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
+};
+
+static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
+     { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */

This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which you are not suspending. They do not belong to this CMU.

Ok. I change the from GATE_IP_FSYS to GATE_BUS_FSYS0 in the above exynos5x_fsys_gate_clks to make this consistent to used GATE_BUS_FSYS0 for CMU, with this change it works as per previously.

Quoted 2 lines

Don't you need to save also parts of GATE_BUS_FSYS0?

GATE_BUS_FSYS0 and GATE_IP_FSYS are already part of list
of control register which are saved and restored during suspend and resume so no point in adding this here, I should drop the GATE_IP_FSYS reg dump over here.

Quoted 84 lines · Anand Moon

Hi Krzysztof,

Thanks for your review comments.

Quoted 78 lines · Krzysztof Kozlowski

Quoted 16 lines · Anand Moon

FSYS power domain support usbdrd3, pdma and usb2 power gaiting, hence move FSYS clk setting to sub-CMU block to support power domain on/off sequences for device nodes.

Signed-off-by Anand Moon <[email protected]>

---
New patch in the series

---
 drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 11 deletions(-)

drivers/clk/samsung/clk-exynos5420.c +0 -0

index c9e5a1fb6653..6c4c47dfcdce 100644

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { · line 866

Quoted 8 lines

drivers/clk/samsung/clk-exynos5420.c +0 -5

@@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
      DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
      DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 
-     /* USB3.0 */
-     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
-     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
-     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
-     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),

According to clock diagram these are still in CMU TOP, not FSYS.

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {

Quoted 5 lines

drivers/clk/samsung/clk-exynos5420.c +0 -1

-
      /* MMC */
      DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
      DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),

@@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {

/>

Quoted 29 lines

drivers/clk/samsung/clk-exynos5420.c +8 -5

      /* FSYS Block */
      GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
-     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
-     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
      GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
      GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
      GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),

@@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
      GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
      GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
                      GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
-     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
-     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
-     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
      GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
                      SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 

@@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
      { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
 };
 
+/* USB3.0 */
+static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
+     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
+     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
+     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+};
+

drivers/clk/samsung/clk-exynos5420.c static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { · line 1267

Quoted 10 lines

drivers/clk/samsung/clk-exynos5420.c +10 -0

+static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
+     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
+     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
+     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
+     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
+};
+
+static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
+     { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */

This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which you are not suspending. They do not belong to this CMU.

Quoted 3 lines

Ok. I change the from GATE_IP_FSYS to GATE_BUS_FSYS0 in the above exynos5x_fsys_gate_clks to make this consistent to used GATE_BUS_FSYS0 for CMU, with this change it works as per previously.

Wait, you should set here proper registers with proper mask.

Quoted 7 lines

Quoted 2 lines

Don't you need to save also parts of GATE_BUS_FSYS0?

GATE_BUS_FSYS0 and GATE_IP_FSYS are already part of list
of control register which are saved and restored during suspend and resume so no point in adding this here, I should drop the GATE_IP_FSYS reg dump over here.

Since registers are used in separate sub CMU devices, each should save/restore its part.

Best regards,
Krzysztof

Hi Krzysztof,

Quoted 90 lines · Krzysztof Kozlowski

Quoted 87 lines · Anand Moon

Hi Krzysztof,

Thanks for your review comments.

Quoted 69 lines · Krzysztof Kozlowski

Quoted 16 lines · Anand Moon

FSYS power domain support usbdrd3, pdma and usb2 power gaiting, hence move FSYS clk setting to sub-CMU block to support power domain on/off sequences for device nodes.

Signed-off-by Anand Moon <[email protected]>

---
New patch in the series

---
 drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 11 deletions(-)

drivers/clk/samsung/clk-exynos5420.c +0 -0

index c9e5a1fb6653..6c4c47dfcdce 100644

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { · line 866

Quoted 8 lines

drivers/clk/samsung/clk-exynos5420.c +0 -5

@@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
      DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
      DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 
-     /* USB3.0 */
-     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
-     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
-     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
-     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),

According to clock diagram these are still in CMU TOP, not FSYS.

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {

Quoted 5 lines

drivers/clk/samsung/clk-exynos5420.c +0 -1

-
      /* MMC */
      DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
      DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),

@@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {

/>

Quoted 34 lines

drivers/clk/samsung/clk-exynos5420.c +13 -5

      /* FSYS Block */
      GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
-     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
-     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
      GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
      GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
      GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),

@@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
      GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
      GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
                      GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
-     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
-     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
-     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
      GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
                      SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 

@@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
      { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
 };
 
+/* USB3.0 */
+static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
+     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
+     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
+     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+};
+
+static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
+     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
+     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
+     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),

Quoted 9 lines

drivers/clk/samsung/clk-exynos5420.c static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { · line 1267

Quoted 5 lines

drivers/clk/samsung/clk-exynos5420.c +5 -0

+     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
+};
+
+static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
+     { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */

This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which you are not suspending. They do not belong to this CMU.

Ok. I change the from GATE_IP_FSYS to GATE_BUS_FSYS0 in the above exynos5x_fsys_gate_clks to make this consistent to used GATE_BUS_FSYS0 for CMU, with this change it works as per previously.

Quoted 1 line

Wait, you should set here proper registers with proper mask.

Yes I will set the proper mask for each as per the Exynos 5422 User Manual.

Here is what I feel
CLK_GATE_BUS_FSYS0 controls the PHY clock CLK_GATE_IP_FSYS controls the IP clock.

So both these field should be part of this FSYS CMU.

Quoted 8 lines

Quoted 7 lines

Quoted 2 lines

Don't you need to save also parts of GATE_BUS_FSYS0?

GATE_BUS_FSYS0 and GATE_IP_FSYS are already part of list
of control register which are saved and restored during suspend and resume so no point in adding this here, I should drop the GATE_IP_FSYS reg dump over here.

Quoted 2 lines

Since registers are used in separate sub CMU devices, each should save/restore its part.

Ok I will add both GATE_BUS_FSYS0 and GATE_IP_FSYS reset value over here.

Hi Krzysztof,

Quoted 94 lines · Anand Moon

Hi Krzysztof,

Quoted 90 lines · Krzysztof Kozlowski

Quoted 87 lines · Anand Moon

Hi Krzysztof,

Thanks for your review comments.

Quoted 69 lines · Krzysztof Kozlowski

Quoted 16 lines · Anand Moon

FSYS power domain support usbdrd3, pdma and usb2 power gaiting, hence move FSYS clk setting to sub-CMU block to support power domain on/off sequences for device nodes.

Signed-off-by Anand Moon <[email protected]>

---
New patch in the series

---
 drivers/clk/samsung/clk-exynos5420.c | 45 +++++++++++++++++++++-------
 1 file changed, 34 insertions(+), 11 deletions(-)

drivers/clk/samsung/clk-exynos5420.c +0 -0

index c9e5a1fb6653..6c4c47dfcdce 100644

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_div_clock exynos5x_div_clks[] __initconst = { · line 866

Quoted 8 lines

drivers/clk/samsung/clk-exynos5420.c +0 -5

@@ -859,12 +859,6 @@ static const struct samsung_div_clock exynos5x_div_clks[] __initconst = {
      DIV(0, "dout_maudio0", "mout_maudio0", DIV_MAU, 20, 4),
      DIV(0, "dout_maupcm0", "dout_maudio0", DIV_MAU, 24, 8),
 
-     /* USB3.0 */
-     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
-     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
-     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
-     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),

According to clock diagram these are still in CMU TOP, not FSYS.

drivers/clk/samsung/clk-exynos5420.c static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {

Quoted 5 lines

drivers/clk/samsung/clk-exynos5420.c +0 -1

-
      /* MMC */
      DIV(0, "dout_mmc0", "mout_mmc0", DIV_FSYS1, 0, 10),
      DIV(0, "dout_mmc1", "mout_mmc1", DIV_FSYS1, 10, 10),

@@ -1031,8 +1025,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {

/>

Quoted 34 lines

drivers/clk/samsung/clk-exynos5420.c +13 -5

      /* FSYS Block */
      GATE(CLK_TSI, "tsi", "aclk200_fsys", GATE_BUS_FSYS0, 0, 0, 0),
-     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
-     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
      GATE(CLK_UFS, "ufs", "aclk200_fsys2", GATE_BUS_FSYS0, 3, 0, 0),
      GATE(CLK_RTIC, "rtic", "aclk200_fsys", GATE_IP_FSYS, 9, 0, 0),
      GATE(CLK_MMC0, "mmc0", "aclk200_fsys2", GATE_IP_FSYS, 12, 0, 0),

@@ -1040,9 +1032,6 @@ static const struct samsung_gate_clock exynos5x_gate_clks[] __initconst = {
      GATE(CLK_MMC2, "mmc2", "aclk200_fsys2", GATE_IP_FSYS, 14, 0, 0),
      GATE(CLK_SROMC, "sromc", "aclk200_fsys2",
                      GATE_IP_FSYS, 17, CLK_IGNORE_UNUSED, 0),
-     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
-     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),
-     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
      GATE(CLK_SCLK_UNIPRO, "sclk_unipro", "dout_unipro",
                      SRC_MASK_FSYS, 24, CLK_SET_RATE_PARENT, 0),
 

@@ -1258,6 +1247,28 @@ static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = {
      { DIV2_RATIO0, 0, 0x30 },       /* DIV dout_gscl_blk_300 */
 };
 
+/* USB3.0 */
+static const struct samsung_div_clock exynos5x_fsys_div_clks[] __initconst = {
+     DIV(0, "dout_usbphy301", "mout_usbd301", DIV_FSYS0, 12, 4),
+     DIV(0, "dout_usbphy300", "mout_usbd300", DIV_FSYS0, 16, 4),
+     DIV(0, "dout_usbd301", "mout_usbd301", DIV_FSYS0, 20, 4),
+     DIV(0, "dout_usbd300", "mout_usbd300", DIV_FSYS0, 24, 4),
+};
+
+static const struct samsung_gate_clock exynos5x_fsys_gate_clks[] __initconst = {
+     GATE(CLK_PDMA0, "pdma0", "aclk200_fsys", GATE_BUS_FSYS0, 1, 0, 0),
+     GATE(CLK_PDMA1, "pdma1", "aclk200_fsys", GATE_BUS_FSYS0, 2, 0, 0),
+     GATE(CLK_USBH20, "usbh20", "aclk200_fsys", GATE_IP_FSYS, 18, 0, 0),
+     GATE(CLK_USBD300, "usbd300", "aclk200_fsys", GATE_IP_FSYS, 19, 0, 0),

Quoted 9 lines

drivers/clk/samsung/clk-exynos5420.c static struct exynos5_subcmu_reg_dump exynos5x_gsc_suspend_regs[] = { · line 1267

Quoted 5 lines

drivers/clk/samsung/clk-exynos5420.c +5 -0

+     GATE(CLK_USBD301, "usbd301", "aclk200_fsys", GATE_IP_FSYS, 20, 0, 0),
+};
+
+static struct exynos5_subcmu_reg_dump exynos5x_fsys_suspend_regs[] = {
+     { GATE_IP_FSYS, 0xffffffff, 0xffffffff }, /* FSYS gates */

This looks wrong. GATE_IP_FSYS has fields also for FSYS2 clocks which you are not suspending. They do not belong to this CMU.

Ok. I change the from GATE_IP_FSYS to GATE_BUS_FSYS0 in the above exynos5x_fsys_gate_clks to make this consistent to used GATE_BUS_FSYS0 for CMU, with this change it works as per previously.

Quoted 8 lines

Quoted 1 line

Wait, you should set here proper registers with proper mask.

Yes I will set the proper mask for each as per the Exynos 5422 User Manual.

Here is what I feel
CLK_GATE_BUS_FSYS0 controls the PHY clock
CLK_GATE_IP_FSYS controls the IP clock.

Sorry I cannot register both CLK_GATE_BUS_FSYS0 and CLK_GATE_IP_FSYS to aclk200_fsys, so I got some error like below.

[    0.922693] samsung_clk_register_gate: failed to register clock usbh20
[    0.922857] samsung_clk_register_gate: failed to register clock usbd300
[    0.923000] samsung_clk_register_gate: failed to register clock usbd301

Quoted 1 line

So both these field should be part of this FSYS CMU.