1. Patch 2 is separated into two as per the comment by Boris.
2. Renamed MICRON_CFG_CONTI_READ into MICRON_CFG_CR.
3. Reworked die selection function as per the comment by Boris.

Changes since v3:
-----------------

1. Patch 3 and 4 reworked as follows
- Patch 3 introducing the Continuous read feature
- Patch 4 adding devices with the feature

Changes since v2:
-----------------

1. Patch commit messages have been modified.
2. Handled devices with Continuous Read feature with vendor specific flag.
3. Reworked die selection function as per the comment.

Changes since v1:
-----------------

1. The patch split into multiple patches.
2. Added comments for selecting the die.

Shivamurthy Shastri (6):
mtd: spinand: micron: Generalize the OOB layout structure and function
names
mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD
mtd: spinand: micron: Add new Micron SPI NAND devices
mtd: spinand: micron: identify SPI NAND device with Continuous Read
mode
mtd: spinand: micron: Add M70A series Micron SPI NAND devices
mtd: spinand: micron: Add new Micron SPI NAND devices with multiple
dies

 drivers/mtd/nand/spi/micron.c | 158 +++++++++++++++++++++++++++++++---
 include/linux/mtd/spinand.h   |   1 +
 2 files changed, 145 insertions(+), 14 deletions(-)

Signature · 1 line

2.17.1

[email protected]

author

2020-03-11 17:58 UTC #1 lore raw

PATCH v7 1/6 mtd: spinand: micron: Generalize the OOB layout structure and function names

From: Shivamurthy Shastri <[email protected]>

In order to add new Micron SPI NAND devices, we generalized the OOB layout structure and function names.

Signed-off-by Shivamurthy Shastri <[email protected]>

Reviewed-by Boris Brezillon <[email protected]>

---
 drivers/mtd/nand/spi/micron.c | 28 ++++++++++++++--------------
 1 file changed, 14 insertions(+), 14 deletions(-)

drivers/mtd/nand/spi/micron.c +14 ~~-14~~

index f56f81325e10..cc1ee68421c8 100644
@@ -34,38 +34,38 @@ static SPINAND_OP_VARIANTS(update_cache_variants,
 		SPINAND_PROG_LOAD_X4(false, 0, NULL, 0),
 		SPINAND_PROG_LOAD(false, 0, NULL, 0));
 
-static int mt29f2g01abagd_ooblayout_ecc(struct mtd_info *mtd, int section,
-					struct mtd_oob_region *region)
+static int micron_8_ooblayout_ecc(struct mtd_info *mtd, int section,
+				  struct mtd_oob_region *region)
 {
 	if (section)
 		return -ERANGE;
 
-	region->offset = 64;
-	region->length = 64;
+	region->offset = mtd->oobsize / 2;
+	region->length = mtd->oobsize / 2;
 
 	return 0;
 }
 
-static int mt29f2g01abagd_ooblayout_free(struct mtd_info *mtd, int section,
-					 struct mtd_oob_region *region)
+static int micron_8_ooblayout_free(struct mtd_info *mtd, int section,
+				   struct mtd_oob_region *region)
 {
 	if (section)
 		return -ERANGE;
 
 	/* Reserve 2 bytes for the BBM. */
 	region->offset = 2;
-	region->length = 62;
+	region->length = (mtd->oobsize / 2) - 2;
 
 	return 0;
 }
 
-static const struct mtd_ooblayout_ops mt29f2g01abagd_ooblayout = {
-	.ecc = mt29f2g01abagd_ooblayout_ecc,
-	.free = mt29f2g01abagd_ooblayout_free,
+static const struct mtd_ooblayout_ops micron_8_ooblayout = {
+	.ecc = micron_8_ooblayout_ecc,
+	.free = micron_8_ooblayout_free,
 };
 
-static int mt29f2g01abagd_ecc_get_status(struct spinand_device *spinand,
-					 u8 status)
+static int micron_8_ecc_get_status(struct spinand_device *spinand,
+				   u8 status)
 {
 	switch (status & MICRON_STATUS_ECC_MASK) {
 	case STATUS_ECC_NO_BITFLIPS:

@@ -99,8 +99,8 @@ static const struct spinand_info micron_spinand_table[] = {
 					      &write_cache_variants,
 					      &update_cache_variants),
 		     0,
-		     SPINAND_ECCINFO(&mt29f2g01abagd_ooblayout,
-				     mt29f2g01abagd_ecc_get_status)),
+		     SPINAND_ECCINFO(&micron_8_ooblayout,
+				     micron_8_ecc_get_status)),
 };
 
 static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {

Signature · 1 line

2.17.1

Miquel Raynal

maintainer Applied

2020-03-12 21:33 UTC #2 lore raw

Re: [PATCH v7 1/6] mtd: spinand: micron: Generalize the OOB layout structure and function names

Quoted 7 lines · On Wed, 2020-03-11 at 17:57:30 UTC, [email protected] wrote:

From: Shivamurthy Shastri <[email protected]>
In order to add new Micron SPI NAND devices, we generalized the OOB layout structure and function names.
Signed-off-by Shivamurthy Shastri <[email protected]>
Reviewed-by Boris Brezillon <[email protected]>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel

[email protected]

author

2020-03-11 17:59 UTC #3 lore raw

PATCH v7 2/6 mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD

In reply to [email protected]

From: Shivamurthy Shastri <[email protected]>

Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage details as a comment.

Signed-off-by Shivamurthy Shastri <[email protected]>

Reviewed-by Boris Brezillon <[email protected]>

---
 drivers/mtd/nand/spi/micron.c | 1 +
 1 file changed, 1 insertion(+)

drivers/mtd/nand/spi/micron.c +1 -0

index cc1ee68421c8..4727933c894b 100644
@@ -91,6 +91,7 @@ static int micron_8_ecc_get_status(struct spinand_device *spinand,
 }
 
 static const struct spinand_info micron_spinand_table[] = {
+	/* M79A 2Gb 3.3V */
 	SPINAND_INFO("MT29F2G01ABAGD",
 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x24),
 		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),

Signature · 1 line

2.17.1

Miquel Raynal

maintainer Applied

2020-03-12 21:33 UTC #4 lore raw

Re: [PATCH v7 2/6] mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD

Quoted 7 lines · On Wed, 2020-03-11 at 17:57:31 UTC, [email protected] wrote:

From: Shivamurthy Shastri <[email protected]>
Add the SPI NAND device MT29F2G01ABAGD series number, size and voltage details as a comment.
Signed-off-by Shivamurthy Shastri <[email protected]>
Reviewed-by Boris Brezillon <[email protected]>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel

[email protected]

author

2020-03-11 17:58 UTC #5 lore raw

PATCH v7 3/6 mtd: spinand: micron: Add new Micron SPI NAND devices

In reply to [email protected]

From: Shivamurthy Shastri <[email protected]>

Add device table for M79A and M78A series Micron SPI NAND devices.

Signed-off-by Shivamurthy Shastri <[email protected]>

Reviewed-by Boris Brezillon <[email protected]>

---
 drivers/mtd/nand/spi/micron.c | 33 +++++++++++++++++++++++++++++++++
 1 file changed, 33 insertions(+)

drivers/mtd/nand/spi/micron.c +33 -0

index 4727933c894b..26925714a9fb 100644
@@ -102,6 +102,39 @@ static const struct spinand_info micron_spinand_table[] = {
 		     0,
 		     SPINAND_ECCINFO(&micron_8_ooblayout,
 				     micron_8_ecc_get_status)),
+	/* M79A 2Gb 1.8V */
+	SPINAND_INFO("MT29F2G01ABBGD",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x25),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 40, 2, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&micron_8_ooblayout,
+				     micron_8_ecc_get_status)),
+	/* M78A 1Gb 3.3V */
+	SPINAND_INFO("MT29F1G01ABAFD",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x14),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&micron_8_ooblayout,
+				     micron_8_ecc_get_status)),
+	/* M78A 1Gb 1.8V */
+	SPINAND_INFO("MT29F1G01ABAFD",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x15),
+		     NAND_MEMORG(1, 2048, 128, 64, 1024, 20, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&micron_8_ooblayout,
+				     micron_8_ecc_get_status)),
 };
 
 static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {

Signature · 1 line

2.17.1

Miquel Raynal

maintainer Applied

2020-03-12 21:33 UTC #6 lore raw

Re: [PATCH v7 3/6] mtd: spinand: micron: Add new Micron SPI NAND devices

Quoted 6 lines · On Wed, 2020-03-11 at 17:57:32 UTC, [email protected] wrote:

From: Shivamurthy Shastri <[email protected]>
Add device table for M79A and M78A series Micron SPI NAND devices.
Signed-off-by Shivamurthy Shastri <[email protected]>
Reviewed-by Boris Brezillon <[email protected]>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel

[email protected]

author

2020-03-11 17:59 UTC #7 lore raw

PATCH v7 4/6 mtd: spinand: micron: identify SPI NAND device with Continuous Read mode

In reply to [email protected]

From: Shivamurthy Shastri <[email protected]>

Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode.

Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs.

In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area.

Hence, we disable the feature at probe time.

Signed-off-by Shivamurthy Shastri <[email protected]>

Reviewed-by Boris Brezillon <[email protected]>

---
 drivers/mtd/nand/spi/micron.c | 16 ++++++++++++++++
 include/linux/mtd/spinand.h   |  1 +
 2 files changed, 17 insertions(+)

drivers/mtd/nand/spi/micron.c +16 -0

index 26925714a9fb..956f7710aca2 100644
@@ -18,6 +18,8 @@
 #define MICRON_STATUS_ECC_4TO6_BITFLIPS	(3 << 4)
 #define MICRON_STATUS_ECC_7TO8_BITFLIPS	(5 << 4)
 
+#define MICRON_CFG_CR			BIT(0)
+
 static SPINAND_OP_VARIANTS(read_cache_variants,
 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),

@@ -137,7 +139,21 @@ static const struct spinand_info micron_spinand_table[] = {
 				     micron_8_ecc_get_status)),
 };
 
+static int micron_spinand_init(struct spinand_device *spinand)
+{
+	/*
+	 * M70A device series enable Continuous Read feature at Power-up,
+	 * which is not supported. Disable this bit to avoid any possible
+	 * failure.
+	 */
+	if (spinand->flags & SPINAND_HAS_CR_FEAT_BIT)
+		return spinand_upd_cfg(spinand, MICRON_CFG_CR, 0);
+
+	return 0;
+}
+
 static const struct spinand_manufacturer_ops micron_spinand_manuf_ops = {
+	.init = micron_spinand_init,
 };
 
 const struct spinand_manufacturer micron_spinand_manufacturer = {

include/linux/mtd/spinand.h +1 -0

index f4c4ae87181b..1077c45721ff 100644
@@ -284,6 +284,7 @@ struct spinand_ecc_info {
 };
 
 #define SPINAND_HAS_QE_BIT		BIT(0)
+#define SPINAND_HAS_CR_FEAT_BIT		BIT(1)
 
 /**
  * struct spinand_info - Structure used to describe SPI NAND chips

Signature · 1 line

2.17.1

Miquel Raynal

maintainer Applied

2020-03-12 21:33 UTC #8 lore raw

Re: [PATCH v7 4/6] mtd: spinand: micron: identify SPI NAND device with Continuous Read mode

Quoted 17 lines · On Wed, 2020-03-11 at 17:57:33 UTC, [email protected] wrote:

From: Shivamurthy Shastri <[email protected]>
Add SPINAND_HAS_CR_FEAT_BIT flag to identify the SPI NAND device with the Continuous Read mode.
Some of the Micron SPI NAND devices have the "Continuous Read" feature enabled by default, which does not fit the subsystem needs.
In this mode, the READ CACHE command doesn't require the starting column address. The device always output the data starting from the first column of the cache register, and once the end of the cache register reached, the data output continues through the next page. With the continuous read mode, it is possible to read out the entire block using a single READ command, and once the end of the block reached, the output pins become High-Z state. However, during this mode the read command doesn't output the OOB area.

Quoted 4 lines

Hence, we disable the feature at probe time.
Signed-off-by Shivamurthy Shastri <[email protected]>
Reviewed-by Boris Brezillon <[email protected]>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel

[email protected]

author

2020-03-11 17:59 UTC #9 lore raw

PATCH v7 5/6 mtd: spinand: micron: Add M70A series Micron SPI NAND devices

In reply to [email protected]

From: Shivamurthy Shastri <[email protected]>

Add device table for M70A series Micron SPI NAND devices.

Signed-off-by Shivamurthy Shastri <[email protected]>

Reviewed-by Boris Brezillon <[email protected]>

---
 drivers/mtd/nand/spi/micron.c | 22 ++++++++++++++++++++++
 1 file changed, 22 insertions(+)

drivers/mtd/nand/spi/micron.c +22 -0

index 956f7710aca2..d6fd63008782 100644
@@ -137,6 +137,28 @@ static const struct spinand_info micron_spinand_table[] = {
 		     0,
 		     SPINAND_ECCINFO(&micron_8_ooblayout,
 				     micron_8_ecc_get_status)),
+	/* M70A 4Gb 3.3V */
+	SPINAND_INFO("MT29F4G01ABAFD",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_CR_FEAT_BIT,
+		     SPINAND_ECCINFO(&micron_8_ooblayout,
+				     micron_8_ecc_get_status)),
+	/* M70A 4Gb 1.8V */
+	SPINAND_INFO("MT29F4G01ABBFD",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x35),
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 1),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_CR_FEAT_BIT,
+		     SPINAND_ECCINFO(&micron_8_ooblayout,
+				     micron_8_ecc_get_status)),
 };
 
 static int micron_spinand_init(struct spinand_device *spinand)

Signature · 1 line

2.17.1

Miquel Raynal

maintainer Applied

2020-03-12 21:33 UTC #10 lore raw

Re: [PATCH v7 5/6] mtd: spinand: micron: Add M70A series Micron SPI NAND devices

Quoted 6 lines · On Wed, 2020-03-11 at 17:57:34 UTC, [email protected] wrote:

From: Shivamurthy Shastri <[email protected]>
Add device table for M70A series Micron SPI NAND devices.
Signed-off-by Shivamurthy Shastri <[email protected]>
Reviewed-by Boris Brezillon <[email protected]>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel

[email protected]

author

2020-03-11 17:59 UTC #11 lore raw

PATCH v7 6/6 mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies

In reply to [email protected]

From: Shivamurthy Shastri <[email protected]>

Add device table for new Micron SPI NAND devices, which have multiple dies.

Also, enable support to select the dies.

Signed-off-by Shivamurthy Shastri <[email protected]>

Reviewed-by Boris Brezillon <[email protected]>

---
 drivers/mtd/nand/spi/micron.c | 58 +++++++++++++++++++++++++++++++++++
 1 file changed, 58 insertions(+)

drivers/mtd/nand/spi/micron.c +58 -0

index d6fd63008782..5d370cfcdaaa 100644
@@ -20,6 +20,14 @@
 
 #define MICRON_CFG_CR			BIT(0)
 
+/*
+ * As per datasheet, die selection is done by the 6th bit of Die
+ * Select Register (Address 0xD0).
+ */
+#define MICRON_DIE_SELECT_REG	0xD0
+
+#define MICRON_SELECT_DIE(x)	((x) << 6)
+
 static SPINAND_OP_VARIANTS(read_cache_variants,
 		SPINAND_PAGE_READ_FROM_CACHE_QUADIO_OP(0, 2, NULL, 0),
 		SPINAND_PAGE_READ_FROM_CACHE_X4_OP(0, 1, NULL, 0),

@@ -66,6 +74,20 @@ static const struct mtd_ooblayout_ops micron_8_ooblayout = {
 	.free = micron_8_ooblayout_free,
 };
 
+static int micron_select_target(struct spinand_device *spinand,
+				unsigned int target)
+{
+	struct spi_mem_op op = SPINAND_SET_FEATURE_OP(MICRON_DIE_SELECT_REG,
+						      spinand->scratchbuf);
+
+	if (target > 1)
+		return -EINVAL;
+
+	*spinand->scratchbuf = MICRON_SELECT_DIE(target);
+
+	return spi_mem_exec_op(spinand->spimem, &op);
+}
+
 static int micron_8_ecc_get_status(struct spinand_device *spinand,
 				   u8 status)
 {

@@ -137,6 +159,18 @@ static const struct spinand_info micron_spinand_table[] = {
 		     0,
 		     SPINAND_ECCINFO(&micron_8_ooblayout,
 				     micron_8_ecc_get_status)),
+	/* M79A 4Gb 3.3V */
+	SPINAND_INFO("MT29F4G01ADAGD",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x36),
+		     NAND_MEMORG(1, 2048, 128, 64, 2048, 80, 2, 1, 2),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     0,
+		     SPINAND_ECCINFO(&micron_8_ooblayout,
+				     micron_8_ecc_get_status),
+		     SPINAND_SELECT_TARGET(micron_select_target)),
 	/* M70A 4Gb 3.3V */
 	SPINAND_INFO("MT29F4G01ABAFD",
 		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x34),

@@ -159,6 +193,30 @@ static const struct spinand_info micron_spinand_table[] = {
 		     SPINAND_HAS_CR_FEAT_BIT,
 		     SPINAND_ECCINFO(&micron_8_ooblayout,
 				     micron_8_ecc_get_status)),
+	/* M70A 8Gb 3.3V */
+	SPINAND_INFO("MT29F8G01ADAFD",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x46),
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_CR_FEAT_BIT,
+		     SPINAND_ECCINFO(&micron_8_ooblayout,
+				     micron_8_ecc_get_status),
+		     SPINAND_SELECT_TARGET(micron_select_target)),
+	/* M70A 8Gb 1.8V */
+	SPINAND_INFO("MT29F8G01ADBFD",
+		     SPINAND_ID(SPINAND_READID_METHOD_OPCODE_DUMMY, 0x47),
+		     NAND_MEMORG(1, 4096, 256, 64, 2048, 40, 1, 1, 2),
+		     NAND_ECCREQ(8, 512),
+		     SPINAND_INFO_OP_VARIANTS(&read_cache_variants,
+					      &write_cache_variants,
+					      &update_cache_variants),
+		     SPINAND_HAS_CR_FEAT_BIT,
+		     SPINAND_ECCINFO(&micron_8_ooblayout,
+				     micron_8_ecc_get_status),
+		     SPINAND_SELECT_TARGET(micron_select_target)),
 };
 
 static int micron_spinand_init(struct spinand_device *spinand)

Signature · 1 line

2.17.1

Miquel Raynal

maintainer Applied

2020-03-12 21:33 UTC #12 lore raw

Re: [PATCH v7 6/6] mtd: spinand: micron: Add new Micron SPI NAND devices with multiple dies

Quoted 9 lines · On Wed, 2020-03-11 at 17:57:35 UTC, [email protected] wrote:

From: Shivamurthy Shastri <[email protected]>
Add device table for new Micron SPI NAND devices, which have multiple dies.
Also, enable support to select the dies.
Signed-off-by Shivamurthy Shastri <[email protected]>
Reviewed-by Boris Brezillon <[email protected]>

Applied to https://git.kernel.org/pub/scm/linux/kernel/git/mtd/linux.git nand/next, thanks.

Miquel

Shivamurthy Shastri (sshivamurthy)

2020-03-12 19:16 UTC #13 lore raw

In reply to [email protected]

Hi Miquel,

I have rebased these patches to nand/next as you suggested. Please let me know, if there is still a problem.

Thanks,
Shiva

Quoted 84 lines

From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
M78A:
[1] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m78a_1gb_3v_nand_spi.pdf
[2] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m78a_1gb_1_8v_nand_spi.pdf
M79A:
[3] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m79a_2gb_1_8v_nand_spi.pdf
[4] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m79a_ddp_4gb_3v_nand_spi.pdf
M70A:
[5] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m70a_4gb_3v_nand_spi.pdf
[6] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m70a_4gb_1_8v_nand_spi.pdf
[7] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m70a_ddp_8gb_3v_nand_spi.pdf
[8] https://www.micron.com/~/media/documents/products/data-
sheet/nand-flash/70-series/m70a_ddp_8gb_1_8v_nand_spi.pdf
Changes since v6:
-----------------
1. Rebased series to nand/next.
2. Added Reviewed-by from Boris.
Changes since v5:
-----------------
1. Rebased series to v5.6-rc1.
Changes since v4:
-----------------
1. Patch 2 is separated into two as per the comment by Boris.
2. Renamed MICRON_CFG_CONTI_READ into MICRON_CFG_CR.
3. Reworked die selection function as per the comment by Boris.
Changes since v3:
-----------------
1. Patch 3 and 4 reworked as follows
- Patch 3 introducing the Continuous read feature
- Patch 4 adding devices with the feature
Changes since v2:
-----------------
1. Patch commit messages have been modified.
2. Handled devices with Continuous Read feature with vendor specific flag.
3. Reworked die selection function as per the comment.
Changes since v1:
-----------------
1. The patch split into multiple patches.
2. Added comments for selecting the die.
Shivamurthy Shastri (6):
mtd: spinand: micron: Generalize the OOB layout structure and function
names
mtd: spinand: micron: Describe the SPI NAND device MT29F2G01ABAGD
mtd: spinand: micron: Add new Micron SPI NAND devices
mtd: spinand: micron: identify SPI NAND device with Continuous Read
mode
mtd: spinand: micron: Add M70A series Micron SPI NAND devices
mtd: spinand: micron: Add new Micron SPI NAND devices with multiple
dies
 drivers/mtd/nand/spi/micron.c | 158
+++++++++++++++++++++++++++++++---
 include/linux/mtd/spinand.h   |   1 +
 2 files changed, 145 insertions(+), 14 deletions(-)
--
2.17.1

Miquel Raynal

maintainer

2020-03-12 19:39 UTC #14 lore raw

Hi Shivamurthy,

"Shivamurthy Shastri (sshivamurthy)" <[email protected]> wrote on Thu, 12 Mar 2020 19:16:52 +0000:

Quoted 4 lines

Hi Miquel,
I have rebased these patches to nand/next as you suggested. Please let me know, if there is still a problem.

Everything applies smoothly, it's good, thanks!
Miquèl

Naresh Kamboju

2020-05-15 05:27 UTC #15 lore raw

In reply to [email protected]

Quoted 5 lines · On Wed, 11 Mar 2020 at 23:28, <[email protected]> wrote:

From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.

While boot NXP ls2088 device with mainline kernel the following nand warning noticed. How critical this warning ?

[    1.357722] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x48
[    1.364085] nand: Micron MT29F16G08ABACAWP
[    1.368181] nand: 2048 MiB, SLC, erase size: 512 KiB, page size:
4096, OOB size: 224
[    1.375932] nand: WARNING: 530000000.flash: the ECC used on your

system is too weak compared to the one required by the NAND chip

[    1.388767] Bad block table found at page 524160, version 0x01
[    1.396833] Bad block table found at page 524032, version 0x01
[    1.403781] nand_read_bbt: bad block at 0x000002d00000
[    1.408921] nand_read_bbt: bad block at 0x000002d80000
[    1.414750] fsl,ifc-nand 530000000.nand: IFC NAND device at

0x530000000, bank 2

Full test log,
https://qa-reports.linaro.org/lkft/linux-mainline-oe/build/v5.7-rc5-55-g1ae7efb38854/testrun/18254/log

- Naresh

Poonam Aggrwal

2020-05-15 05:29 UTC #16 lore raw

Adding Ashish.

Regards
Poonam

Quoted 48 lines

-----Original Message-----
From: Naresh Kamboju <[email protected]>
Sent: Friday, May 15, 2020 10:57 AM
To: [email protected]; Miquel Raynal <[email protected]>; Shivamurthy Shastri <[email protected]>
Cc: Richard Weinberger <[email protected]>; Vignesh Raghavendra <[email protected]>; Boris Brezillon <[email protected]>; Chuanhong Guo <[email protected]>; Frieder Schrempf <[email protected]>; [email protected]; open list <linux- [email protected]>; Poonam Aggrwal <[email protected]>; Suram Suram <[email protected]>; [email protected]
Subject: Re: [PATCH v7 0/6] Add new series Micron SPI NAND devices
Quoted 5 lines · On Wed, 11 Mar 2020 at 23:28, <[email protected]> wrote:
From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
While boot NXP ls2088 device with mainline kernel the following nand warning noticed. How critical this warning ?
[    1.357722] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x48
[    1.364085] nand: Micron MT29F16G08ABACAWP
[    1.368181] nand: 2048 MiB, SLC, erase size: 512 KiB, page size:
4096, OOB size: 224
[    1.375932] nand: WARNING: 530000000.flash: the ECC used on your
system is too weak compared to the one required by the NAND chip
[    1.388767] Bad block table found at page 524160, version 0x01
[    1.396833] Bad block table found at page 524032, version 0x01
[    1.403781] nand_read_bbt: bad block at 0x000002d00000
[    1.408921] nand_read_bbt: bad block at 0x000002d80000
[    1.414750] fsl,ifc-nand 530000000.nand: IFC NAND device at
0x530000000, bank 2
Full test log,
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fqa-
reports.linaro.org%2Flkft%2Flinux-mainline-oe%2Fbuild%2Fv5.7-rc5-55- g1ae7efb38854%2Ftestrun%2F18254%2Flog&data=02%7C01%7Cpoonam. aggrwal%40nxp.com%7C146f634c869f4c70baa108d7f8909ffb%7C686ea1d3bc2 b4c6fa92cd99c5c301635%7C0%7C0%7C637251172354638298&sdata=%2B Jhs%2Fb92%2BA56WzYdHe%2BBhXWfjk8feCGAFv%2BRzFKC9PM%3D&rese rved=0
- Naresh

Miquel Raynal

maintainer

2020-05-15 07:33 UTC #17 lore raw

Hi Poonam,

Poonam Aggrwal <[email protected]> wrote on Fri, 15 May 2020 05:29:07 +0000:

Quoted 27 lines

Adding Ashish.
Regards
Poonam
Quoted 22 lines
-----Original Message-----
From: Naresh Kamboju <[email protected]>
Sent: Friday, May 15, 2020 10:57 AM
To: [email protected]; Miquel Raynal <[email protected]>; Shivamurthy Shastri <[email protected]>
Cc: Richard Weinberger <[email protected]>; Vignesh Raghavendra <[email protected]>; Boris Brezillon <[email protected]>; Chuanhong Guo <[email protected]>; Frieder Schrempf <[email protected]>; [email protected]; open list <linux- [email protected]>; Poonam Aggrwal <[email protected]>; Suram Suram <[email protected]>; [email protected]
Subject: Re: [PATCH v7 0/6] Add new series Micron SPI NAND devices
Quoted 5 lines · On Wed, 11 Mar 2020 at 23:28, <[email protected]> wrote:
From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
While boot NXP ls2088 device with mainline kernel the following nand warning noticed. How critical this warning ?

Are you sure this is the right thread? Shivamurthy added SPI-NAND support, you are talking about a raw NAND device.

Quoted 7 lines

[    1.357722] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x48
[    1.364085] nand: Micron MT29F16G08ABACAWP
[    1.368181] nand: 2048 MiB, SLC, erase size: 512 KiB, page size:
4096, OOB size: 224
[    1.375932] nand: WARNING: 530000000.flash: the ECC used on your

system is too weak compared to the one required by the NAND chip

If you are talking about this one, it is pretty self explanatory: the NAND chip requires a minimum correction which is not achieved here. Either because the ECC engine cannot reach the requested amount (you cannot do anything) or because you requested a too low correction with DT properties.

Quoted 18 lines

Quoted 18 lines
[    1.388767] Bad block table found at page 524160, version 0x01
[    1.396833] Bad block table found at page 524032, version 0x01
[    1.403781] nand_read_bbt: bad block at 0x000002d00000
[    1.408921] nand_read_bbt: bad block at 0x000002d80000
[    1.414750] fsl,ifc-nand 530000000.nand: IFC NAND device at
0x530000000, bank 2
Full test log,
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fqa-
reports.linaro.org%2Flkft%2Flinux-mainline-oe%2Fbuild%2Fv5.7-rc5-55- g1ae7efb38854%2Ftestrun%2F18254%2Flog&data=02%7C01%7Cpoonam. aggrwal%40nxp.com%7C146f634c869f4c70baa108d7f8909ffb%7C686ea1d3bc2 b4c6fa92cd99c5c301635%7C0%7C0%7C637251172354638298&sdata=%2B Jhs%2Fb92%2BA56WzYdHe%2BBhXWfjk8feCGAFv%2BRzFKC9PM%3D&rese rved=0

Quoted 1 line

Quoted 1 line
- Naresh

Thanks,
Miquèl

Shivamurthy Shastri (sshivamurthy)

2020-05-15 09:59 UTC #18 lore raw

Hi Naresh and Poonam,

Quoted 49 lines

Subject: [EXT] Re: [PATCH v7 0/6] Add new series Micron SPI NAND devices
Hi Poonam,
Poonam Aggrwal <[email protected]> wrote on Fri, 15 May 2020 05:29:07 +0000:
Quoted 9 lines
Adding Ashish.
Regards
Poonam
Quoted 4 lines
-----Original Message-----
From: Naresh Kamboju <[email protected]>
Sent: Friday, May 15, 2020 10:57 AM
To: [email protected]; Miquel Raynal
<[email protected]>;
Quoted 5 lines
Quoted 5 lines
Shivamurthy Shastri <[email protected]>
Cc: Richard Weinberger <[email protected]>; Vignesh Raghavendra <[email protected]>; Boris Brezillon <[email protected]>; Chuanhong Guo <[email protected]>; Frieder Schrempf <[email protected]>; [email protected]; open
list <linux-
Quoted 1 line
Quoted 1 line
[email protected]>; Poonam Aggrwal
<[email protected]>;
Quoted 11 lines
Quoted 11 lines
Suram Suram <[email protected]>; [email protected]
Subject: Re: [PATCH v7 0/6] Add new series Micron SPI NAND devices
Quoted 5 lines · On Wed, 11 Mar 2020 at 23:28, <[email protected]> wrote:
From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
While boot NXP ls2088 device with mainline kernel the following nand
warning
Quoted 1 line
Quoted 1 line
noticed. How critical this warning ?
Are you sure this is the right thread? Shivamurthy added SPI-NAND support, you are talking about a raw NAND device.
Quoted 7 lines
Quoted 7 lines
[    1.357722] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x48
[    1.364085] nand: Micron MT29F16G08ABACAWP
[    1.368181] nand: 2048 MiB, SLC, erase size: 512 KiB, page size:
4096, OOB size: 224
[    1.375932] nand: WARNING: 530000000.flash: the ECC used on your
system is too weak compared to the one required by the NAND chip

Quoted 6 lines

If you are talking about this one, it is pretty self explanatory: the NAND chip requires a minimum correction which is not achieved here. Either because the ECC engine cannot reach the requested amount (you cannot do anything) or because you requested a too low correction with DT properties.

Minimum required ECC for this device is 8-bit. Below is the datasheet for your reference.

https://www.micron.com/-/media/client/global/documents/products/data-sheet/nand-flash/70-series/m72a_production_datasheet_revg.pdf?rev=bb0a4ba04a1f40f98e29dc624d178dd8

Quoted 22 lines

Quoted 11 lines
Quoted 11 lines
[    1.388767] Bad block table found at page 524160, version 0x01
[    1.396833] Bad block table found at page 524032, version 0x01
[    1.403781] nand_read_bbt: bad block at 0x000002d00000
[    1.408921] nand_read_bbt: bad block at 0x000002d80000
[    1.414750] fsl,ifc-nand 530000000.nand: IFC NAND device at
0x530000000, bank 2
Full test log,
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fqa-
Quoted 2 lines
Quoted 2 lines
reports.linaro.org%2Flkft%2Flinux-mainline-oe%2Fbuild%2Fv5.7-rc5-55-
g1ae7efb38854%2Ftestrun%2F18254%2Flog&data=02%7C01%7Cpoona m.
Quoted 1 line
Quoted 1 line
aggrwal%40nxp.com%7C146f634c869f4c70baa108d7f8909ffb%7C686ea1d3bc 2
Quoted 1 line
Quoted 1 line
b4c6fa92cd99c5c301635%7C0%7C0%7C637251172354638298&sdata=%2B
Quoted 1 line
Quoted 1 line

Quoted 8 lines

Jhs%2Fb92%2BA56WzYdHe%2BBhXWfjk8feCGAFv%2BRzFKC9PM%3D&r ese
Quoted 3 lines
Quoted 3 lines
rved=0
- Naresh
Thanks,
Miquèl

Thanks,
Shiva

Suram Suram

2020-05-15 10:02 UTC #19 lore raw

+Ron who owns the test on this platform in NXP.

-----Original Message-----
From: Shivamurthy Shastri (sshivamurthy) <[email protected]>
Sent: Friday, May 15, 2020 3:29 PM
To: Poonam Aggrwal <[email protected]>; Naresh Kamboju <[email protected]>
Cc: Miquel Raynal <[email protected]>; [email protected]; Ashish Kumar <[email protected]>; Richard Weinberger <[email protected]>; Vignesh Raghavendra <[email protected]>; Boris Brezillon <[email protected]>; Chuanhong Guo <[email protected]>; Frieder Schrempf <[email protected]>; [email protected]; open list <[email protected]>; Suram Suram <[email protected]>; [email protected]
Subject: RE: [EXT] Re: [PATCH v7 0/6] Add new series Micron SPI NAND devices

Caution: EXT Email

Hi Naresh and Poonam,

Quoted 52 lines

Subject: [EXT] Re: [PATCH v7 0/6] Add new series Micron SPI NAND devices
Hi Poonam,
Poonam Aggrwal <[email protected]> wrote on Fri, 15 May 2020 05:29:07 +0000:
Quoted 9 lines
Adding Ashish.
Regards
Poonam
Quoted 4 lines
-----Original Message-----
From: Naresh Kamboju <[email protected]>
Sent: Friday, May 15, 2020 10:57 AM
To: [email protected]; Miquel Raynal
<[email protected]>;
Quoted 6 lines
Quoted 6 lines
Shivamurthy Shastri <[email protected]>
Cc: Richard Weinberger <[email protected]>; Vignesh Raghavendra <[email protected]>; Boris Brezillon <[email protected]>; Chuanhong Guo <[email protected]>; Frieder Schrempf <[email protected]>; [email protected]; open
list <linux-
Quoted 1 line
Quoted 1 line
[email protected]>; Poonam Aggrwal
<[email protected]>;
Quoted 5 lines
Quoted 5 lines
Suram Suram <[email protected]>; [email protected]
Subject: Re: [PATCH v7 0/6] Add new series Micron SPI NAND devices
Quoted 1 line · On Wed, 11 Mar 2020 at 23:28, <[email protected]> wrote:
Quoted 7 lines
Quoted 7 lines
Quoted 4 lines
From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
While boot NXP ls2088 device with mainline kernel the following nand
warning
Quoted 1 line
Quoted 1 line
noticed. How critical this warning ?
Are you sure this is the right thread? Shivamurthy added SPI-NAND support, you are talking about a raw NAND device.
Quoted 7 lines
Quoted 7 lines
[    1.357722] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x48
[    1.364085] nand: Micron MT29F16G08ABACAWP
[    1.368181] nand: 2048 MiB, SLC, erase size: 512 KiB, page size:
4096, OOB size: 224
[    1.375932] nand: WARNING: 530000000.flash: the ECC used on your
system is too weak compared to the one required by the NAND chip

Quoted 6 lines

If you are talking about this one, it is pretty self explanatory: the NAND chip requires a minimum correction which is not achieved here. Either because the ECC engine cannot reach the requested amount (you cannot do anything) or because you requested a too low correction with DT properties.

Minimum required ECC for this device is 8-bit. Below is the datasheet for your reference.

https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fwww.micron.com%2F-%2Fmedia%2Fclient%2Fglobal%2Fdocuments%2Fproducts%2Fdata-sheet%2Fnand-flash%2F70-series%2Fm72a_production_datasheet_revg.pdf%3Frev%3Dbb0a4ba04a1f40f98e29dc624d178dd8&data=02%7C01%7Csuram%40nxp.com%7Cf699d2102f954d4d3bd208d7f8b69d35%7C686ea1d3bc2b4c6fa92cd99c5c301635%7C0%7C1%7C637251335518803010&sdata=1HP9Nx2mpttYGyURYB8t1hRsLOX6cBi05wnq8tiok64%3D&reserved=0

Quoted 23 lines

Quoted 11 lines
Quoted 11 lines
[    1.388767] Bad block table found at page 524160, version 0x01
[    1.396833] Bad block table found at page 524032, version 0x01
[    1.403781] nand_read_bbt: bad block at 0x000002d00000
[    1.408921] nand_read_bbt: bad block at 0x000002d80000
[    1.414750] fsl,ifc-nand 530000000.nand: IFC NAND device at
0x530000000, bank 2
Full test log,
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fqa-
Quoted 3 lines
Quoted 3 lines
reports.linaro.org%2Flkft%2Flinux-mainline-oe%2Fbuild%2Fv5.7-rc5-5 5-
g1ae7efb38854%2Ftestrun%2F18254%2Flog&data=02%7C01%7Cpoona m.
Quoted 1 line
Quoted 1 line
aggrwal%40nxp.com%7C146f634c869f4c70baa108d7f8909ffb%7C686ea1d3bc 2
Quoted 1 line
Quoted 1 line
b4c6fa92cd99c5c301635%7C0%7C0%7C637251172354638298&sdata=%2B
Quoted 1 line
Quoted 1 line

Quoted 8 lines

Jhs%2Fb92%2BA56WzYdHe%2BBhXWfjk8feCGAFv%2BRzFKC9PM%3D&r ese
Quoted 3 lines
Quoted 3 lines
rved=0
- Naresh
Thanks,
Miquèl

Thanks,
Shiva

X.f. Ren

2020-05-15 10:13 UTC #20 lore raw

Hello Suram, et al
Here are some information about those warming. Those warning should not impact testing.
"
It is in the nature of NAND Flash that a small proportion of the blocks in the device are defective and therefore unusable from the day of manufacture (typically up to 1% is deemed acceptable by the manufacturer). Manufacturers perform thorough testing to identify any potentially bad blocks. When they have been identified, bad blocks are marked with a special marker in the OOB area of the block. This is the Manufacturer's Bad Block Marker (MBBM).

RAM resident BBT
RAM-resident BBTs are volatile and must be recreated every time the system is booted. The process involves scanning each block in the NAND device to check for bad block markers.

The main advantage of this approach is simplicity. This is particularly true for manufacturability, where is is possible for a generic NAND programmer to program pre-prepared images without the need to understand the underlying ECC scheme or any BBT formats.

There are, however, a number of disadvantages. In some cases these disadvantages preclude the use of RAM-resident BBTs.
NAND resident BBT
The use of NAND-Resident BBTs overcomes many of the issues associated with RAM-resident BBTs. For most cases this is the recommended method for recording and tracking bad blocks.

As a NAND-resident BBT is non-volatile, it is preserved across system boots. There should never be any reason to recreate the BBT by scanning the NAND device for bad block markers.

Typically, the BBT requires two bits of storage for each block. The table is stored in the last good block with a backup in the penultimate good block. By default, the last four physical blocks are reserved for BBTs. If there are fewer than two good blocks available in the last four, then the NAND device should be discarded.

In a ideal situation, the BBT should be built and written to Flash before any other data. This is mandatory in cases where it is not possible to use the ECC tags to distinguish between valid programmed ECC data and an MBBM. However, this has implications for manufacturability, as the NAND programmer needs to be taught how to write the BBT, including the relevant ECC scheme.

In some cases, it may be appropriate for the NAND Programmer to skip writing BBTs, and to defer BBT creation to the software drivers when the system is first booted. This avoids the complexities of customising the NAND Programmer, whilst retaining the benefits of using NAND-resident BBTs. This approach is only viable if there is no clash between the ECC layout and the MBBM location, or where ECC tags can be used to avoid ECC data being misinterpreted as a MBBM. "

Best Regards
Ron

-----Original Message-----
From: Suram Suram <[email protected]>
Sent: 2020年5月15日 18:02
To: Shivamurthy Shastri (sshivamurthy) <[email protected]>; Poonam Aggrwal <[email protected]>; Naresh Kamboju <[email protected]>; X.f. Ren <[email protected]>
Cc: Miquel Raynal <[email protected]>; [email protected]; Ashish Kumar <[email protected]>; Richard Weinberger <[email protected]>; Vignesh Raghavendra <[email protected]>; Boris Brezillon <[email protected]>; Chuanhong Guo <[email protected]>; Frieder Schrempf <[email protected]>; [email protected]; open list <[email protected]>; [email protected]
Subject: RE: [EXT] Re: [PATCH v7 0/6] Add new series Micron SPI NAND devices

+Ron who owns the test on this platform in NXP.

Caution: EXT Email

Hi Naresh and Poonam,

Quoted 52 lines

Subject: [EXT] Re: [PATCH v7 0/6] Add new series Micron SPI NAND devices
Hi Poonam,
Poonam Aggrwal <[email protected]> wrote on Fri, 15 May 2020 05:29:07 +0000:
Quoted 9 lines
Adding Ashish.
Regards
Poonam
Quoted 4 lines
-----Original Message-----
From: Naresh Kamboju <[email protected]>
Sent: Friday, May 15, 2020 10:57 AM
To: [email protected]; Miquel Raynal
<[email protected]>;
Quoted 6 lines
Quoted 6 lines
Shivamurthy Shastri <[email protected]>
Cc: Richard Weinberger <[email protected]>; Vignesh Raghavendra <[email protected]>; Boris Brezillon <[email protected]>; Chuanhong Guo <[email protected]>; Frieder Schrempf <[email protected]>; [email protected]; open
list <linux-
Quoted 1 line
Quoted 1 line
[email protected]>; Poonam Aggrwal
<[email protected]>;
Quoted 5 lines
Quoted 5 lines
Suram Suram <[email protected]>; [email protected]
Subject: Re: [PATCH v7 0/6] Add new series Micron SPI NAND devices
Quoted 1 line · On Wed, 11 Mar 2020 at 23:28, <[email protected]> wrote:
Quoted 7 lines
Quoted 7 lines
Quoted 4 lines
From: Shivamurthy Shastri <[email protected]>
This patchset is for the new series of Micron SPI NAND devices, and the following links are their datasheets.
While boot NXP ls2088 device with mainline kernel the following nand
warning
Quoted 1 line
Quoted 1 line
noticed. How critical this warning ?
Are you sure this is the right thread? Shivamurthy added SPI-NAND support, you are talking about a raw NAND device.
Quoted 7 lines
Quoted 7 lines
[    1.357722] nand: device found, Manufacturer ID: 0x2c, Chip ID: 0x48
[    1.364085] nand: Micron MT29F16G08ABACAWP
[    1.368181] nand: 2048 MiB, SLC, erase size: 512 KiB, page size:
4096, OOB size: 224
[    1.375932] nand: WARNING: 530000000.flash: the ECC used on your
system is too weak compared to the one required by the NAND chip

Quoted 6 lines

If you are talking about this one, it is pretty self explanatory: the NAND chip requires a minimum correction which is not achieved here. Either because the ECC engine cannot reach the requested amount (you cannot do anything) or because you requested a too low correction with DT properties.

Minimum required ECC for this device is 8-bit. Below is the datasheet for your reference.

Quoted 23 lines

Quoted 11 lines
Quoted 11 lines
[    1.388767] Bad block table found at page 524160, version 0x01
[    1.396833] Bad block table found at page 524032, version 0x01
[    1.403781] nand_read_bbt: bad block at 0x000002d00000
[    1.408921] nand_read_bbt: bad block at 0x000002d80000
[    1.414750] fsl,ifc-nand 530000000.nand: IFC NAND device at
0x530000000, bank 2
Full test log,
https://eur01.safelinks.protection.outlook.com/?url=https%3A%2F%2Fqa-
Quoted 3 lines
Quoted 3 lines
reports.linaro.org%2Flkft%2Flinux-mainline-oe%2Fbuild%2Fv5.7-rc5-5 5-
g1ae7efb38854%2Ftestrun%2F18254%2Flog&data=02%7C01%7Cpoona m.
Quoted 1 line
Quoted 1 line
aggrwal%40nxp.com%7C146f634c869f4c70baa108d7f8909ffb%7C686ea1d3bc 2
Quoted 1 line
Quoted 1 line
b4c6fa92cd99c5c301635%7C0%7C0%7C637251172354638298&sdata=%2B
Quoted 1 line
Quoted 1 line

Quoted 8 lines

Jhs%2Fb92%2BA56WzYdHe%2BBhXWfjk8feCGAFv%2BRzFKC9PM%3D&r ese
Quoted 3 lines
Quoted 3 lines
rved=0
- Naresh
Thanks,
Miquèl

Thanks,
Shiva