Enable LP2 CPUIDLE state on NVIDIA Tegra30

Hello,

This series enables LP2 CPU idling state on Tegra30. Previously, Michał Mirosław reported that this wasn't working on ASUS Transformer device and we found that replicating the Transformer's downstream kernel behavior (in regards to the firmware) helps. Later on Michał told that LP2 works without the firmware changes using a different kernel version / config, we don't know for sure what was the cause of the original problem.

This series makes the TF firmware changes that are known to work well in regards to LP2 idling on all devices and then the LP2 idling state is enabled.

Please review and apply, thanks in advance.

Dmitry Osipenko (3):
ARM: tegra: Initialize r0 register for firmware wake-up
firmware: trusted_foundations: Different way of L2 cache enabling
after LP2 suspend
cpuidle: tegra: Support CPU cluster power-down state on Tegra30

 arch/arm/mach-tegra/pm.c                     |  4 ++++
 arch/arm/mach-tegra/reset-handler.S          |  7 ++++++-
 drivers/cpuidle/cpuidle-tegra.c              |  1 -
 drivers/firmware/trusted_foundations.c       | 21 ++++++++++++++++++--
 include/linux/firmware/trusted_foundations.h |  1 +
 5 files changed, 30 insertions(+), 4 deletions(-)

2.25.1

Downstream kernel of ASUS TF300T sets r0 to #3. There is no explanation in downstream code whether this is really needed and some of T30 downstream kernels have and explicit comment telling that all arguments are ignored by firmware. Let's take a safe side by replicating behavior of the TF300T downstream kernel. This change works fine on Ouya and Nexus 7 devices.

---
 arch/arm/mach-tegra/reset-handler.S | 7 ++++++-
 1 file changed, 6 insertions(+), 1 deletion(-)

index 53123ae4ac3b..06ca44b09381 100644
@@ -98,7 +98,12 @@ ENTRY(tegra_resume_trusted_foundations)
 	reteq	lr
 
  .arch_extension sec
-	/* First call after suspend wakes firmware. No arguments required. */
+	/*
+	 * First call after suspend wakes firmware. No arguments required
+	 * for some firmware versions. Downstream kernel of ASUS TF300T uses
+	 * r0=3 for the wake-up notification.
+	 */
+	mov	r0, #3
 	smc	#0
 
 	b	cpu_resume

2.25.1

Applied to for-5.8/arm/core, thanks.

Thierry

ASUS TF300T device may not work properly if firmware is asked to fully re-initialize L2 cache after resume from LP2 suspend. The downstream kernel of TF300T uses different opcode to enable cache after resuming from LP2, this opcode also works fine on Nexus 7 and Ouya devices. Supposedly, this may be needed by an older firmware versions.

---
 arch/arm/mach-tegra/pm.c                     |  4 ++++
 drivers/firmware/trusted_foundations.c       | 21 ++++++++++++++++++--
 include/linux/firmware/trusted_foundations.h |  1 +
 3 files changed, 24 insertions(+), 2 deletions(-)

index d1e1a61b12cf..6452ebf68d40 100644
@@ -216,6 +216,8 @@ int tegra_pm_enter_lp2(void)
 	restore_cpu_complex();
 	cpu_cluster_pm_exit();
 
+	call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
+
 	return err;
 }
 

@@ -391,6 +393,8 @@ static int tegra_suspend_enter(suspend_state_t state)
 
 	local_fiq_enable();
 
+	call_firmware_op(prepare_idle, TF_PM_MODE_NONE);
+
 	return 0;
 }
 

index fc544e19b0a1..1389fa9418a7 100644
@@ -19,6 +19,7 @@
 
 #define TF_CACHE_ENABLE		1
 #define TF_CACHE_DISABLE	2
+#define TF_CACHE_REENABLE	4
 
 #define TF_SET_CPU_BOOT_ADDR_SMC 0xfffff200
 

@@ -29,6 +30,7 @@
 #define TF_CPU_PM_S1		0xffffffe4
 #define TF_CPU_PM_S1_NOFLUSH_L2	0xffffffe7
 
+static unsigned long tf_idle_mode = TF_PM_MODE_NONE;
 static unsigned long cpu_boot_addr;
 
 static void tf_generic_smc(u32 type, u32 arg1, u32 arg2)

@@ -85,25 +87,40 @@ static int tf_prepare_idle(unsigned long mode)
 			       cpu_boot_addr);
 		break;
 
+	case TF_PM_MODE_NONE:
+		break;
+
 	default:
 		return -EINVAL;
 	}
 
+	tf_idle_mode = mode;
+
 	return 0;
 }
 
 #ifdef CONFIG_CACHE_L2X0
 static void tf_cache_write_sec(unsigned long val, unsigned int reg)
 {
-	u32 l2x0_way_mask = 0xff;
+	u32 enable_op, l2x0_way_mask = 0xff;
 
 	switch (reg) {
 	case L2X0_CTRL:
 		if (l2x0_saved_regs.aux_ctrl & L310_AUX_CTRL_ASSOCIATIVITY_16)
 			l2x0_way_mask = 0xffff;
 
+		switch (tf_idle_mode) {
+		case TF_PM_MODE_LP2:
+			enable_op = TF_CACHE_REENABLE;
+			break;
+
+		default:
+			enable_op = TF_CACHE_ENABLE;
+			break;
+		}
+
 		if (val == L2X0_CTRL_EN)
-			tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_ENABLE,
+			tf_generic_smc(TF_CACHE_MAINT, enable_op,
 				       l2x0_saved_regs.aux_ctrl);
 		else
 			tf_generic_smc(TF_CACHE_MAINT, TF_CACHE_DISABLE,

index 2549a2db56aa..be5984bda592 100644
@@ -32,6 +32,7 @@
 #define TF_PM_MODE_LP1_NO_MC_CLK	2
 #define TF_PM_MODE_LP2			3
 #define TF_PM_MODE_LP2_NOFLUSH_L2	4
+#define TF_PM_MODE_NONE			5
 
 struct trusted_foundations_platform_data {
 	unsigned int version_major;

2.25.1

I split this up and applied it to for-5.8/firmware and for-5.8/arm/core, respectively.

Thanks,
Thierry

The new Tegra CPU Idle driver now has a unified code path for the coupled CC6 (LP2) state, this allows to enable the deepest idling state on Tegra30 SoC where the whole CPU cluster is power-gated.

---
 drivers/cpuidle/cpuidle-tegra.c | 1 -
 1 file changed, 1 deletion(-)

index 313b0290e97b..150045849d78 100644
@@ -365,7 +365,6 @@ static int tegra_cpuidle_probe(struct platform_device *pdev)
 		break;
 
 	case TEGRA30:
-		tegra_cpuidle_disable_state(TEGRA_CC6);
 		break;
 
 	case TEGRA114:

2.25.1

Daniel,

do you mind if I pick this up into the Tegra tree because of the runtime dependencies on the firmware and ARM core changes in patches 1 & 2?

Thierry

Sorry for the late reply, I'm overbooked this cycle.

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