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spi: bcm-qspi: Handle clock probe deferral

PATCH In review Kamal Dasu 4 participants 20 messages Apr 20, 2020 – Apr 21, 2020 1 message not in the archive

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Device tree bindings SPI Broadcom SPI driver
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A message that is not in the archive (sent off-list or not yet received): [email protected]

Kamal Dasu

author
#1 lore raw

PATCH v3 1/9 spi: bcm-qspi: Handle clock probe deferral

From: Florian Fainelli <[email protected]>

The clock provider may not be ready by the time spi-bcm-qspi gets probed, handle probe deferral using devm_clk_get_optional().

Signed-off-by Florian Fainelli <[email protected]>
Signed-off-by Kamal Dasu <[email protected]>
---
 drivers/spi/spi-bcm-qspi.c | 12 +++++-------
 1 file changed, 5 insertions(+), 7 deletions(-)
drivers/spi/spi-bcm-qspi.c +5 -7
index 23d295f36c80..74f4579c3f6a 100644
@@ -1222,6 +1222,11 @@ int bcm_qspi_probe(struct platform_device *pdev,
 	}
 
 	qspi = spi_master_get_devdata(master);
+
+	qspi->clk = devm_clk_get_optional(&pdev->dev, NULL);
+	if (IS_ERR(qspi->clk))
+		return PTR_ERR(qspi->clk);
+
 	qspi->pdev = pdev;
 	qspi->trans_pos.trans = NULL;
 	qspi->trans_pos.byte = 0;

@@ -1335,13 +1340,6 @@ int bcm_qspi_probe(struct platform_device *pdev,
 		qspi->soc_intc = NULL;
 	}
 
-	qspi->clk = devm_clk_get(&pdev->dev, NULL);
-	if (IS_ERR(qspi->clk)) {
-		dev_warn(dev, "unable to get clock\n");
-		ret = PTR_ERR(qspi->clk);
-		goto qspi_probe_err;
-	}
-
 	ret = clk_prepare_enable(qspi->clk);
 	if (ret) {
 		dev_err(dev, "failed to prepare clock\n");
Signature · 1 line
2.17.1
maintainer
#2 lore raw
Quoted 9 lines · Kamal Dasu

From: Florian Fainelli <[email protected]>

The clock provider may not be ready by the time spi-bcm-qspi gets probed, handle probe deferral using devm_clk_get_optional().

Signed-off-by Florian Fainelli <[email protected]>
Signed-off-by Kamal Dasu <[email protected]>

[...]

Applied to

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.7

Thanks!

[1/9] spi: bcm-qspi: Handle clock probe deferral

      commit: 0392727c261bab65a35cd4f82ee9459bc237591d

[2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs
(not applied)
[3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset
(not applied)
[4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change

      commit: 742d5958062488d03082a9ff01a6afb3cf7bd634
[5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0
      commit: 4df3bea7f9d2ddd9ac2c29ba945c7c4db2def29c
[6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management
      commit: 1b7ad8c405c3dc0ad6c2dc61fe21fe7a446cceeb

[7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds
(not applied)
[8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz
(not applied)
[9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers
(not applied)

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

#3 lore raw
Quoted 6 lines · Mark Brown
Quoted 5 lines · Kamal Dasu

From: Florian Fainelli <[email protected]>

The clock provider may not be ready by the time spi-bcm-qspi gets probed, handle probe deferral using devm_clk_get_optional().

Quoted 8 lines
Quoted 4 lines
Signed-off-by Florian Fainelli <[email protected]>
Signed-off-by Kamal Dasu <[email protected]>

[...]

Applied to

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.7

It would be nice if the URL could be clickable, e.g.:

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/log/?h=for-5.7

Quoted 41 lines

Thanks!

[1/9] spi: bcm-qspi: Handle clock probe deferral

       commit: 0392727c261bab65a35cd4f82ee9459bc237591d

[2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs
(not applied)
[3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset
(not applied)
[4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change

       commit: 742d5958062488d03082a9ff01a6afb3cf7bd634
[5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0
       commit: 4df3bea7f9d2ddd9ac2c29ba945c7c4db2def29c
[6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management
       commit: 1b7ad8c405c3dc0ad6c2dc61fe21fe7a446cceeb

[7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds
(not applied)
[8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz
(not applied)
[9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers
(not applied)

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

Signature · 1 line
Florian
#5 lore raw
Quoted 4 lines · Mark Brown
Quoted 1 line · Florian Fainelli
Quoted 1 line

Applied to

Quoted 9 lines
Quoted 5 lines
Quoted 1 line

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.7

It would be nice if the URL could be clickable, e.g.:

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/log/?h=for-5.7

That then doesn't work with git itself unfortunately, someone's got to loose out :/

Could you provide both links with a market at the front, e.g.:

Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.7 CGIT URL: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/log/?h=for-5.7

Signature · 1 line
Florian
#7 lore raw
Quoted 7 lines · Mark Brown
Quoted 5 lines

Could you provide both links with a market at the front, e.g.:

Git URL: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git
for-5.7
CGIT URL: https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git/log/?h=for-5.7

Ask Konstantin to implement it (I'm using b4 ty now) and I might!

You can do this already in the template, if your treename is set to the https URL.

----
Applied to

Git: ${treename} ${branch}
Link: ${treename}/log/?h=${branch}
----

-K

maintainer
#8 lore raw
In reply to Kamal Dasu
Quoted 9 lines · Kamal Dasu

From: Florian Fainelli <[email protected]>

The clock provider may not be ready by the time spi-bcm-qspi gets probed, handle probe deferral using devm_clk_get_optional().

Signed-off-by Florian Fainelli <[email protected]>
Signed-off-by Kamal Dasu <[email protected]>

[...]

Applied to

https://git.kernel.org/pub/scm/linux/kernel/git/broonie/spi.git for-5.7

Thanks!

[1/9] spi: bcm-qspi: Handle clock probe deferral

      commit: 0392727c261bab65a35cd4f82ee9459bc237591d

[2/9] dt: bindings: spi: Add support for mspi on brcmstb SoCs
(not applied)
[3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset
(not applied)
[4/9] spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change

      commit: 742d5958062488d03082a9ff01a6afb3cf7bd634
[5/9] spi: bcm-qspi: when tx/rx buffer is NULL set to 0
      commit: 4df3bea7f9d2ddd9ac2c29ba945c7c4db2def29c
[6/9] spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management
      commit: 1b7ad8c405c3dc0ad6c2dc61fe21fe7a446cceeb

[7/9] spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds
(not applied)
[8/9] spi: bcm-qspi: add support for MSPI sys clk 108Mhz
(not applied)
[9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers
(not applied)

All being well this means that it will be integrated into the linux-next tree (usually sometime in the next 24 hours) and sent to Linus during the next merge window (or sooner if it is a bug fix), however if problems are discovered then the patch may be dropped or reverted.

You may get further e-mails resulting from automated or manual testing and review of the tree, please engage with people reporting problems and send followup patches addressing any issues that are reported if needed.

If any updates are required or you are submitting further changes they should be sent as incremental updates against current git, existing patches will not be replaced.

Please add any relevant lists and maintainers to the CCs when replying to this mail.

Thanks,
Mark

author
#9 lore raw

PATCH v3 2/9 dt: bindings: spi: Add support for mspi on brcmstb SoCs

In reply to a message not in the archive

Added documentation for compatibility for brcmstb SoCs :
7425, 7429, 7435, 7216, 7278

Signed-off-by Kamal Dasu <[email protected]>
---
 .../devicetree/bindings/spi/brcm,spi-bcm-qspi.txt      | 10 ++++++++++
 1 file changed, 10 insertions(+)
Documentation/devicetree/bindings/spi/brcm,spi-bcm-qspi.txt +10 -0
index ad7ac80a3841..f5e518d099f2 100644
@@ -26,6 +26,16 @@ Required properties:
     "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-qspi" : MSPI+BSPI on BRCMSTB SoCs
     "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
 						   BRCMSTB  SoCs
+    "brcm,spi-bcm7425-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+    			     			  			    BRCMSTB  SoCs
+    "brcm,spi-bcm7429-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+    			     			  			    BRCMSTB  SoCs
+    "brcm,spi-bcm7435-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+    			     			  			    BRCMSTB  SoCs
+    "brcm,spi-bcm7216-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+    			     			  			    BRCMSTB  SoCs
+    "brcm,spi-bcm7278-qspi", "brcm,spi-bcm-qspi", "brcm,spi-brcmstb-mspi" : Second Instance of MSPI
+    			     			  			    BRCMSTB  SoCs
     "brcm,spi-bcm-qspi", "brcm,spi-nsp-qspi"     : MSPI+BSPI on Cygnus, NSP
     "brcm,spi-bcm-qspi", "brcm,spi-ns2-qspi"     : NS2 SoCs
Signature · 1 line
2.17.1
author
#10 lore raw

PATCH v3 3/9 spi: bcm-qspi: Handle lack of MSPI_REV offset

In reply to a message not in the archive

From: Florian Fainelli <[email protected]>

Older MIPS chips have a QSPI/MSPI controller that does not have the MSPI_REV offset, reading from that offset will cause a bus error. Match their compatible string and do not perform a read from that register in that case.

Signed-off-by Florian Fainelli <[email protected]>
Signed-off-by Kamal Dasu <[email protected]>
---
 drivers/spi/spi-bcm-qspi.c | 50 ++++++++++++++++++++++++++++++++++++--
 1 file changed, 48 insertions(+), 2 deletions(-)
drivers/spi/spi-bcm-qspi.c +48 -2
index 74f4579c3f6a..d901dcb10d06 100644
@@ -91,6 +91,7 @@
 #define MSPI_MSPI_STATUS			0x020
 #define MSPI_CPTQP				0x024
 #define MSPI_SPCR3				0x028
+#define MSPI_REV				0x02c
 #define MSPI_TXRAM				0x040
 #define MSPI_RXRAM				0x0c0
 #define MSPI_CDRAM				0x140

@@ -217,6 +218,8 @@ struct bcm_qspi {
 	struct bcm_qspi_dev_id *dev_ids;
 	struct completion mspi_done;
 	struct completion bspi_done;
+	u8 mspi_maj_rev;
+	u8 mspi_min_rev;
 };
 
 static inline bool has_bspi(struct bcm_qspi *qspi)

@@ -1190,8 +1193,35 @@ static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
 	.exec_op = bcm_qspi_exec_mem_op,
 };
 
+struct bcm_qspi_data {
+	bool	has_mspi_rev;
+};
+
+static const struct bcm_qspi_data bcm_qspi_no_rev_data = {
+	.has_mspi_rev	= false,
+};
+
+static const struct bcm_qspi_data bcm_qspi_rev_data = {
+	.has_mspi_rev	= true,
+};
+
 static const struct of_device_id bcm_qspi_of_match[] = {
-	{ .compatible = "brcm,spi-bcm-qspi" },
+	{
+		.compatible = "brcm,spi-bcm7425-qspi",
+		.data = &bcm_qspi_no_rev_data,
+	},
+	{
+		.compatible = "brcm,spi-bcm7429-qspi",
+		.data = &bcm_qspi_no_rev_data,
+	},
+	{
+		.compatible = "brcm,spi-bcm7435-qspi",
+		.data = &bcm_qspi_no_rev_data,
+	},
+	{
+		.compatible = "brcm,spi-bcm-qspi",
+		.data = &bcm_qspi_rev_data,
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);

@@ -1199,12 +1229,15 @@ MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);
 int bcm_qspi_probe(struct platform_device *pdev,
 		   struct bcm_qspi_soc_intc *soc_intc)
 {
+	const struct of_device_id *of_id = NULL;
+	const struct bcm_qspi_data *data;
 	struct device *dev = &pdev->dev;
 	struct bcm_qspi *qspi;
 	struct spi_master *master;
 	struct resource *res;
 	int irq, ret = 0, num_ints = 0;
 	u32 val;
+	u32 rev = 0;
 	const char *name = NULL;
 	int num_irqs = ARRAY_SIZE(qspi_irq_tab);
 

@@ -1212,9 +1245,12 @@ int bcm_qspi_probe(struct platform_device *pdev,
 	if (!dev->of_node)
 		return -ENODEV;
 
-	if (!of_match_node(bcm_qspi_of_match, dev->of_node))
+	of_id = of_match_node(bcm_qspi_of_match, dev->of_node);
+	if (!of_id)
 		return -ENODEV;
 
+	data = of_id->data;
+
 	master = spi_alloc_master(dev, sizeof(struct bcm_qspi));
 	if (!master) {
 		dev_err(dev, "error allocating spi_master\n");

@@ -1349,6 +1385,16 @@ int bcm_qspi_probe(struct platform_device *pdev,
 	qspi->base_clk = clk_get_rate(qspi->clk);
 	qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
 
+	if (data->has_mspi_rev) {
+		rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);
+		/* some older revs do not have a MSPI_REV register */
+		if ((rev & 0xff) == 0xff)
+			rev = 0;
+	}
+
+	qspi->mspi_maj_rev = (rev >> 4) & 0xf;
+	qspi->mspi_min_rev = rev & 0xf;
+
 	bcm_qspi_hw_init(qspi);
 	init_completion(&qspi->mspi_done);
 	init_completion(&qspi->bspi_done);
Signature · 1 line
2.17.1
author
#11 lore raw

PATCH v3 4/9 spi: bcm-qspi: Drive MSPI peripheral SSb pin on cs_change

In reply to a message not in the archive

As per the spi core implementation for MSPI devices when the transfer is the last one in the message, the chip may stay selected until the next transfer. On multi-device SPI busses with nothing blocking messages going to other devices, this is just a performance hint; starting a message to another device deselects this one. But in other cases, this can be used to ensure correctness. Some devices need protocol transactions to be built from a series of spi_message submissions, where the content of one message is determined by the results of previous messages and where the whole transaction ends when the chipselect goes intactive.

On CS change after completing the last serial transfer, the MSPI driver drives SSb pin CDRAM register correctly according comments in core spi.h as shown below:

case 1) EOM =1, cs_change =0: SSb inactive
case 2) EOM =1, cs_change =1: SSb active
case 3) EOM =0, cs_change =0: SSb active
case 4) EOM =0, cs_change =1: SSb inactive

Signed-off-by Kamal Dasu <[email protected]>
---
 drivers/spi/spi-bcm-qspi.c | 19 ++++++++++++-------
 1 file changed, 12 insertions(+), 7 deletions(-)
drivers/spi/spi-bcm-qspi.c +12 -7
index d901dcb10d06..c48c399dce53 100644
@@ -615,19 +615,15 @@ static int update_qspi_trans_byte_count(struct bcm_qspi *qspi,
 		if (qt->trans->cs_change &&
 		    (flags & TRANS_STATUS_BREAK_CS_CHANGE))
 			ret |= TRANS_STATUS_BREAK_CS_CHANGE;
-		if (ret)
-			goto done;
 
-		dev_dbg(&qspi->pdev->dev, "advance msg exit\n");
 		if (bcm_qspi_mspi_transfer_is_last(qspi, qt))
-			ret = TRANS_STATUS_BREAK_EOM;
+			ret |= TRANS_STATUS_BREAK_EOM;
 		else
-			ret = TRANS_STATUS_BREAK_NO_BYTES;
+			ret |= TRANS_STATUS_BREAK_NO_BYTES;
 
 		qt->trans = NULL;
 	}
 
-done:
 	dev_dbg(&qspi->pdev->dev, "trans %p len %d byte %d ret %x\n",
 		qt->trans, qt->trans ? qt->trans->len : 0, qt->byte, ret);
 	return ret;

@@ -774,7 +770,16 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
 	bcm_qspi_write(qspi, MSPI, MSPI_NEWQP, 0);
 	bcm_qspi_write(qspi, MSPI, MSPI_ENDQP, slot - 1);
 
-	if (tstatus & TRANS_STATUS_BREAK_DESELECT) {
+	/*
+	 *  case 1) EOM =1, cs_change =0: SSb inactive
+	 *  case 2) EOM =1, cs_change =1: SSb stay active
+	 *  case 3) EOM =0, cs_change =0: SSb stay active
+	 *  case 4) EOM =0, cs_change =1: SSb inactive
+	 */
+	if (((tstatus & TRANS_STATUS_BREAK_DESELECT)
+	     == TRANS_STATUS_BREAK_CS_CHANGE) ||
+	    ((tstatus & TRANS_STATUS_BREAK_DESELECT)
+	     == TRANS_STATUS_BREAK_EOM)) {
 		mspi_cdram = read_cdram_slot(qspi, slot - 1) &
 			~MSPI_CDRAM_CONT_BIT;
 		write_cdram_slot(qspi, slot - 1, mspi_cdram);
Signature · 1 line
2.17.1
author
#12 lore raw

PATCH v3 5/9 spi: bcm-qspi: when tx/rx buffer is NULL set to 0

In reply to a message not in the archive

From: Justin Chen <[email protected]>

Currently we set the tx/rx buffer to 0xff when NULL. This causes problems with some spi slaves where 0xff is a valid command. Looking at other drivers, the tx/rx buffer is usually set to 0x00 when NULL. Following this convention solves the issue.

Fixes fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
Signed-off-by Justin Chen <[email protected]>
Signed-off-by Kamal Dasu <[email protected]>
---
 drivers/spi/spi-bcm-qspi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)
drivers/spi/spi-bcm-qspi.c +4 -4
index c48c399dce53..e00208801c8b 100644
@@ -669,7 +669,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots)
 			if (buf)
 				buf[tp.byte] = read_rxram_slot_u8(qspi, slot);
 			dev_dbg(&qspi->pdev->dev, "RD %02x\n",
-				buf ? buf[tp.byte] : 0xff);
+				buf ? buf[tp.byte] : 0x0);
 		} else {
 			u16 *buf = tp.trans->rx_buf;
 

@@ -677,7 +677,7 @@ static void read_from_hw(struct bcm_qspi *qspi, int slots)
 				buf[tp.byte / 2] = read_rxram_slot_u16(qspi,
 								      slot);
 			dev_dbg(&qspi->pdev->dev, "RD %04x\n",
-				buf ? buf[tp.byte] : 0xffff);
+				buf ? buf[tp.byte / 2] : 0x0);
 		}
 
 		update_qspi_trans_byte_count(qspi, &tp,

@@ -732,13 +732,13 @@ static int write_to_hw(struct bcm_qspi *qspi, struct spi_device *spi)
 	while (!tstatus && slot < MSPI_NUM_CDRAM) {
 		if (tp.trans->bits_per_word <= 8) {
 			const u8 *buf = tp.trans->tx_buf;
-			u8 val = buf ? buf[tp.byte] : 0xff;
+			u8 val = buf ? buf[tp.byte] : 0x00;
 
 			write_txram_slot_u8(qspi, slot, val);
 			dev_dbg(&qspi->pdev->dev, "WR %02x\n", val);
 		} else {
 			const u16 *buf = tp.trans->tx_buf;
-			u16 val = buf ? buf[tp.byte / 2] : 0xffff;
+			u16 val = buf ? buf[tp.byte / 2] : 0x0000;
 
 			write_txram_slot_u16(qspi, slot, val);
 			dev_dbg(&qspi->pdev->dev, "WR %04x\n", val);
Signature · 1 line
2.17.1
author
#13 lore raw

PATCH v3 6/9 spi: bcm-qspi: Make PM suspend/resume work with SCMI clock management

In reply to a message not in the archive

SCMI only passes clk_prepare_enable() and clk_disable_unprepare(), made changes to suspend/resume ops to use the appropriate calls so that PM works for ARM and ARM64 platforms.

Signed-off-by Kamal Dasu <[email protected]>
---
 drivers/spi/spi-bcm-qspi.c | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)
drivers/spi/spi-bcm-qspi.c +2 -2
index e00208801c8b..a3936ae5a860 100644
@@ -1455,7 +1455,7 @@ static int __maybe_unused bcm_qspi_suspend(struct device *dev)
 			bcm_qspi_read(qspi, BSPI, BSPI_STRAP_OVERRIDE_CTRL);
 
 	spi_master_suspend(qspi->master);
-	clk_disable(qspi->clk);
+	clk_disable_unprepare(qspi->clk);
 	bcm_qspi_hw_uninit(qspi);
 
 	return 0;

@@ -1473,7 +1473,7 @@ static int __maybe_unused bcm_qspi_resume(struct device *dev)
 		qspi->soc_intc->bcm_qspi_int_set(qspi->soc_intc, MSPI_DONE,
 						 true);
 
-	ret = clk_enable(qspi->clk);
+	ret = clk_prepare_enable(qspi->clk);
 	if (!ret)
 		spi_master_resume(qspi->master);
Signature · 1 line
2.17.1
author
#14 lore raw

PATCH v3 7/9 spi: bcm-qspi: Use fastbr setting to allow faster MSPI speeds

In reply to a message not in the archive

Setting MSPI_SPCR3.fastbr=1 allows using clock divider (SPBR) values of 1-7, while the default value prohibits these values and requires a minimum clock divider value of 8.

Signed-off-by Kamal Dasu <[email protected]>
---
 drivers/spi/spi-bcm-qspi.c | 36 +++++++++++++++++++++++++++++++++---
 1 file changed, 33 insertions(+), 3 deletions(-)
drivers/spi/spi-bcm-qspi.c +33 -3
index a3936ae5a860..edc601dbf221 100644
@@ -107,13 +107,15 @@
 #define MSPI_SPCR2_SPE				BIT(6)
 #define MSPI_SPCR2_CONT_AFTER_CMD		BIT(7)
 
+#define MSPI_SPCR3_FASTBR			BIT(0)
+#define MSPI_SPCR3_FASTDT			BIT(1)
+
 #define MSPI_MSPI_STATUS_SPIF			BIT(0)
 
 #define INTR_BASE_BIT_SHIFT			0x02
 #define INTR_COUNT				0x07
 
 #define NUM_CHIPSELECT				4
-#define QSPI_SPBR_MIN				8U
 #define QSPI_SPBR_MAX				255U
 
 #define OPCODE_DIOR				0xBB

@@ -227,6 +229,25 @@ static inline bool has_bspi(struct bcm_qspi *qspi)
 	return qspi->bspi_mode;
 }
 
+/* hardware supports spcr3 and fast baud-rate  */
+static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
+{
+	if (!has_bspi(qspi) &&
+	    ((qspi->mspi_maj_rev >= 1) &&
+	     (qspi->mspi_min_rev >= 5)))
+		return true;
+
+	return false;
+}
+
+static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
+{
+	if (bcm_qspi_has_fastbr(qspi))
+		return 1;
+	else
+		return 8;
+}
+
 /* Read qspi controller register*/
 static inline u32 bcm_qspi_read(struct bcm_qspi *qspi, enum base_type type,
 				unsigned int offset)

@@ -534,7 +555,7 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
 	if (xp->speed_hz)
 		spbr = qspi->base_clk / (2 * xp->speed_hz);
 
-	spcr = clamp_val(spbr, QSPI_SPBR_MIN, QSPI_SPBR_MAX);
+	spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
 
 	spcr = MSPI_MASTER_BIT;

@@ -544,6 +565,14 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
 	spcr |= xp->mode & 3;
 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
 
+	if (bcm_qspi_has_fastbr(qspi)) {
+		spcr = 0;
+
+		/* enable fastbr */
+		spcr |=	MSPI_SPCR3_FASTBR;
+		bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
+	}
+
 	qspi->last_parms = *xp;
 }
 

@@ -1388,7 +1417,6 @@ int bcm_qspi_probe(struct platform_device *pdev,
 	}
 
 	qspi->base_clk = clk_get_rate(qspi->clk);
-	qspi->max_speed_hz = qspi->base_clk / (QSPI_SPBR_MIN * 2);
 
 	if (data->has_mspi_rev) {
 		rev = bcm_qspi_read(qspi, MSPI, MSPI_REV);

@@ -1400,6 +1428,8 @@ int bcm_qspi_probe(struct platform_device *pdev,
 	qspi->mspi_maj_rev = (rev >> 4) & 0xf;
 	qspi->mspi_min_rev = rev & 0xf;
 
+	qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
+
 	bcm_qspi_hw_init(qspi);
 	init_completion(&qspi->mspi_done);
 	init_completion(&qspi->bspi_done);
Signature · 1 line
2.17.1
author
#15 lore raw

PATCH v3 8/9 spi: bcm-qspi: add support for MSPI sys clk 108Mhz

In reply to a message not in the archive

Adding support for MSPI sys clk 108Mhz available on 7216 and 7278 BRCMSTB SoCs.

Signed-off-by Kamal Dasu <[email protected]>
---
 drivers/spi/spi-bcm-qspi.c | 44 ++++++++++++++++++++++++++++++++++++++
 1 file changed, 44 insertions(+)
drivers/spi/spi-bcm-qspi.c +44 -0
index edc601dbf221..99f2cfcbb50c 100644
@@ -109,6 +109,11 @@
 
 #define MSPI_SPCR3_FASTBR			BIT(0)
 #define MSPI_SPCR3_FASTDT			BIT(1)
+#define MSPI_SPCR3_SYSCLKSEL_MASK		GENMASK(11, 10)
+#define MSPI_SPCR3_SYSCLKSEL_27			(MSPI_SPCR3_SYSCLKSEL_MASK & \
+						 ~(BIT(10) | BIT(11)))
+#define MSPI_SPCR3_SYSCLKSEL_108		(MSPI_SPCR3_SYSCLKSEL_MASK & \
+						 BIT(11))
 
 #define MSPI_MSPI_STATUS_SPIF			BIT(0)
 

@@ -117,6 +122,7 @@
 
 #define NUM_CHIPSELECT				4
 #define QSPI_SPBR_MAX				255U
+#define MSPI_BASE_FREQ				27000000UL
 
 #define OPCODE_DIOR				0xBB
 #define OPCODE_QIOR				0xEB

@@ -222,6 +228,7 @@ struct bcm_qspi {
 	struct completion bspi_done;
 	u8 mspi_maj_rev;
 	u8 mspi_min_rev;
+	bool mspi_spcr3_sysclk;
 };
 
 static inline bool has_bspi(struct bcm_qspi *qspi)

@@ -240,6 +247,17 @@ static inline bool bcm_qspi_has_fastbr(struct bcm_qspi *qspi)
 	return false;
 }
 
+/* hardware supports sys clk 108Mhz  */
+static inline bool bcm_qspi_has_sysclk_108(struct bcm_qspi *qspi)
+{
+	if (!has_bspi(qspi) && (qspi->mspi_spcr3_sysclk ||
+	    ((qspi->mspi_maj_rev >= 1) &&
+	     (qspi->mspi_min_rev >= 6))))
+		return true;
+
+	return false;
+}
+
 static inline int bcm_qspi_spbr_min(struct bcm_qspi *qspi)
 {
 	if (bcm_qspi_has_fastbr(qspi))

@@ -570,6 +588,15 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
 
 		/* enable fastbr */
 		spcr |=	MSPI_SPCR3_FASTBR;
+
+		if (bcm_qspi_has_sysclk_108(qspi)) {
+			/* SYSCLK_108 */
+			spcr |= MSPI_SPCR3_SYSCLKSEL_108;
+			qspi->base_clk = MSPI_BASE_FREQ * 4;
+			/* Change spbr as we changed sysclk */
+			bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, 4);
+		}
+
 		bcm_qspi_write(qspi, MSPI, MSPI_SPCR3, spcr);
 	}
 

@@ -1229,14 +1256,22 @@ static const struct spi_controller_mem_ops bcm_qspi_mem_ops = {
 
 struct bcm_qspi_data {
 	bool	has_mspi_rev;
+	bool	has_spcr3_sysclk;
 };
 
 static const struct bcm_qspi_data bcm_qspi_no_rev_data = {
 	.has_mspi_rev	= false,
+	.has_spcr3_sysclk = false,
 };
 
 static const struct bcm_qspi_data bcm_qspi_rev_data = {
 	.has_mspi_rev	= true,
+	.has_spcr3_sysclk = false,
+};
+
+static const struct bcm_qspi_data bcm_qspi_spcr3_data = {
+	.has_mspi_rev	= true,
+	.has_spcr3_sysclk = true,
 };
 
 static const struct of_device_id bcm_qspi_of_match[] = {

@@ -1256,6 +1291,14 @@ static const struct of_device_id bcm_qspi_of_match[] = {
 		.compatible = "brcm,spi-bcm-qspi",
 		.data = &bcm_qspi_rev_data,
 	},
+	{
+		.compatible = "brcm,spi-bcm7216-qspi",
+		.data = &bcm_qspi_spcr3_data,
+	},
+	{
+		.compatible = "brcm,spi-bcm7278-qspi",
+		.data = &bcm_qspi_spcr3_data,
+	},
 	{},
 };
 MODULE_DEVICE_TABLE(of, bcm_qspi_of_match);

@@ -1427,6 +1470,7 @@ int bcm_qspi_probe(struct platform_device *pdev,
 
 	qspi->mspi_maj_rev = (rev >> 4) & 0xf;
 	qspi->mspi_min_rev = rev & 0xf;
+	qspi->mspi_spcr3_sysclk = data->has_spcr3_sysclk;
 
 	qspi->max_speed_hz = qspi->base_clk / (bcm_qspi_spbr_min(qspi) * 2);
Signature · 1 line
2.17.1
author
#16 lore raw

PATCH v3 9/9 spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers

In reply to a message not in the archive

Set MASTER bit on the MSPI_SPCR0_MSB only for legacy MSPI and HIF_MSPI controllers.

Fixes fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
Signed-off-by Kamal Dasu <[email protected]>
---
 drivers/spi/spi-bcm-qspi.c | 8 +++++++-
 1 file changed, 7 insertions(+), 1 deletion(-)
drivers/spi/spi-bcm-qspi.c +7 -1
index 99f2cfcbb50c..681d09085175 100644
@@ -576,11 +576,17 @@ static void bcm_qspi_hw_set_parms(struct bcm_qspi *qspi,
 	spcr = clamp_val(spbr, bcm_qspi_spbr_min(qspi), QSPI_SPBR_MAX);
 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_LSB, spcr);
 
-	spcr = MSPI_MASTER_BIT;
+	if (!qspi->mspi_maj_rev)
+		/* legacy controller */
+		spcr = MSPI_MASTER_BIT;
+	else
+		spcr = 0;
+
 	/* for 16 bit the data should be zero */
 	if (xp->bits_per_word != 16)
 		spcr |= xp->bits_per_word << 2;
 	spcr |= xp->mode & 3;
+
 	bcm_qspi_write(qspi, MSPI, MSPI_SPCR0_MSB, spcr);
 
 	if (bcm_qspi_has_fastbr(qspi)) {
Signature · 1 line
2.17.1
maintainer
#17 lore raw

Re: [Patch v3 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers

Quoted 5 lines · Kamal Dasu

Set MASTER bit on the MSPI_SPCR0_MSB only for legacy MSPI and HIF_MSPI controllers.

Fixes fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
Signed-off-by Kamal Dasu <[email protected]>

If this is a fix it should have been near the start of the series before any new features to make sure that it can be applied cleanly as a fix.

author
#18 lore raw

Re: [Patch v3 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers

Quoted 10 lines · Mark Brown
Quoted 5 lines · Kamal Dasu

Set MASTER bit on the MSPI_SPCR0_MSB only for legacy MSPI and HIF_MSPI controllers.

Fixes fa236a7ef240 ("spi: bcm-qspi: Add Broadcom MSPI driver")
Signed-off-by Kamal Dasu <[email protected]>

If this is a fix it should have been near the start of the series before any new features to make sure that it can be applied cleanly as a fix.

Yes it could can be after [Patch v3 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset

Kamal

maintainer
#19 lore raw

Re: [Patch v3 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers

Quoted 7 lines · Kamal Dasu
Quoted 2 lines · Mark Brown

If this is a fix it should have been near the start of the series before any new features to make sure that it can be applied cleanly as a fix.

Yes it could can be after [Patch v3 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset

That's not a fix though, that's adding support for new devices?

author
#20 lore raw

Re: [Patch v3 9/9] spi: bcm-qspi: MSPI_SPCR0_MSB MSTR bit exists only on legacy controllers

Quoted 11 lines · Mark Brown
Quoted 7 lines · Kamal Dasu
Quoted 2 lines · Mark Brown

If this is a fix it should have been near the start of the series before any new features to make sure that it can be applied cleanly as a fix.

Yes it could can be after [Patch v3 3/9] spi: bcm-qspi: Handle lack of MSPI_REV offset

That's not a fix though, that's adding support for new devices?

Since its dependent on knowing if the MSPI_REV register exists on a given SoC and path 3/9, maybe I can remove the fixes tag for that commit.

Kamal

Kamal