Add USB DWC3 support for SC7180
Subsystems (3)
v5 cover Add USB DWC3 support for SC7180
Converting dt binding to yaml.
Adding compatible for SC7180 in dt bindings.
Changes in v5:
Addressed the comments from Stephen in yaml file.
Changes in v4:
Addressed the comments from Doug in yaml file.
Changes in v3:
Dropped the patch for adding the compatible in dwc3 driver from the series. Addressed the comments from Doug in yaml file.
Changes in v2:
Sorted the compatible in dwc3 driver.
Converted dt binding to yaml.
Added compatible in yaml.
Sandeep Maheswaram (2):
dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
dt-bindings: usb: qcom,dwc3: Add compatible for SC7180
.../devicetree/bindings/usb/qcom,dwc3.txt | 104 -------------- .../devicetree/bindings/usb/qcom,dwc3.yaml | 159 +++++++++++++++++++++ 2 files changed, 159 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 1/2 dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
Convert USB DWC3 bindings to DT schema format using json-schema.
--- .../devicetree/bindings/usb/qcom,dwc3.txt | 104 -------------- .../devicetree/bindings/usb/qcom,dwc3.yaml | 158 +++++++++++++++++++++ 2 files changed, 158 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.yaml
Documentation/devicetree/bindings/usb/qcom,dwc3.txt deleted +0 -104
@@ -1,104 +0,0 @@ -Qualcomm SuperSpeed DWC3 USB SoC controller - -Required properties: -- compatible: Compatible list, contains - "qcom,dwc3" - "qcom,msm8996-dwc3" for msm8996 SOC. - "qcom,msm8998-dwc3" for msm8998 SOC. - "qcom,sdm845-dwc3" for sdm845 SOC. -- reg: Offset and length of register set for QSCRATCH wrapper -- power-domains: specifies a phandle to PM domain provider node -- clocks: A list of phandle + clock-specifier pairs for the - clocks listed in clock-names -- clock-names: Should contain the following: - "core" Master/Core clock, have to be >= 125 MHz for SS - operation and >= 60MHz for HS operation - "mock_utmi" Mock utmi clock needed for ITP/SOF generation in - host mode. Its frequency should be 19.2MHz. - "sleep" Sleep clock, used for wakeup when USB3 core goes - into low power mode (U3). - -Optional clocks: - "iface" System bus AXI clock. - Not present on "qcom,msm8996-dwc3" compatible. - "cfg_noc" System Config NOC clock. - Not present on "qcom,msm8996-dwc3" compatible. -- assigned-clocks: Should be: - MOCK_UTMI_CLK - MASTER_CLK -- assigned-clock-rates: Should be: - 19.2Mhz (192000000) for MOCK_UTMI_CLK - >=125Mhz (125000000) for MASTER_CLK in SS mode - >=60Mhz (60000000) for MASTER_CLK in HS mode - -Optional properties: -- resets: Phandle to reset control that resets core and wrapper. -- interrupts: specifies interrupts from controller wrapper used - to wakeup from low power/susepnd state. Must contain - one or more entry for interrupt-names property -- interrupt-names: Must include the following entries: - - "hs_phy_irq": The interrupt that is asserted when a - wakeup event is received on USB2 bus - - "ss_phy_irq": The interrupt that is asserted when a - wakeup event is received on USB3 bus - - "dm_hs_phy_irq" and "dp_hs_phy_irq": Separate - interrupts for any wakeup event on DM and DP lines -- qcom,select-utmi-as-pipe-clk: if present, disable USB3 pipe_clk requirement. - Used when dwc3 operates without SSPHY and only - HS/FS/LS modes are supported. - -Required child node: -A child node must exist to represent the core DWC3 IP block. The name of -the node is not important. The content of the node is defined in dwc3.txt. - -Phy documentation is provided in the following places: -Documentation/devicetree/bindings/phy/qcom-qmp-phy.txt - USB3 QMP PHY -Documentation/devicetree/bindings/phy/qcom-qusb2-phy.txt - USB2 QUSB2 PHY - -Example device nodes: - - hs_phy: phy@100f8800 { - compatible = "qcom,qusb2-v2-phy"; - ... - }; - - ss_phy: phy@100f8830 { - compatible = "qcom,qmp-v3-usb3-phy"; - ... - }; - - usb3_0: usb30@a6f8800 { - compatible = "qcom,dwc3"; - reg = <0xa6f8800 0x400>; - #address-cells = <1>; - #size-cells = <1>; - ranges; - - interrupts = <0 131 0>, <0 486 0>, <0 488 0>, <0 489 0>; - interrupt-names = "hs_phy_irq", "ss_phy_irq", - "dm_hs_phy_irq", "dp_hs_phy_irq"; - - clocks = <&gcc GCC_USB30_PRIM_MASTER_CLK>, - <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_SLEEP_CLK>; - clock-names = "core", "mock_utmi", "sleep"; - - assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, - <&gcc GCC_USB30_PRIM_MASTER_CLK>; - assigned-clock-rates = <19200000>, <133000000>; - - resets = <&gcc GCC_USB30_PRIM_BCR>; - reset-names = "core_reset"; - power-domains = <&gcc USB30_PRIM_GDSC>; - qcom,select-utmi-as-pipe-clk; - - dwc3@10000000 { - compatible = "snps,dwc3"; - reg = <0x10000000 0xcd00>; - interrupts = <0 205 0x4>; - phys = <&hs_phy>, <&ss_phy>; - phy-names = "usb2-phy", "usb3-phy"; - dr_mode = "host"; - }; - }; -
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +158 -0
158 lines not on this page · raw message
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Rob Herring
maintainerRe: [PATCH v5 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
Quoted 71 lines · Sandeep Maheswaram
Convert USB DWC3 bindings to DT schema format using json-schema.
Signed-off-by Sandeep Maheswaram <[email protected]>--- .../devicetree/bindings/usb/qcom,dwc3.txt | 104 -------------- .../devicetree/bindings/usb/qcom,dwc3.yaml | 158 +++++++++++++++++++++ 2 files changed, 158 insertions(+), 104 deletions(-) delete mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.txt create mode 100644 Documentation/devicetree/bindings/usb/qcom,dwc3.yamlDocumentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +54
-0@@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SuperSpeed DWC3 USB SoC controller + +maintainers: + - Manu Gautam <[email protected]> + +properties: + compatible: + items: + - enum: + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,sdm845-dwc3 + - const: qcom,dwc3 + + reg: + description: Offset and length of register set for QSCRATCH wrapper + maxItems: 1 + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + power-domains: + description: specifies a phandle to PM domain provider node + maxItems: 1 + + clocks: + description: + A list of phandle and clock-specifier pairs for the clocks + listed in clock-names. + items: + - description: System Config NOC clock. + - description: Master/Core clock, has to be >= 125 MHz + for SS operation and >= 60MHz for HS operation. + - description: System bus AXI clock. + - description: Mock utmi clock needed for ITP/SOF generation + in host mode. Its frequency should be 19.2MHz. + - description: Sleep clock, used for wakeup when + USB3 core goes into low power mode (U3). + + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 64
Quoted 10 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +10
-0+ - const: mock_utmi + - const: sleep + + assigned-clocks: + items: + - description: Phandle and clock specifier of MOCK_UTMI_CLK. + - description: Phandle and clock specifoer of MASTER_CLK. + + assigned-clock-rates: + maxItems: 2
Need to drop this as it is redundant. Soon this will generate an error.
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 66
Quoted 2 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +2
-0+ items: + - description: Must be 19.2MHz (19200000).
Sounds like a constraint:
- const: 19200000
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 67
Quoted 1 line
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +1
-0+ - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
- minimum: 60000000
maximum: ?
Quoted 73 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +73
-0+ + resets: + maxItems: 1 + + interrupts: + items: + - description: The interrupt that is asserted + when a wakeup event is received on USB2 bus. + - description: The interrupt that is asserted + when a wakeup event is received on USB3 bus. + - description: Wakeup event on DM line. + - description: Wakeup event on DP line. + + interrupt-names: + items: + - const: hs_phy_irq + - const: ss_phy_irq + - const: dm_hs_phy_irq + - const: dp_hs_phy_irq + + qcom,select-utmi-as-pipe-clk: + description: + If present, disable USB3 pipe_clk requirement. + Used when dwc3 operates without SSPHY and only + HS/FS/LS modes are supported. + type: boolean + +# Required child node: + +patternProperties: + "^dwc3@[0-9a-f]+$": + type: object + description: + A child node must exist to represent the core DWC3 IP block + The content of the node is defined in dwc3.txt. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - power-domains + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + usb@a6f8800 { + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>;
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 150
Quoted 10 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +10
-0+ interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; + + power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>;
You need 'ranges' in the parent for this address to be translatable.
Quoted 12 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +8
-0+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x740 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + };Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v5 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
Hi Rob,
Quoted 74 lines · Rob Herring
Quoted 73 lines · Sandeep Maheswaram
Convert USB DWC3 bindings to DT schema format using json-schema.
Signed-off-by Sandeep Maheswaram <[email protected]>--- .../devicetree/bindings/usb/qcom,dwc3.txt | 104 -------------- .../devicetree/bindings/usb/qcom,dwc3.yaml | 158 +++++++++++++++++++++ 2 files changed, 158 insertions(+), 104 deletions(-)delete mode 100644
Documentation/devicetree/bindings/usb/qcom,dwc3.txtcreate mode 100644Documentation/devicetree/bindings/usb/qcom,dwc3.yamlDocumentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +57
-0@@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SuperSpeed DWC3 USB SoC controller + +maintainers: + - Manu Gautam <[email protected]> + +properties: + compatible: + items: + - enum: + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,sdm845-dwc3 + - const: qcom,dwc3 + + reg: + description: Offset and length of register set for QSCRATCH wrapper + maxItems: 1 + + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + power-domains: + description: specifies a phandle to PM domain provider node + maxItems: 1 + + clocks: + description: + A list of phandle and clock-specifier pairs for the clocks + listed in clock-names. + items: + - description: System Config NOC clock. + - description: Master/Core clock, has to be >= 125 MHz + for SS operation and >= 60MHz for HS operation. + - description: System bus AXI clock. + - description: Mock utmi clock needed for ITP/SOF generation + in host mode. Its frequency should be 19.2MHz. + - description: Sleep clock, used for wakeup when + USB3 core goes into low power mode (U3). + + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: mock_utmi + - const: sleep +
Quoted 8 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 64
Quoted 7 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +7
-0+ assigned-clocks: + items: + - description: Phandle and clock specifier of MOCK_UTMI_CLK. + - description: Phandle and clock specifoer of MASTER_CLK. + + assigned-clock-rates: + maxItems: 2Need to drop this as it is redundant. Soon this will generate an error.
Will do in next version.
Quoted 9 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 66
Quoted 2 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +2
-0+ items: + - description: Must be 19.2MHz (19200000).Sounds like a constraint:
- const: 19200000
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 67
Quoted 1 line
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +1
-0+ - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.- minimum: 60000000
maximum: ?
Tried as below but facing errors
assigned-clock-rates:
items:
- const: 19200000
- minimum: 60000000
maximum: 150000000
Errors
linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml: usb@a6f8800: assigned-clock-rates: Additional items are not allowed ([150000000] was unexpected) linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml: usb@a6f8800: assigned-clock-rates:0: [19200000] is too short linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml: usb@a6f8800: assigned-clock-rates: [[19200000], [150000000]] is too long
Quoted 76 lines
Quoted 76 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +76
-0+ + resets: + maxItems: 1 + + interrupts: + items: + - description: The interrupt that is asserted + when a wakeup event is received on USB2 bus. + - description: The interrupt that is asserted + when a wakeup event is received on USB3 bus. + - description: Wakeup event on DM line. + - description: Wakeup event on DP line. + + interrupt-names: + items: + - const: hs_phy_irq + - const: ss_phy_irq + - const: dm_hs_phy_irq + - const: dp_hs_phy_irq + + qcom,select-utmi-as-pipe-clk: + description: + If present, disable USB3 pipe_clk requirement. + Used when dwc3 operates without SSPHY and only + HS/FS/LS modes are supported. + type: boolean + +# Required child node: + +patternProperties: + "^dwc3@[0-9a-f]+$": + type: object + description: + A child node must exist to represent the core DWC3 IP block + The content of the node is defined in dwc3.txt. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - power-domains + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + usb@a6f8800 { + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; +
Quoted 8 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 150
Quoted 7 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +7
-0+ power-domains = <&gcc USB30_PRIM_GDSC>; + + resets = <&gcc GCC_USB30_PRIM_BCR>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>;You need 'ranges' in the parent for this address to be translatable.
Will add in next version.
Quoted 13 lines
Quoted 13 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +8
-0+ interrupts = <GIC_SPI 133 IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu 0x740 0>; + snps,dis_u2_susphy_quirk; + snps,dis_enblslpm_quirk; + phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy"; + }; + };Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Signature · 1 line
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v5 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
Hi Rob,
Any suggestions to solve this error in assigned-clock-rates
Regards
Sandeep
Quoted 212 lines · Sandeep Maheswaram (Temp)
Hi Rob,
Quoted 77 lines · Rob Herring
Quoted 76 lines · Sandeep Maheswaram
Convert USB DWC3 bindings to DT schema format using json-schema.
Signed-off-by Sandeep Maheswaram <[email protected]>---
.../devicetree/bindings/usb/qcom,dwc3.txt | 104
--------------
.../devicetree/bindings/usb/qcom,dwc3.yaml | 158
+++++++++++++++++++++2 files changed, 158 insertions(+), 104 deletions(-)delete mode 100644
Documentation/devicetree/bindings/usb/qcom,dwc3.txtcreate mode 100644Documentation/devicetree/bindings/usb/qcom,dwc3.yamlDocumentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +23
-0@@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) + +%YAML 1.2 +--- +$id: http://devicetree.org/schemas/usb/qcom,dwc3.yaml# +$schema: http://devicetree.org/meta-schemas/core.yaml# + +title: Qualcomm SuperSpeed DWC3 USB SoC controller + +maintainers: + - Manu Gautam <[email protected]> + +properties: + compatible: + items: + - enum: + - qcom,msm8996-dwc3 + - qcom,msm8998-dwc3 + - qcom,sdm845-dwc3 + - const: qcom,dwc3 + + reg: + description: Offset and length of register set for QSCRATCHwrapper
+ maxItems: 1Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +33
-0+ + "#address-cells": + enum: [ 1, 2 ] + + "#size-cells": + enum: [ 1, 2 ] + + power-domains: + description: specifies a phandle to PM domain provider node + maxItems: 1 + + clocks: + description: + A list of phandle and clock-specifier pairs for the clocks + listed in clock-names. + items: + - description: System Config NOC clock. + - description: Master/Core clock, has to be >= 125 MHz + for SS operation and >= 60MHz for HS operation. + - description: System bus AXI clock. + - description: Mock utmi clock needed for ITP/SOF generation + in host mode. Its frequency should be 19.2MHz. + - description: Sleep clock, used for wakeup when + USB3 core goes into low power mode (U3). + + clock-names: + items: + - const: cfg_noc + - const: core + - const: iface + - const: mock_utmi + - const: sleep +Quoted 8 lines
Quoted 7 lines
+ assigned-clocks:
+ items:
+ - description: Phandle and clock specifier ofMOCK_UTMI_CLK. + - description: Phandle and clock specifoer ofMASTER_CLK. +
+ assigned-clock-rates:
+ maxItems: 2Need to drop this as it is redundant. Soon this will generate an error.
Will do in next version.
Quoted 10 lines
Quoted 2 lines
+ items:
+ - description: Must be 19.2MHz (19200000).Sounds like a constraint:
- const: 19200000
Quoted 2 lines
+ - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
- minimum: 60000000
maximum: ?Tried as below but facing errors
assigned-clock-rates:
items:
- const: 19200000
- minimum: 60000000
maximum: 150000000Errors
linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml: usb@a6f8800: assigned-clock-rates: Additional items are not allowed ([150000000] was unexpected)linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml: usb@a6f8800: assigned-clock-rates:0: [19200000] is too shortlinux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml: usb@a6f8800: assigned-clock-rates: [[19200000], [150000000]] is too longQuoted 76 lines
Quoted 76 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +76
-0+ + resets: + maxItems: 1 + + interrupts: + items: + - description: The interrupt that is asserted + when a wakeup event is received on USB2 bus. + - description: The interrupt that is asserted + when a wakeup event is received on USB3 bus. + - description: Wakeup event on DM line. + - description: Wakeup event on DP line. + + interrupt-names: + items: + - const: hs_phy_irq + - const: ss_phy_irq + - const: dm_hs_phy_irq + - const: dp_hs_phy_irq + + qcom,select-utmi-as-pipe-clk: + description: + If present, disable USB3 pipe_clk requirement. + Used when dwc3 operates without SSPHY and only + HS/FS/LS modes are supported. + type: boolean + +# Required child node: + +patternProperties: + "^dwc3@[0-9a-f]+$": + type: object + description: + A child node must exist to represent the core DWC3 IP block + The content of the node is defined in dwc3.txt. + +required: + - compatible + - reg + - "#address-cells" + - "#size-cells" + - power-domains + - clocks + - clock-names + +examples: + - | + #include <dt-bindings/clock/qcom,gcc-sdm845.h> + #include <dt-bindings/interrupt-controller/arm-gic.h> + #include <dt-bindings/interrupt-controller/irq.h> + usb@a6f8800 { + compatible = "qcom,sdm845-dwc3", "qcom,dwc3"; + reg = <0 0x0a6f8800 0 0x400>; + + #address-cells = <2>; + #size-cells = <2>; + + clocks = <&gcc GCC_CFG_NOC_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>, + <&gcc GCC_AGGRE_USB3_PRIM_AXI_CLK>, + <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_SLEEP_CLK>; + clock-names = "cfg_noc", "core", "iface", "mock_utmi", + "sleep"; + + assigned-clocks = <&gcc GCC_USB30_PRIM_MOCK_UTMI_CLK>, + <&gcc GCC_USB30_PRIM_MASTER_CLK>; + assigned-clock-rates = <19200000>, <150000000>; + + interrupts = <GIC_SPI 131 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 486 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 488 IRQ_TYPE_LEVEL_HIGH>, + <GIC_SPI 489 IRQ_TYPE_LEVEL_HIGH>; + interrupt-names = "hs_phy_irq", "ss_phy_irq", + "dm_hs_phy_irq", "dp_hs_phy_irq"; +Quoted 8 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 150
Quoted 7 lines
+ power-domains = <&gcc
USB30_PRIM_GDSC>;Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +6
-0+ + resets = <&gcc GCC_USB30_PRIM_BCR>; + + dwc3@a600000 { + compatible = "snps,dwc3"; + reg = <0 0x0a600000 0 0xcd00>;You need 'ranges' in the parent for this address to be translatable.
Will add in next version.
Quoted 13 lines
Quoted 13 lines
+ interrupts = <
GIC_SPI133IRQ_TYPE_LEVEL_HIGH>; + iommus = <&apps_smmu0x7400>;
+ snps,dis_u2_susphy_quirk;
+ snps,dis_enblslpm_quirk;
+ phys = <&usb_1_hsphy>, <&usb_1_ssphy>; + phy-names = "usb2-phy", "usb3-phy";
+ };
+ };Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Signature · 1 line
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v5 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
Quoted 30 lines · Sandeep Maheswaram (Temp)
Hi Rob,
Any suggestions to solve this error in assigned-clock-rates
Quoted 25 lines · Sandeep Maheswaram (Temp)
Hi Rob,
Quoted 22 lines · Rob Herring
Quoted 21 lines · Sandeep Maheswaram
Convert USB DWC3 bindings to DT schema format using json-schema.
Signed-off-by Sandeep Maheswaram <[email protected]>---
.../devicetree/bindings/usb/qcom,dwc3.txt | 104
--------------
.../devicetree/bindings/usb/qcom,dwc3.yaml | 158
+++++++++++++++++++++2 files changed, 158 insertions(+), 104 deletions(-)delete mode 100644
Documentation/devicetree/bindings/usb/qcom,dwc3.txtcreate mode 100644Documentation/devicetree/bindings/usb/qcom,dwc3.yamldiff --git
a/Documentation/devicetree/bindings/usb/qcom,dwc3.yamlb/Documentation/devicetree/bindings/usb/qcom,dwc3.yamlnew file mode 100644
index 0000000..0f69475Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +0
-0
...
Quoted 21 lines
Quoted 21 lines
Quoted 10 lines
Quoted 2 lines
+ items:
+ - description: Must be 19.2MHz (19200000).Sounds like a constraint:
- const: 19200000
Quoted 2 lines
+ - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
- minimum: 60000000
maximum: ?Tried as below but facing errors
assigned-clock-rates:
items:
- const: 19200000
- minimum: 60000000
maximum: 150000000Errors
Quoted 7 lines
Quoted 7 lines
linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml:
usb@a6f8800: assigned-clock-rates: Additional items are not allowed ([150000000] was unexpected)linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml:
usb@a6f8800: assigned-clock-rates:0: [19200000] is too shortlinux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml:
usb@a6f8800: assigned-clock-rates: [[19200000], [150000000]] is too long
judging from the error messages my uneducated guess is that the above rules for assigned-clock-rates expect a single tuple of two elements, not two tuples with a single element, i.e.
assigned-clock-rates = <19200000, 150000000>;
instead of
assigned-clock-rates = <19200000>, <150000000>;
I experimented a bit but couldn't find the magic incantation to appease the schema deities.
Rob, could you please help to distentangle this?
Thanks
Matthias
A message that is not in the archive (sent off-list or not yet received): [email protected]
Re: [PATCH v5 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
Hi Sandeep,
I would suggest to send v6 with the changes Rob and Stephen requested, except for the 'assigned-clock-rate' constraints. A description instead of the constraints is not ideal, but the constraints could be also be added at a later time. Hopefully Rob can either ack with the description or help to resolve the constraints issue.
Regards
Matthias
Quoted 89 lines · Sandeep Maheswaram (Temp)
Hi Rob,
Any suggestions to solve this error in assigned-clock-rates
Regards
SandeepQuoted 76 lines · Matthias Kaehlcke
Quoted 28 lines · Sandeep Maheswaram (Temp)
Hi Rob,
Any suggestions to solve this error in assigned-clock-rates
Quoted 24 lines · Sandeep Maheswaram (Temp)
Hi Rob,
Quoted 21 lines · Rob Herring
Quoted 20 lines · Sandeep Maheswaram
Convert USB DWC3 bindings to DT schema format using json-schema.
Signed-off-by Sandeep Maheswaram <[email protected]>--- .../devicetree/bindings/usb/qcom,dwc3.txt | 104 -------------- .../devicetree/bindings/usb/qcom,dwc3.yaml | 158 +++++++++++++++++++++ 2 files changed, 158 insertions(+), 104 deletions(-)delete mode 100644
Documentation/devicetree/bindings/usb/qcom,dwc3.txt
create mode 100644Documentation/devicetree/bindings/usb/qcom,dwc3.yamldiff --gita/Documentation/devicetree/bindings/usb/qcom,dwc3.yamlb/Documentation/devicetree/bindings/usb/qcom,dwc3.yamlnew file mode 100644
index 0000000..0f69475Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +0
-0...
Quoted 20 lines
Quoted 20 lines
Quoted 10 lines
Quoted 2 lines
+ items:
+ - description: Must be 19.2MHz (19200000).Sounds like a constraint:
- const: 19200000
Quoted 2 lines
+ - description: Must be >= 60 MHz in HS mode, >= 125 MHz in SS mode.
- minimum: 60000000
maximum: ?Tried as below but facing errors
assigned-clock-rates:
items:
- const: 19200000
- minimum: 60000000
maximum: 150000000Errors
Quoted 7 lines
Quoted 7 lines
linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml:
usb@a6f8800: assigned-clock-rates: Additional items are not allowed ([150000000] was unexpected)linux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml:
usb@a6f8800: assigned-clock-rates:0: [19200000] is too shortlinux-next/Documentation/devicetree/bindings/usb/qcom,dwc3.example.dt.yaml:
usb@a6f8800: assigned-clock-rates: [[19200000], [150000000]] is too longjudging from the error messages my uneducated guess is that the above rules for assigned-clock-rates expect a single tuple of two elements, not two tuples with a single element, i.e.
assigned-clock-rates = <19200000, 150000000>;
instead of
assigned-clock-rates = <19200000>, <150000000>;
I experimented a bit but couldn't find the magic incantation to appease the schema deities.
Rob, could you please help to distentangle this?
Thanks
Matthias
Signature · 1 line
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Re: [PATCH v5 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
In reply to Sandeep MaheswaramQuoting Sandeep Maheswaram (2020-03-26 00:06:07)
Quoted 8 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +2
-0@@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +
[...]
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 79
Quoted 10 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +10
-0+ maxItems: 1 + + interrupts: + items: + - description: The interrupt that is asserted + when a wakeup event is received on USB2 bus. + - description: The interrupt that is asserted + when a wakeup event is received on USB3 bus. + - description: Wakeup event on DM line. + - description: Wakeup event on DP line.
I can see that it was optional before but that still doesn't make sense to me. The glue hardware from qcom always has interrupts so I'd expect it to be required in the binding.
Re: [PATCH v5 1/2] dt-bindings: usb: qcom,dwc3: Convert USB DWC3 bindings
Quoted 20 lines · Stephen Boyd
Quoting Sandeep Maheswaram (2020-03-26 00:06:07)
Quoted 8 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +2
-0@@ -0,0 +1,158 @@ +# SPDX-License-Identifier: (GPL-2.0 OR BSD-2-Clause) +[...]
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml line 79
Quoted 10 lines
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml new file +10
-0+ maxItems: 1 + + interrupts: + items: + - description: The interrupt that is asserted + when a wakeup event is received on USB2 bus. + - description: The interrupt that is asserted + when a wakeup event is received on USB3 bus. + - description: Wakeup event on DM line. + - description: Wakeup event on DP line.
Quoted 3 lines
I can see that it was optional before but that still doesn't make sense to me. The glue hardware from qcom always has interrupts so I'd expect it to be required in the binding.
Will add in next version.
Signature · 1 line
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
PATCH v5 2/2 dt-bindings: usb: qcom,dwc3: Add compatible for SC7180
In reply to Sandeep MaheswaramAdd compatible for SC7180 in usb dwc3 bindings.
--- Documentation/devicetree/bindings/usb/qcom,dwc3.yaml | 1 + 1 file changed, 1 insertion(+)
Documentation/devicetree/bindings/usb/qcom,dwc3.yaml +1 -0
@@ -16,6 +16,7 @@ properties: - enum: - qcom,msm8996-dwc3 - qcom,msm8998-dwc3 + - qcom,sc7180-dwc3 - qcom,sdm845-dwc3 - const: qcom,dwc3
Signature · 2 lines
QUALCOMM INDIA, on behalf of Qualcomm Innovation Center, Inc. is a member of Code Aurora Forum, hosted by The Linux Foundation
Quoted 9 lines · Sandeep Maheswaram
Converting dt binding to yaml.
Adding compatible for SC7180 in dt bindings.Changes in v5:
Addressed the comments from Stephen in yaml file.Changes in v4:
Addressed the comments from Doug in yaml file.
Quoted 8 lines
Changes in v3:
Dropped the patch for adding the compatible in dwc3 driver from the series. Addressed the comments from Doug in yaml file.Changes in v2:
Sorted the compatible in dwc3 driver.
Converted dt binding to yaml.
Added compatible in yaml.
now queued for v5.8
Signature · 1 line
balbi