mtd: spi-nor: add xSPI Octal DTR support
Subsystems (5)
v6 cover mtd: spi-nor: add xSPI Octal DTR support
Hi,
This series adds support for octal DTR flashes in the spi-nor framework, and then adds hooks for the Cypress Semper and Mircom Xcella flashes to allow running them in octal DTR mode. This series assumes that the flash is handed to the kernel in Legacy SPI mode.
Tested on TI J721e EVM with 1-bit ECC on the Cypress flash.
Changes in v6:
- Instead of hard-coding 8D-8D-8D Fast Read dummy cycles to 20, find them out from the Profile 1.0 table.
Changes in v5:
- Do not enable stateful X-X-X modes if the reset line is broken.
- Instead of setting SNOR_READ_HWCAPS_8_8_8_DTR from Profile 1.0 table parsing, do it in spi_nor_info_init_params() instead based on the SPI_NOR_OCTAL_DTR_READ flag instead.
- Set SNOR_HWCAPS_PP_8_8_8_DTR in s28hs post_sfdp hook since this capability is no longer set in Profile 1.0 parsing.
- Instead of just checking for spi_nor_get_protocol_width() in spi_nor_octal_dtr_enable(), make sure the protocol is SNOR_PROTO_8_8_8_DTR since get_protocol_width() only cares about data width.
- Drop flag SPI_NOR_SOFT_RESET. Instead, discover soft reset capability via BFPT.
- Do not make an invalid Quad Enable BFPT field a fatal error. Silently ignore it by assuming no quad enable bit is present.
- Set dummy cycles for Cypress Semper flash to 24 instead of 20. This allows for 200MHz operation in 8D mode compared to the 166MHz with 20.
- Rename spi_nor_cypress_octal_enable() to
spi_nor_cypress_octal_dtr_enable().
- Update spi-mtk-nor.c to reject DTR ops since it doesn't call spi_mem_default_supports_op().
Changes in v4:
- Refactor the series to use the new spi-nor framework with the manufacturer-specific bits separated from the core.
- Add support for Micron MT35XU512ABA.
- Use cmd.nbytes as the criteria of whether the data phase exists or not instead of cmd.buf.in || cmd.buf.out in spi_nor_spimem_setup_op().
- Update Read FSR to use the same dummy cycles and address width as Read SR.
- Fix BFPT parsing stopping too early for JESD216 rev B flashes.
- Use 2 byte reads for Read SR and FSR commands in DTR mode.
Changes in v3:
- Drop the DT properties "spi-rx-dtr" and "spi-tx-dtr". Instead, if later a need is felt to disable DTR in case someone has a board with Octal DTR capable flash but does not support DTR transactions for some reason, a property like "spi-no-dtr" can be added.
- Remove mode bits SPI_RX_DTR and SPI_TX_DTR.
- Remove the Cadence Quadspi controller patch to un-block this series. I will submit it as a separate patch.
- Rebase on latest 'master' and fix merge conflicts.
- Update read and write dirmap templates to use DTR.
- Rename 'is_dtr' to 'dtr'.
- Make 'dtr' a bitfield.
- Reject DTR ops in spi_mem_default_supports_op().
- Update atmel-quadspi to reject DTR ops. All other controller drivers call spi_mem_default_supports_op() so they will automatically reject DTR ops.
- Add support for both enabling and disabling DTR modes.
- Perform a Software Reset on flashes that support it when shutting down.
- Disable Octal DTR mode on suspend, and re-enable it on resume.
- Drop enum 'spi_mem_cmd_ext' and make command opcode u16 instead. Update spi-nor to use the 2-byte command instead of the command extension. Since we still need a "extension type", mode that enum to spi-nor and name it 'spi_nor_cmd_ext'.
- Default variable address width to 3 to fix SMPT parsing.
- Drop non-volatile change to uniform sector mode and rely on parsing SMPT.
Changes in v2:
- Add DT properties "spi-rx-dtr" and "spi-tx-dtr" to allow expressing DTR capabilities.
- Set the mode bits SPI_RX_DTR and SPI_TX_DTR when we discover the DT properties "spi-rx-dtr" and spi-tx-dtr".
- spi_nor_cypress_octal_enable() was updating nor->params.read[] with the intention of setting the correct number of dummy cycles. But this function is called _after_ selecting the read so setting nor->params.read[] will have no effect. So, update nor->read_dummy directly.
- Fix spi_nor_spimem_check_readop() and spi_nor_spimem_check_pp() passing nor->read_proto and nor->write_proto to spi_nor_spimem_setup_op() instead of read->proto and pp->proto respectively.
- Move the call to cqspi_setup_opcode_ext() inside cqspi_enable_dtr(). This avoids repeating the 'if (f_pdata->is_dtr) cqspi_setup_opcode_ext()...` snippet multiple times.
- Call the default 'supports_op()' from cqspi_supports_mem_op(). This makes sure the buswidth requirements are also enforced along with the DTR requirements.
- Drop the 'is_dtr' argument from spi_check_dtr_req(). We only call it when a phase is DTR so it is redundant.
Pratyush Yadav (19):
spi: spi-mem: allow specifying whether an op is DTR or not
spi: atmel-quadspi: reject DTR ops
spi: spi-mtk-nor: reject DTR ops
spi: spi-mem: allow specifying a command's extension
mtd: spi-nor: add support for DTR protocol
mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths
mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D
mtd: spi-nor: sfdp: get command opcode extension type from BFPT
mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table
mtd: spi-nor: core: use dummy cycle and address width info from SFDP
mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode
mtd: spi-nor: core: enable octal DTR mode when possible
mtd: spi-nor: sfdp: do not make invalid quad enable fatal
mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT
mtd: spi-nor: core: perform a Soft Reset on shutdown
mtd: spi-nor: core: disable Octal DTR mode on suspend.
mtd: spi-nor: core: expose spi_nor_default_setup() in core.h
mtd: spi-nor: spansion: add support for Cypress Semper flash
mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode
drivers/mtd/spi-nor/core.c | 446 +++++++++++++++++++++++++++----- drivers/mtd/spi-nor/core.h | 22 ++ drivers/mtd/spi-nor/micron-st.c | 112 +++++++- drivers/mtd/spi-nor/sfdp.c | 144 ++++++++++- drivers/mtd/spi-nor/sfdp.h | 13 +- drivers/mtd/spi-nor/spansion.c | 167 ++++++++++++ drivers/spi/atmel-quadspi.c | 4 + drivers/spi/spi-mem.c | 3 + drivers/spi/spi-mtk-nor.c | 4 + include/linux/mtd/spi-nor.h | 53 +++- include/linux/spi/spi-mem.h | 13 +- 11 files changed, 889 insertions(+), 92 deletions(-)
--
2.26.2
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PATCH v6 1/19 spi: spi-mem: allow specifying whether an op is DTR or not
Each phase is given a separate 'dtr' field so mixed protocols like 4S-4D-4D can be supported.
--- drivers/spi/spi-mem.c | 3 +++ include/linux/spi/spi-mem.h | 8 ++++++++ 2 files changed, 11 insertions(+)
drivers/spi/spi-mem.c +3 -0
@@ -156,6 +156,9 @@ bool spi_mem_default_supports_op(struct spi_mem *mem, op->data.dir == SPI_MEM_DATA_OUT))return false; +if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) +return false; +return true; }EXPORT_SYMBOL_GPL (spi_mem_default_supports_op);
include/linux/spi/spi-mem.h +8 -0
@@ -71,9 +71,11 @@ enum spi_mem_data_dir {* struct spi_mem_op - describes a SPI memory operation * @cmd.buswidth: number of IO lines used to transmit the command * @cmd.opcode: operation opcode +* @cmd.dtr: whether the command opcode should be sent in DTR mode or not * @addr.nbytes: number of address bytes to send. Can be zero if the operation * does not need to send an address * @addr.buswidth: number of IO lines used to transmit the address cycles +* @addr.dtr: whether the address should be sent in DTR mode or not * @addr.val: address value. This value is always sent MSB first on the bus. * Note that only @addr.nbytes are taken into account in this * address value, so users should make sure the value fits in the
@@ -81,7 +83,9 @@ enum spi_mem_data_dir {* @dummy.nbytes: number of dummy bytes to send after an opcode or address. Can * be zero if the operation does not require dummy bytes * @dummy.buswidth: number of IO lanes used to transmit the dummy bytes +* @dummy.dtr: whether the dummy bytes should be sent in DTR mode or not * @data.buswidth: number of IO lanes used to send/receive the data +* @data.dtr: whether the data should be sent in DTR mode or not * @data.dir: direction of the transfer * @data.nbytes: number of data bytes to send/receive. Can be zero if the * operation does not involve transferring data
@@ -91,22 +95,26 @@ enum spi_mem_data_dir { struct spi_mem_op { struct { u8 buswidth; + u8 dtr : 1; u8 opcode; } cmd; struct { u8 nbytes; u8 buswidth; + u8 dtr : 1; u64 val; } addr; struct { u8 nbytes; u8 buswidth; + u8 dtr : 1; } dummy; struct { u8 buswidth; + u8 dtr : 1; enum spi_mem_data_dir dir; unsigned int nbytes; union {
Signature · 1 line
2.26.2
PATCH v6 2/19 spi: atmel-quadspi: reject DTR ops
In reply to Pratyush YadavDouble Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op().
--- drivers/spi/atmel-quadspi.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/spi/atmel-quadspi.c +4 -0
@@ -285,6 +285,10 @@ static bool atmel_qspi_supports_op(struct spi_mem *mem, op->dummy.nbytes == 0)return false; +/* DTR ops not supported. */ +if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) +return false; +return true; }
Signature · 1 line
2.26.2
PATCH v6 3/19 spi: spi-mtk-nor: reject DTR ops
In reply to Pratyush YadavDouble Transfer Rate (DTR) ops are added in spi-mem. But this controller doesn't support DTR transactions. Since we don't use the default supports_op(), which rejects all DTR ops, do that explicitly in our supports_op().
--- drivers/spi/spi-mtk-nor.c | 4 ++++ 1 file changed, 4 insertions(+)
drivers/spi/spi-mtk-nor.c +4 -0
@@ -211,6 +211,10 @@ static bool mtk_nor_supports_op(struct spi_mem *mem,if (op->cmd.buswidth !=1 )return false; +/* DTR ops not supported. */ +if (op->cmd.dtr || op->addr.dtr || op->dummy.dtr || op->data.dtr) +return false; +if ((op->addr.nbytes ==3 ) || (op->addr.nbytes ==4 )) {if ((op->data.dir ==SPI_MEM_DATA_IN ) &&mtk_nor_match_read (op))return true;
Signature · 1 line
2.26.2
PATCH v6 4/19 spi: spi-mem: allow specifying a command's extension
In reply to Pratyush YadavIn xSPI mode, flashes expect 2-byte opcodes. The second byte is called the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same opcode is sent twice. When it is "invert", the second byte is the inverse of the opcode. When it is "hex" an additional opcode byte based is sent with the command whose value can be anything.
So, make opcode a 16-bit value and add a 'nbytes', similar to how multiple address widths are handled.
--- include/linux/spi/spi-mem.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)
include/linux/spi/spi-mem.h +4 -1
@@ -69,6 +69,8 @@ enum spi_mem_data_dir {/** * struct spi_mem_op - describes a SPI memory operation +* @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is +* sent MSB-first. * @cmd.buswidth: number of IO lines used to transmit the command * @cmd.opcode: operation opcode * @cmd.dtr: whether the command opcode should be sent in DTR mode or not
@@ -94,9 +96,10 @@ enum spi_mem_data_dir {*/ struct spi_mem_op {struct { +u8 nbytes;u8 buswidth;u8 dtr :1 ; -u8 opcode; +u16 opcode; } cmd;struct {
Signature · 1 line
2.26.2
Re: [PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension
Quoted 30 lines · On Wed, 20 May 2020 22:00:38 +0530 Pratyush Yadav <[email protected]> wrote:
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same opcode is sent twice. When it is "invert", the second byte is the inverse of the opcode. When it is "hex" an additional opcode byte based is sent with the command whose value can be anything.So, make opcode a 16-bit value and add a 'nbytes', similar to how multiple address widths are handled.
Signed-off-by Pratyush Yadav <[email protected]>--- include/linux/spi/spi-mem.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)include/linux/spi/spi-mem.h +2
-0@@ -69,6 +69,8 @@ enum spi_mem_data_dir {/** * struct spi_mem_op - describes a SPI memory operation +* @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is +* sent MSB-first. * @cmd.buswidth: number of IO lines used to transmit the command * @cmd.opcode: operation opcode * @cmd.dtr: whether the command opcode should be sent in DTR mode or not @@ -94,9 +96,10 @@ enum spi_mem_data_dir {*/
include/linux/spi/spi-mem.h enum spi_mem_data_dir { · line 105
Quoted 10 lines
include/linux/spi/spi-mem.h +2
-1struct spi_mem_op {struct { +u8 nbytes;u8 buswidth;u8 dtr :1 ; -u8 opcode; +u16 opcode; } cmd;struct {
As mentioned in one of my previous review, you should patch the mxic driver before extending the opcode field:
--->8---
drivers/spi/spi-mxic.c +5 -1
@@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,int nio =1 , i, ret;u32 ss_ctrl;u8 addr[8 ]; +u8 cmd[2 ]; ret =mxic_spi_set_freq (mxic, mem->spi->max_speed_hz);if (ret)
@@ -393,7 +394,10 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,writel (readl (mxic->regs +HC_CFG ) |HC_CFG_MAN_CS_ASSERT , mxic->regs +HC_CFG ); - ret =mxic_spi_data_xfer (mxic, &op->cmd.opcode,NULL ,1 ); +for (i =0 ; i < op->cmd.nbytes; i++) + cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i -1 )); + + ret =mxic_spi_data_xfer (mxic, cmd,NULL , op->cmd.nbytes);if (ret) goto out;
Re: [PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension
Quoted 42 lines · Boris Brezillon
Quoted 39 lines · On Wed, 20 May 2020 22:00:38 +0530 Pratyush Yadav <[email protected]> wrote:
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same opcode is sent twice. When it is "invert", the second byte is the inverse of the opcode. When it is "hex" an additional opcode byte based is sent with the command whose value can be anything.So, make opcode a 16-bit value and add a 'nbytes', similar to how multiple address widths are handled.
Signed-off-by Pratyush Yadav <[email protected]>--- include/linux/spi/spi-mem.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)include/linux/spi/spi-mem.h +4
-1@@ -69,6 +69,8 @@ enum spi_mem_data_dir {/** * struct spi_mem_op - describes a SPI memory operation +* @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is +* sent MSB-first. * @cmd.buswidth: number of IO lines used to transmit the command * @cmd.opcode: operation opcode * @cmd.dtr: whether the command opcode should be sent in DTR mode or not @@ -94,9 +96,10 @@ enum spi_mem_data_dir {*/ struct spi_mem_op {struct { +u8 nbytes;u8 buswidth;u8 dtr :1 ; -u8 opcode; +u16 opcode; } cmd;
Quoted 4 lines
include/linux/spi/spi-mem.h enum spi_mem_data_dir { · line 105
Quoted 1 line
include/linux/spi/spi-mem.h +0
-0struct {As mentioned in one of my previous review, you should patch the mxic driver before extending the opcode field:
IIUC, this patchset doesn't break original functionality of the driver. It will work like before with 1-byte opcodes. So I don't think it is the responsibility of this patchset to enhance the driver. It didn't work before with 2-byte opcodes, it won't work now. IMO this should be a separate, independent change.
Quoted 25 lines
--->8---
drivers/spi/spi-mxic.c +5
-1@@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,int nio =1 , i, ret;u32 ss_ctrl;u8 addr[8 ]; +u8 cmd[2 ]; ret =mxic_spi_set_freq (mxic, mem->spi->max_speed_hz);if (ret)@@ -393,7 +394,10 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,writel (readl (mxic->regs +HC_CFG ) |HC_CFG_MAN_CS_ASSERT , mxic->regs +HC_CFG ); - ret =mxic_spi_data_xfer (mxic, &op->cmd.opcode,NULL ,1 ); +for (i =0 ; i < op->cmd.nbytes; i++) + cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i -1 )); + + ret =mxic_spi_data_xfer (mxic, cmd,NULL , op->cmd.nbytes);if (ret) goto out;
Signature · 7 lines
Regards, Pratyush Yadav Texas Instruments India ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
Re: [PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension
Quoted 48 lines · Pratyush Yadav
Quoted 42 lines · Boris Brezillon
Quoted 39 lines · On Wed, 20 May 2020 22:00:38 +0530 Pratyush Yadav <[email protected]> wrote:
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same opcode is sent twice. When it is "invert", the second byte is the inverse of the opcode. When it is "hex" an additional opcode byte based is sent with the command whose value can be anything.So, make opcode a 16-bit value and add a 'nbytes', similar to how multiple address widths are handled.
Signed-off-by Pratyush Yadav <[email protected]>--- include/linux/spi/spi-mem.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)include/linux/spi/spi-mem.h +4
-1@@ -69,6 +69,8 @@ enum spi_mem_data_dir {/** * struct spi_mem_op - describes a SPI memory operation +* @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is +* sent MSB-first. * @cmd.buswidth: number of IO lines used to transmit the command * @cmd.opcode: operation opcode * @cmd.dtr: whether the command opcode should be sent in DTR mode or not @@ -94,9 +96,10 @@ enum spi_mem_data_dir {*/ struct spi_mem_op {struct { +u8 nbytes;u8 buswidth;u8 dtr :1 ; -u8 opcode; +u16 opcode; } cmd;Quoted 4 lines
include/linux/spi/spi-mem.h enum spi_mem_data_dir { · line 105
Quoted 1 line
include/linux/spi/spi-mem.h +0
-0struct {As mentioned in one of my previous review, you should patch the mxic driver before extending the opcode field:
Quoted 5 lines
IIUC, this patchset doesn't break original functionality of the driver. It will work like before with 1-byte opcodes. So I don't think it is the responsibility of this patchset to enhance the driver. It didn't work before with 2-byte opcodes, it won't work now. IMO this should be a separate, independent change.
Scratch that. Big/little endian issue. If you'd drop your Signed-off-by, I'll write the commit message and patch it in.
Quoted 25 lines
Quoted 25 lines
--->8---
drivers/spi/spi-mxic.c +5
-1@@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,int nio =1 , i, ret;u32 ss_ctrl;u8 addr[8 ]; +u8 cmd[2 ]; ret =mxic_spi_set_freq (mxic, mem->spi->max_speed_hz);if (ret)@@ -393,7 +394,10 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,writel (readl (mxic->regs +HC_CFG ) |HC_CFG_MAN_CS_ASSERT , mxic->regs +HC_CFG ); - ret =mxic_spi_data_xfer (mxic, &op->cmd.opcode,NULL ,1 ); +for (i =0 ; i < op->cmd.nbytes; i++) + cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i -1 )); + + ret =mxic_spi_data_xfer (mxic, cmd,NULL , op->cmd.nbytes);if (ret) goto out;
Signature · 7 lines
Regards, Pratyush Yadav Texas Instruments India ______________________________________________________ Linux MTD discussion mailing list http://lists.infradead.org/mailman/listinfo/linux-mtd/
Re: [PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension
Quoted 49 lines · On Fri, 22 May 2020 01:33:15 +0530 Pratyush Yadav <[email protected]> wrote:
Quoted 48 lines · Pratyush Yadav
Quoted 46 lines · Boris Brezillon
Quoted 30 lines · On Wed, 20 May 2020 22:00:38 +0530 Pratyush Yadav <[email protected]> wrote:
In xSPI mode, flashes expect 2-byte opcodes. The second byte is called the "command extension". There can be 3 types of extensions in xSPI:
repeat, invert, and hex. When the extension type is "repeat", the same opcode is sent twice. When it is "invert", the second byte is the inverse of the opcode. When it is "hex" an additional opcode byte based is sent with the command whose value can be anything.So, make opcode a 16-bit value and add a 'nbytes', similar to how multiple address widths are handled.
Signed-off-by Pratyush Yadav <[email protected]>--- include/linux/spi/spi-mem.h | 5 ++++- 1 file changed, 4 insertions(+), 1 deletion(-)include/linux/spi/spi-mem.h +2
-0@@ -69,6 +69,8 @@ enum spi_mem_data_dir {/** * struct spi_mem_op - describes a SPI memory operation +* @cmd.nbytes: number of opcode bytes (only 1 or 2 are valid). The opcode is +* sent MSB-first. * @cmd.buswidth: number of IO lines used to transmit the command * @cmd.opcode: operation opcode * @cmd.dtr: whether the command opcode should be sent in DTR mode or not @@ -94,9 +96,10 @@ enum spi_mem_data_dir {*/ include/linux/spi/spi-mem.h enum spi_mem_data_dir { · line 105
Quoted 10 lines
include/linux/spi/spi-mem.h +2
-1struct spi_mem_op {struct { +u8 nbytes;u8 buswidth;u8 dtr :1 ; -u8 opcode; +u16 opcode; } cmd;struct {As mentioned in one of my previous review, you should patch the mxic driver before extending the opcode field:
Quoted 8 lines
Quoted 5 lines
IIUC, this patchset doesn't break original functionality of the driver. It will work like before with 1-byte opcodes. So I don't think it is the responsibility of this patchset to enhance the driver. It didn't work before with 2-byte opcodes, it won't work now. IMO this should be a separate, independent change.
Scratch that. Big/little endian issue. If you'd drop your Signed-off-by, I'll write the commit message and patch it in.
Just add a Suggested-by, that should be fine.
Quoted 27 lines
Quoted 26 lines
Quoted 26 lines
--->8---
drivers/spi/spi-mxic.c +5
-1@@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,int nio =1 , i, ret;u32 ss_ctrl;u8 addr[8 ]; +u8 cmd[2 ]; ret =mxic_spi_set_freq (mxic, mem->spi->max_speed_hz);if (ret)@@ -393,7 +394,10 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,writel (readl (mxic->regs +HC_CFG ) |HC_CFG_MAN_CS_ASSERT , mxic->regs +HC_CFG ); - ret =mxic_spi_data_xfer (mxic, &op->cmd.opcode,NULL ,1 ); +for (i =0 ; i < op->cmd.nbytes; i++) + cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i -1 )); + + ret =mxic_spi_data_xfer (mxic, cmd,NULL , op->cmd.nbytes);if (ret) goto out;
Re: [PATCH v6 04/19] spi: spi-mem: allow specifying a command's extension
In reply to Boris BrezillonHi Boris,
Quoted 12 lines · Boris Brezillon
On Wed, 20 May 2020 22:00:38 +0530
Pratyush Yadav <[email protected]> wrote:As mentioned in one of my previous review, you should patch the mxic driver before extending the opcode field:
--->8---
drivers/spi/spi-mxic.c +0
-0
drivers/spi/spi-mxic.c static int mxic_spi_mem_exec_op(struct spi_mem *mem, · line 359
Quoted 4 lines
drivers/spi/spi-mxic.c +1
-0@@ -356,6 +356,7 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,int nio =1 , i, ret;u32 ss_ctrl;u8 addr[8 ]; +u8 cmd[2 ];
Regarding your comment about bisect-ability, how about I change this to:
u8 cmd[sizeof(op->cmd.opcode)];
and put this patch before the change to 2-byte opcodes. This should also make it resistent to further changes in opcode size. Does that sound like a sane idea?
Quoted 14 lines
drivers/spi/spi-mxic.c +4
-1ret =mxic_spi_set_freq (mxic, mem->spi->max_speed_hz);if (ret)@@ -393,7 +394,10 @@ static int mxic_spi_mem_exec_op(struct spi_mem *mem,writel (readl (mxic->regs +HC_CFG ) |HC_CFG_MAN_CS_ASSERT , mxic->regs +HC_CFG ); - ret =mxic_spi_data_xfer (mxic, &op->cmd.opcode,NULL ,1 ); +for (i =0 ; i < op->cmd.nbytes; i++) + cmd[i] = op->cmd.opcode >> (8 * (op->cmd.nbytes - i -1 )); + + ret =mxic_spi_data_xfer (mxic, cmd,NULL , op->cmd.nbytes);if (ret) goto out;
Signature · 8 lines
Regards, Pratyush Yadav Texas Instruments India _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel
PATCH v6 5/19 mtd: spi-nor: add support for DTR protocol
In reply to Pratyush YadavDouble Transfer Rate (DTR) is SPI protocol in which data is transferred on each clock edge as opposed to on each clock cycle. Make framework-level changes to allow supporting flashes in DTR mode.
Right now, mixed DTR modes are not supported. So, for example a mode like 4S-4D-4D will not work. All phases need to be either DTR or STR.
--- drivers/mtd/spi-nor/core.c | 305 ++++++++++++++++++++++++++++-------- drivers/mtd/spi-nor/core.h | 6 + drivers/mtd/spi-nor/sfdp.c | 9 +- include/linux/mtd/spi-nor.h | 51 ++++-- 4 files changed, 295 insertions(+), 76 deletions(-)
drivers/mtd/spi-nor/core.c +243 -62
@@ -40,6 +40,76 @@#define SPI_NOR_MAX_ADDR_WIDTH 4 +/** +* spi_nor_get_cmd_ext() - Get the command opcode extension based on the +* extension type. +* @nor: pointer to a 'struct spi_nor' +* @op: pointer to the 'struct spi_mem_op' whose properties +* need to be initialized. +* +* Right now, only "repeat" and "invert" are supported. +* +* Return: The opcode extension. +*/ +static u8 spi_nor_get_cmd_ext (const struct spi_nor *nor, +const struct spi_mem_op *op) +{ +switch (nor->cmd_ext_type) { +case SPI_NOR_EXT_INVERT : +return ~op->cmd.opcode; + +case SPI_NOR_EXT_REPEAT : +return op->cmd.opcode; + +default : +dev_err (nor->dev,"Unknown command extension type\n" ); +return 0 ; + } +} + +/** +* spi_nor_spimem_setup_op() - Set up common properties of a spi-mem op. +* @nor: pointer to a 'struct spi_nor' +* @op: pointer to the 'struct spi_mem_op' whose properties +* need to be initialized. +* @proto: the protocol from which the properties need to be set. +*/ +void spi_nor_spimem_setup_op (const struct spi_nor *nor, +struct spi_mem_op *op, +const enum spi_nor_protocol proto) +{ +u8 ext; + + op->cmd.buswidth =spi_nor_get_protocol_inst_nbits (proto); + +if (op->addr.nbytes) + op->addr.buswidth =spi_nor_get_protocol_addr_nbits (proto); + +if (op->dummy.nbytes) + op->dummy.buswidth =spi_nor_get_protocol_addr_nbits (proto); + +if (op->data.nbytes) + op->data.buswidth =spi_nor_get_protocol_data_nbits (proto); + +if (spi_nor_protocol_is_dtr (proto)) { +/* +* spi-mem supports mixed DTR modes, but right now we can only +* have all phases either DTR or STR. IOW, spi-mem can have +* something like 4S-4D-4D, but spi-nor can't. So, set all 4 +* phases to either DTR or STR. +*/ + op->cmd.dtr = op->addr.dtr = op->dummy.dtr + = op->data.dtr = true; + +/* 2 bytes per clock cycle in DTR mode. */ + op->dummy.nbytes *=2 ; + + ext =spi_nor_get_cmd_ext (nor, op); + op->cmd.opcode = (op->cmd.opcode <<8 ) | ext; + op->cmd.nbytes =2 ; + } +} +/** * spi_nor_spimem_bounce() - check if a bounce buffer is needed for the data * transfer
@@ -104,14 +174,12 @@ static ssize_t spi_nor_spimem_read_data(struct spi_nor *nor, loff_t from,ssize_t nbytes;int error; -/* get transfer protocols. */ - op.cmd.buswidth =spi_nor_get_protocol_inst_nbits (nor->read_proto); - op.addr.buswidth =spi_nor_get_protocol_addr_nbits (nor->read_proto); - op.dummy.buswidth = op.addr.buswidth; - op.data.buswidth =spi_nor_get_protocol_data_nbits (nor->read_proto); +spi_nor_spimem_setup_op (nor, &op, nor->read_proto);/* convert the dummy cycles to the number of bytes */ op.dummy.nbytes = (nor->read_dummy * op.dummy.buswidth) /8 ; +if (spi_nor_protocol_is_dtr (nor->read_proto)) + op.dummy.nbytes *=2 ; usebouncebuf =spi_nor_spimem_bounce (nor, &op);
@@ -169,13 +237,11 @@ static ssize_t spi_nor_spimem_write_data(struct spi_nor *nor, loff_t to,ssize_t nbytes;int error; - op.cmd.buswidth =spi_nor_get_protocol_inst_nbits (nor->write_proto); - op.addr.buswidth =spi_nor_get_protocol_addr_nbits (nor->write_proto); - op.data.buswidth =spi_nor_get_protocol_data_nbits (nor->write_proto); -if (nor->program_opcode ==SPINOR_OP_AAI_WP && nor->sst_write_second) op.addr.nbytes =0 ; +spi_nor_spimem_setup_op (nor, &op, nor->write_proto); +if (spi_nor_spimem_bounce (nor, &op))memcpy (nor->bouncebuf, buf, op.data.nbytes);
@@ -227,10 +293,16 @@ int spi_nor_write_enable(struct spi_nor *nor)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_NO_DATA); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->write_reg (nor,SPINOR_OP_WREN , -NULL ,0 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->write_reg (nor, +SPINOR_OP_WREN , +NULL ,0 ); }if (ret)
@@ -256,10 +328,16 @@ int spi_nor_write_disable(struct spi_nor *nor)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_NO_DATA); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->write_reg (nor,SPINOR_OP_WRDI , -NULL ,0 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->write_reg (nor, +SPINOR_OP_WRDI , +NULL ,0 ); }if (ret)
@@ -318,10 +396,15 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_IN(1, fsr, 1)); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->read_reg (nor,SPINOR_OP_RDFSR , - fsr,1 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->read_reg (nor,SPINOR_OP_RDFSR , + fsr,1 ); }if (ret)
@@ -350,9 +433,15 @@ static int spi_nor_read_cr(struct spi_nor *nor, u8 *cr)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_IN(1, cr, 1)); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->read_reg (nor,SPINOR_OP_RDCR , cr,1 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->read_reg (nor,SPINOR_OP_RDCR , + cr,1 ); }if (ret)
@@ -383,12 +472,17 @@ int spi_nor_set_4byte_addr_mode(struct spi_nor *nor, bool enable)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_NO_DATA); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->write_reg (nor, - enable ?SPINOR_OP_EN4B : -SPINOR_OP_EX4B , -NULL ,0 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->write_reg (nor, + enable ?SPINOR_OP_EN4B : +SPINOR_OP_EX4B , +NULL ,0 ); }if (ret)
@@ -419,10 +513,15 @@ static int spansion_set_4byte_addr_mode(struct spi_nor *nor, bool enable)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->write_reg (nor,SPINOR_OP_BRWR , - nor->bouncebuf,1 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->write_reg (nor,SPINOR_OP_BRWR , + nor->bouncebuf,1 ); }if (ret)
@@ -451,10 +550,16 @@ int spi_nor_write_ear(struct spi_nor *nor, u8 ear)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_OUT(1, nor->bouncebuf, 1)); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->write_reg (nor,SPINOR_OP_WREAR , - nor->bouncebuf,1 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->write_reg (nor, +SPINOR_OP_WREAR , + nor->bouncebuf,1 ); }if (ret)
@@ -482,10 +587,16 @@ int spi_nor_xread_sr(struct spi_nor *nor, u8 *sr)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_IN(1, sr, 1)); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->read_reg (nor,SPINOR_OP_XRDSR , - sr,1 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->read_reg (nor, +SPINOR_OP_XRDSR , + sr,1 ); }if (ret)
@@ -527,10 +638,16 @@ static void spi_nor_clear_sr(struct spi_nor *nor)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_NO_DATA); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->write_reg (nor,SPINOR_OP_CLSR , -NULL ,0 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->write_reg (nor, +SPINOR_OP_CLSR , +NULL ,0 ); }if (ret)
@@ -591,10 +708,16 @@ static void spi_nor_clear_fsr(struct spi_nor *nor)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_NO_DATA); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->write_reg (nor,SPINOR_OP_CLFSR , -NULL ,0 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->write_reg (nor, +SPINOR_OP_CLFSR , +NULL ,0 ); }if (ret)
@@ -735,10 +858,16 @@ static int spi_nor_write_sr(struct spi_nor *nor, const u8 *sr, size_t len)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_OUT(len, sr, 1)); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->write_reg (nor,SPINOR_OP_WRSR , - sr, len); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->write_reg (nor, +SPINOR_OP_WRSR , + sr, len); }if (ret) {
@@ -937,10 +1066,16 @@ static int spi_nor_write_sr2(struct spi_nor *nor, const u8 *sr2)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_OUT(1, sr2, 1)); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->write_reg (nor,SPINOR_OP_WRSR2 , - sr2,1 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->write_reg (nor, +SPINOR_OP_WRSR2 , + sr2,1 ); }if (ret) {
@@ -971,10 +1106,16 @@ static int spi_nor_read_sr2(struct spi_nor *nor, u8 *sr2)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_IN(1, sr2, 1)); +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->read_reg (nor,SPINOR_OP_RDSR2 , - sr2,1 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->read_reg (nor, +SPINOR_OP_RDSR2 , + sr2,1 ); }if (ret)
@@ -1002,10 +1143,16 @@ static int spi_nor_erase_chip(struct spi_nor *nor)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_NO_DATA); +spi_nor_spimem_setup_op (nor, &op, nor->write_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->write_reg (nor,SPINOR_OP_CHIP_ERASE , -NULL ,0 ); +if (spi_nor_protocol_is_dtr (nor->write_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->write_reg (nor, +SPINOR_OP_CHIP_ERASE , +NULL ,0 ); }if (ret)
@@ -1144,7 +1291,11 @@ static int spi_nor_erase_sector(struct spi_nor *nor, u32 addr)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_NO_DATA); +spi_nor_spimem_setup_op (nor, &op, nor->write_proto); +return spi_mem_exec_op (nor->spimem, &op); + }else if (spi_nor_protocol_is_dtr (nor->write_proto)) { +return -ENOTSUPP ; }else if (nor->controller_ops->erase) {return nor->controller_ops->erase (nor, addr); }
@@ -2253,6 +2404,7 @@ int spi_nor_hwcaps_read2cmd(u32 hwcaps) { SNOR_HWCAPS_READ_1_8_8, SNOR_CMD_READ_1_8_8 }, { SNOR_HWCAPS_READ_8_8_8, SNOR_CMD_READ_8_8_8 }, { SNOR_HWCAPS_READ_1_8_8_DTR, SNOR_CMD_READ_1_8_8_DTR }, + { SNOR_HWCAPS_READ_8_8_8_DTR, SNOR_CMD_READ_8_8_8_DTR }, }; return spi_nor_hwcaps2cmd(hwcaps, hwcaps_read2cmd,
@@ -2269,6 +2421,7 @@ static int spi_nor_hwcaps_pp2cmd(u32 hwcaps) { SNOR_HWCAPS_PP_1_1_8, SNOR_CMD_PP_1_1_8 }, { SNOR_HWCAPS_PP_1_8_8, SNOR_CMD_PP_1_8_8 }, { SNOR_HWCAPS_PP_8_8_8, SNOR_CMD_PP_8_8_8 }, + { SNOR_HWCAPS_PP_8_8_8_DTR, SNOR_CMD_PP_8_8_8_DTR }, }; return spi_nor_hwcaps2cmd(hwcaps, hwcaps_pp2cmd,
@@ -2322,13 +2475,11 @@ static int spi_nor_spimem_check_readop(struct spi_nor *nor,SPI_MEM_OP_DUMMY (0 ,1 ), SPI_MEM_OP_DATA_IN(0, NULL, 1)); - op.cmd.buswidth =spi_nor_get_protocol_inst_nbits (read->proto); - op.addr.buswidth =spi_nor_get_protocol_addr_nbits (read->proto); - op.data.buswidth =spi_nor_get_protocol_data_nbits (read->proto); - op.dummy.buswidth = op.addr.buswidth; op.dummy.nbytes = (read->num_mode_clocks + read->num_wait_states) * op.dummy.buswidth /8 ; +spi_nor_spimem_setup_op (nor, &op, read->proto); +return spi_nor_spimem_check_op (nor, &op); }
@@ -2348,9 +2499,7 @@ static int spi_nor_spimem_check_pp(struct spi_nor *nor,SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_OUT(0, NULL, 1)); - op.cmd.buswidth =spi_nor_get_protocol_inst_nbits (pp->proto); - op.addr.buswidth =spi_nor_get_protocol_addr_nbits (pp->proto); - op.data.buswidth =spi_nor_get_protocol_data_nbits (pp->proto); +spi_nor_spimem_setup_op (nor, &op, pp->proto);return spi_nor_spimem_check_op (nor, &op); }
@@ -2368,12 +2517,16 @@ spi_nor_spimem_adjust_hwcaps(struct spi_nor *nor, u32 *hwcaps)struct spi_nor_flash_parameter *params = nor->params;unsigned int cap; -/* DTR modes are not supported yet, mask them all. */ - *hwcaps &= ~SNOR_HWCAPS_DTR ; -/* X-X-X modes are not supported yet, mask them all. */ *hwcaps &= ~SNOR_HWCAPS_X_X_X ; +/* +* If the reset line is broken, we do not want to enter a stateful +* mode. +*/ +if (nor->flags &SNOR_F_BROKEN_RESET ) + *hwcaps &= ~(SNOR_HWCAPS_X_X_X |SNOR_HWCAPS_X_X_X_DTR ); +for (cap =0 ; cap <sizeof (*hwcaps) *BITS_PER_BYTE ; cap++) {int rdidx, ppidx;
@@ -2628,7 +2781,7 @@ static int spi_nor_default_setup(struct spi_nor *nor,* controller directly implements the spi_nor interface. * Yet another reason to switch to spi-mem. */ - ignored_mask =SNOR_HWCAPS_X_X_X ; + ignored_mask =SNOR_HWCAPS_X_X_X |SNOR_HWCAPS_X_X_X_DTR ;if (shared_mask & ignored_mask) {dev_dbg (nor->dev,"SPI n-n-n protocols are not supported.\n" );
@@ -2774,11 +2927,25 @@ static void spi_nor_info_init_params(struct spi_nor *nor) SNOR_PROTO_1_1_8); } +if (info->flags &SPI_NOR_OCTAL_DTR_READ ) { + params->hwcaps.mask |=SNOR_HWCAPS_READ_8_8_8_DTR ; +spi_nor_set_read_settings (¶ms->reads[SNOR_CMD_READ_8_8_8_DTR ], +0 ,20 ,SPINOR_OP_READ_FAST , +SNOR_PROTO_8_8_8_DTR ); + } +/* Page Program settings. */ params->hwcaps.mask |=SNOR_HWCAPS_PP ;spi_nor_set_pp_settings (¶ms->page_programs[SNOR_CMD_PP ],SPINOR_OP_PP ,SNOR_PROTO_1_1_1 ); +/* +* Since xSPI Page Program opcode is backward compatible with +* Legacy SPI, use Legacy SPI opcode there as well. +*/ +spi_nor_set_pp_settings (¶ms->page_programs[SNOR_CMD_PP_8_8_8_DTR ], +SPINOR_OP_PP ,SNOR_PROTO_8_8_8_DTR ); +/* * Sector Erase settings. Sort Erase Types in ascending order, with the * smallest erase size starting at BIT(0).
@@ -2886,7 +3053,8 @@ static int spi_nor_init_params(struct spi_nor *nor)spi_nor_manufacturer_init_params (nor); -if ((nor->info->flags & (SPI_NOR_DUAL_READ |SPI_NOR_QUAD_READ )) && +if ((nor->info->flags & (SPI_NOR_DUAL_READ |SPI_NOR_QUAD_READ | +SPI_NOR_OCTAL_READ |SPI_NOR_OCTAL_DTR_READ )) && !(nor->info->flags &SPI_NOR_SKIP_SFDP ))spi_nor_sfdp_init_params (nor);
@@ -2948,7 +3116,9 @@ static int spi_nor_init(struct spi_nor *nor)return err; } -if (nor->addr_width ==4 && !(nor->flags &SNOR_F_4B_OPCODES )) { +if (nor->addr_width ==4 && + !(nor->info->flags &SPI_NOR_OCTAL_DTR_READ ) && + !(nor->flags &SNOR_F_4B_OPCODES )) {/* * If the RESET# pin isn't hooked up properly, or the system * otherwise doesn't perform a reset command in the boot
@@ -3007,6 +3177,9 @@ static int spi_nor_set_addr_width(struct spi_nor *nor) {if (nor->addr_width) {/* already configured from SFDP */ + }else if (spi_nor_protocol_is_dtr (nor->read_proto)) { +/* Always use 4-byte addresses in DTR mode. */ + nor->addr_width =4 ; }else if (nor->info->addr_width) { nor->addr_width = nor->info->addr_width; }else if (nor->mtd.size >0x1000000 ) {
@@ -3244,14 +3417,19 @@ static int spi_nor_create_read_dirmap(struct spi_nor *nor) };struct spi_mem_op *op = &info.op_tmpl; -/* get transfer protocols. */ - op->cmd.buswidth =spi_nor_get_protocol_inst_nbits (nor->read_proto); - op->addr.buswidth =spi_nor_get_protocol_addr_nbits (nor->read_proto); - op->dummy.buswidth = op->addr.buswidth; - op->data.buswidth =spi_nor_get_protocol_data_nbits (nor->read_proto); +spi_nor_spimem_setup_op (nor, op, nor->read_proto);/* convert the dummy cycles to the number of bytes */ op->dummy.nbytes = (nor->read_dummy * op->dummy.buswidth) /8 ; +if (spi_nor_protocol_is_dtr (nor->read_proto)) + op->dummy.nbytes *=2 ; + +/* +* Since spi_nor_spimem_setup_op() only sets buswidth when the number +* of data bytes is non-zero, the data buswidth won't be set here. So, +* do it explicitly. +*/ + op->data.buswidth =spi_nor_get_protocol_data_nbits (nor->read_proto); nor->dirmap.rdesc =devm_spi_mem_dirmap_create (nor->dev, nor->spimem, &info);
@@ -3270,15 +3448,18 @@ static int spi_nor_create_write_dirmap(struct spi_nor *nor) };struct spi_mem_op *op = &info.op_tmpl; -/* get transfer protocols. */ - op->cmd.buswidth =spi_nor_get_protocol_inst_nbits (nor->write_proto); - op->addr.buswidth =spi_nor_get_protocol_addr_nbits (nor->write_proto); - op->dummy.buswidth = op->addr.buswidth; - op->data.buswidth =spi_nor_get_protocol_data_nbits (nor->write_proto); -if (nor->program_opcode ==SPINOR_OP_AAI_WP && nor->sst_write_second) op->addr.nbytes =0 ; +spi_nor_spimem_setup_op (nor, op, nor->write_proto); + +/* +* Since spi_nor_spimem_setup_op() only sets buswidth when the number +* of data bytes is non-zero, the data buswidth won't be set here. So, +* do it explicitly. +*/ + op->data.buswidth =spi_nor_get_protocol_data_nbits (nor->write_proto); + nor->dirmap.wdesc =devm_spi_mem_dirmap_create (nor->dev, nor->spimem, &info);return PTR_ERR_OR_ZERO (nor->dirmap.wdesc);
drivers/mtd/spi-nor/core.h +6 -0
@@ -62,6 +62,7 @@ enum spi_nor_read_command_index {SNOR_CMD_READ_1_8_8 ,SNOR_CMD_READ_8_8_8 ,SNOR_CMD_READ_1_8_8_DTR , +SNOR_CMD_READ_8_8_8_DTR , SNOR_CMD_READ_MAX };
@@ -78,6 +79,7 @@ enum spi_nor_pp_command_index {SNOR_CMD_PP_1_1_8 ,SNOR_CMD_PP_1_8_8 ,SNOR_CMD_PP_8_8_8 , +SNOR_CMD_PP_8_8_8_DTR , SNOR_CMD_PP_MAX };
@@ -311,6 +313,7 @@ struct flash_info {* BP3 is bit 6 of status register. * Must be used with SPI_NOR_4BIT_BP. */ +#define SPI_NOR_OCTAL_DTR_READ BIT(19)/* Flash supports octal DTR Read. */ /* Part specific fixup hooks. */ const struct spi_nor_fixups *fixups;
@@ -399,6 +402,9 @@ extern const struct spi_nor_manufacturer spi_nor_winbond;extern const struct spi_nor_manufacturer spi_nor_xilinx;extern const struct spi_nor_manufacturer spi_nor_xmc; +void spi_nor_spimem_setup_op (const struct spi_nor *nor, +struct spi_mem_op *op, +const enum spi_nor_protocol proto);int spi_nor_write_enable (struct spi_nor *nor);int spi_nor_write_disable (struct spi_nor *nor);int spi_nor_set_4byte_addr_mode (struct spi_nor *nor,bool enable);
drivers/mtd/spi-nor/sfdp.c +8 -1
@@ -1044,9 +1044,16 @@ static int spi_nor_parse_4bait(struct spi_nor *nor, }/* 4BAIT is the only SFDP table that indicates page program support. */ -if (pp_hwcaps &SNOR_HWCAPS_PP ) +if (pp_hwcaps &SNOR_HWCAPS_PP ) {spi_nor_set_pp_settings (¶ms_pp[SNOR_CMD_PP ],SPINOR_OP_PP_4B ,SNOR_PROTO_1_1_1 ); +/* +* Since xSPI Page Program opcode is backward compatible with +* Legacy SPI, use Legacy SPI opcode there as well. +*/ +spi_nor_set_pp_settings (¶ms_pp[SNOR_CMD_PP_8_8_8_DTR ], +SPINOR_OP_PP_4B ,SNOR_PROTO_8_8_8_DTR ); + }if (pp_hwcaps &SNOR_HWCAPS_PP_1_1_4 ) spi_nor_set_pp_settings(¶ms_pp[SNOR_CMD_PP_1_1_4], SPINOR_OP_PP_1_1_4_4B,
include/linux/mtd/spi-nor.h +38 -13
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Signature · 1 line
2.26.2
PATCH v6 6/19 mtd: spi-nor: sfdp: default to addr_width of 3 for configurable widths
In reply to Pratyush YadavJESD216D.01 says that when the address width can be 3 or 4, it defaults to 3 and enters 4-byte mode when given the appropriate command. So, when we see a configurable width, default to 3 and let flash that default to 4 change it in a post-bfpt fixup.
This fixes SMPT parsing for flashes with configurable address width. If the SMPT descriptor advertises variable address width, we use nor->addr_width as the address width. But since it was not set to any value from the SFDP table, the read command uses an address width of 0, resulting in an incorrect read being issued.
--- drivers/mtd/spi-nor/sfdp.c | 1 + 1 file changed, 1 insertion(+)
drivers/mtd/spi-nor/sfdp.c +1 -0
@@ -460,6 +460,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,/* Number of address bytes. */ switch (bfpt.dwords[BFPT_DWORD (1 )] &BFPT_DWORD1_ADDRESS_BYTES_MASK ) {case BFPT_DWORD1_ADDRESS_BYTES_3_ONLY : +case BFPT_DWORD1_ADDRESS_BYTES_3_OR_4 : nor->addr_width =3 ;break ;
Signature · 1 line
2.26.2
PATCH v6 7/19 mtd: spi-nor: sfdp: prepare BFPT parsing for JESD216 rev D
In reply to Pratyush YadavJESD216 rev D makes BFPT 20 DWORDs. Update the BFPT size define to reflect that.
The check for rev A or later compared the BFPT header length with the maximum BFPT length, BFPT_DWORD_MAX. Since BFPT_DWORD_MAX was 16, and so was the BFPT length for both rev A and B, this check worked fine. But now, since BFPT_DWORD_MAX is 20, it means this check will also stop BFPT parsing for rev A or B, since their length is 16.
So, instead check for BFPT_DWORD_MAX_JESD216 to stop BFPT parsing for the first JESD216 version, and check for BFPT_DWORD_MAX_JESD216B for the next two versions.
--- drivers/mtd/spi-nor/sfdp.c | 7 ++++++- drivers/mtd/spi-nor/sfdp.h | 5 +++-- 2 files changed, 9 insertions(+), 3 deletions(-)
drivers/mtd/spi-nor/sfdp.c +6 -1
@@ -549,7 +549,7 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,SNOR_ERASE_TYPE_MASK ;/* Stop here if not JESD216 rev A or later. */ -if (bfpt_header->length <BFPT_DWORD_MAX ) +if (bfpt_header->length ==BFPT_DWORD_MAX_JESD216 )return spi_nor_post_bfpt_fixups (nor, bfpt_header, &bfpt, params);
@@ -605,6 +605,11 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,return -EINVAL ; } +/* Stop here if JESD216 rev B. */ +if (bfpt_header->length ==BFPT_DWORD_MAX_JESD216B ) +return spi_nor_post_bfpt_fixups (nor, bfpt_header, &bfpt, + params); +return spi_nor_post_bfpt_fixups (nor, bfpt_header, &bfpt, params); }
drivers/mtd/spi-nor/sfdp.h +3 -2
@@ -10,11 +10,11 @@/* Basic Flash Parameter Table */ /* -* JESD216 rev B defines a Basic Flash Parameter Table of 16 DWORDs. +* JESD216 rev D defines a Basic Flash Parameter Table of 20 DWORDs. * They are indexed from 1 but C arrays are indexed from 0. */ #define BFPT_DWORD (i) ((i) - 1) -#define BFPT_DWORD_MAX 16 +#define BFPT_DWORD_MAX 20struct sfdp_bfpt {u32 dwords[BFPT_DWORD_MAX ];
@@ -22,6 +22,7 @@ struct sfdp_bfpt {/* The first version of JESD216 defined only 9 DWORDs. */ #define BFPT_DWORD_MAX_JESD216 9 +#define BFPT_DWORD_MAX_JESD216B 16/* 1st DWORD. */ #define BFPT_DWORD1_FAST_READ_1_1_2 BIT(16)
Signature · 1 line
2.26.2
PATCH v6 8/19 mtd: spi-nor: sfdp: get command opcode extension type from BFPT
In reply to Pratyush YadavSome devices in DTR mode expect an extra command byte called the extension. The extension can either be same as the opcode, bitwise inverse of the opcode, or another additional byte forming a 16-byte opcode. Get the extension type from the BFPT. For now, only flashes with "repeat" and "inverse" extensions are supported.
--- drivers/mtd/spi-nor/sfdp.c | 17 +++++++++++++++++ drivers/mtd/spi-nor/sfdp.h | 6 ++++++ 2 files changed, 23 insertions(+)
drivers/mtd/spi-nor/sfdp.c +17 -0
@@ -609,6 +609,23 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,if (bfpt_header->length ==BFPT_DWORD_MAX_JESD216B )return spi_nor_post_bfpt_fixups (nor, bfpt_header, &bfpt, params); +/* 8D-8D-8D command extension. */ +switch (bfpt.dwords[BFPT_DWORD (18 )] &BFPT_DWORD18_CMD_EXT_MASK ) { +case BFPT_DWORD18_CMD_EXT_REP : + nor->cmd_ext_type =SPI_NOR_EXT_REPEAT ; +break ; + +case BFPT_DWORD18_CMD_EXT_INV : + nor->cmd_ext_type =SPI_NOR_EXT_INVERT ; +break ; + +case BFPT_DWORD18_CMD_EXT_RES : +return -EINVAL ; + +case BFPT_DWORD18_CMD_EXT_16B : +dev_err (nor->dev,"16-bit opcodes not supported\n" ); +return -ENOTSUPP ; + }return spi_nor_post_bfpt_fixups (nor, bfpt_header, &bfpt, params); }
drivers/mtd/spi-nor/sfdp.h +6 -0
@@ -84,6 +84,12 @@ struct sfdp_bfpt {#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20)/* Spansion */ +#define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29) +#define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29)/* Repeat */ +#define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29)/* Invert */ +#define BFPT_DWORD18_CMD_EXT_RES (0x2UL << 29)/* Reserved */ +#define BFPT_DWORD18_CMD_EXT_16B (0x3UL << 29)/* 16-bit opcode */ +struct sfdp_parameter_header {u8 id_lsb;u8 minor;
Signature · 1 line
2.26.2
PATCH v6 9/19 mtd: spi-nor: sfdp: parse xSPI Profile 1.0 table
In reply to Pratyush YadavThis table is indication that the flash is xSPI compliant and hence supports octal DTR mode. Extract information like the fast read opcode, dummy cycles, the number of dummy cycles needed for a Read Status Register command, and the number of address bytes needed for a Read Status Register command.
We don't know what speed the controller is running at. Find the fast read dummy cycles for the fastest frequency the flash can run at to be sure we are never short of dummy cycles. If nothing is available, default to 20. Flashes that use a different value should update it in their fixup hooks.
Since we want to set read settings, expose spi_nor_set_read_settings() in core.h.
--- drivers/mtd/spi-nor/core.c | 2 +- drivers/mtd/spi-nor/core.h | 10 ++++ drivers/mtd/spi-nor/sfdp.c | 99 ++++++++++++++++++++++++++++++++++++++ 3 files changed, 110 insertions(+), 1 deletion(-)
drivers/mtd/spi-nor/core.c +1 -1
@@ -2355,7 +2355,7 @@ static int spi_nor_check(struct spi_nor *nor)return 0 ; } -static void +void spi_nor_set_read_settings(struct spi_nor_read_command *read, u8 num_mode_clocks, u8 num_wait_states,
drivers/mtd/spi-nor/core.h +10 -0
@@ -192,6 +192,9 @@ struct spi_nor_locking_ops {* * @size: the flash memory density in bytes. * @page_size: the page size of the SPI NOR flash memory. +* @rdsr_dummy: dummy cycles needed for Read Status Register command. +* @rdsr_addr_nbytes: dummy address bytes needed for Read Status Register +* command. * @hwcaps: describes the read and page program hardware * capabilities. * @reads: read capabilities ordered by priority: the higher index
@@ -214,6 +217,8 @@ struct spi_nor_locking_ops {struct spi_nor_flash_parameter {u64 size;u32 page_size; +u8 rdsr_dummy; +u8 rdsr_addr_nbytes;struct spi_nor_hwcaps hwcaps;struct spi_nor_read_command reads[SNOR_CMD_READ_MAX ];
@@ -424,6 +429,11 @@ ssize_t spi_nor_write_data(struct spi_nor *nor, loff_t to, size_t len,int spi_nor_hwcaps_read2cmd (u32 hwcaps);u8 spi_nor_convert_3to4_read (u8 opcode); +void spi_nor_set_read_settings (struct spi_nor_read_command *read, +u8 num_mode_clocks, +u8 num_wait_states, +u8 opcode, +enum spi_nor_protocol proto);void spi_nor_set_pp_settings (struct spi_nor_pp_command *pp,u8 opcode,enum spi_nor_protocol proto);
drivers/mtd/spi-nor/sfdp.c +99 -0
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Signature · 1 line
2.26.2
PATCH v6 10/19 mtd: spi-nor: core: use dummy cycle and address width info from SFDP
In reply to Pratyush YadavThe xSPI Profile 1.0 table specifies how many dummy cycles and address bytes are needed for the Read Status Register command in octal DTR mode. Use that information to send the correct Read SR command.
--- drivers/mtd/spi-nor/core.c | 25 +++++++++++++++++++++++-- 1 file changed, 23 insertions(+), 2 deletions(-)
drivers/mtd/spi-nor/core.c +23 -2
@@ -357,6 +357,8 @@ int spi_nor_write_disable(struct spi_nor *nor)static int spi_nor_read_sr (struct spi_nor *nor,u8 *sr) {int ret; +u8 addr_bytes = nor->params->rdsr_addr_nbytes; +u8 dummy = nor->params->rdsr_dummy;if (nor->spimem) { struct spi_mem_op op =
@@ -365,10 +367,21 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_IN(1, sr, 1)); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) { + op.addr.nbytes = addr_bytes; + op.addr.val =0 ; + op.dummy.nbytes = dummy; + } + +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); + ret =spi_mem_exec_op (nor->spimem, &op); }else { - ret = nor->controller_ops->read_reg (nor,SPINOR_OP_RDSR , - sr,1 ); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) + ret = -ENOTSUPP ; +else + ret = nor->controller_ops->read_reg (nor,SPINOR_OP_RDSR , + sr,1 ); }if (ret)
@@ -388,6 +401,8 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)static int spi_nor_read_fsr (struct spi_nor *nor,u8 *fsr) {int ret; +u8 addr_bytes = nor->params->rdsr_addr_nbytes; +u8 dummy = nor->params->rdsr_dummy;if (nor->spimem) { struct spi_mem_op op =
@@ -396,6 +411,12 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr)SPI_MEM_OP_NO_DUMMY , SPI_MEM_OP_DATA_IN(1, fsr, 1)); +if (spi_nor_protocol_is_dtr (nor->reg_proto)) { + op.addr.nbytes = addr_bytes; + op.addr.val =0 ; + op.dummy.nbytes = dummy; + } +spi_nor_spimem_setup_op (nor, &op, nor->reg_proto); ret =spi_mem_exec_op (nor->spimem, &op);
Signature · 1 line
2.26.2
PATCH v6 11/19 mtd: spi-nor: core: do 2 byte reads for SR and FSR in DTR mode
In reply to Pratyush YadavSome controllers, like the cadence qspi controller, have trouble reading only 1 byte in DTR mode. So, do 2 byte reads for SR and FSR commands in DTR mode, and then discard the second byte.
--- drivers/mtd/spi-nor/core.c | 15 +++++++++++++-- 1 file changed, 13 insertions(+), 2 deletions(-)
drivers/mtd/spi-nor/core.c +13 -2
@@ -350,7 +350,7 @@ int spi_nor_write_disable(struct spi_nor *nor)* spi_nor_read_sr() - Read the Status Register. * @nor: pointer to 'struct spi_nor'. * @sr: pointer to a DMA-able buffer where the value of the -* Status Register will be written. +* Status Register will be written. Should be at least 2 bytes. * * Return: 0 on success, -errno otherwise. */
@@ -371,6 +371,11 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr) op.addr.nbytes = addr_bytes; op.addr.val =0 ; op.dummy.nbytes = dummy; +/* +* We don't want to read only one byte in DTR mode. So, +* read 2 and then discard the second byte. +*/ + op.data.nbytes =2 ; }spi_nor_spimem_setup_op (nor, &op, nor->reg_proto);
@@ -394,7 +399,8 @@ static int spi_nor_read_sr(struct spi_nor *nor, u8 *sr)* spi_nor_read_fsr() - Read the Flag Status Register. * @nor: pointer to 'struct spi_nor' * @fsr: pointer to a DMA-able buffer where the value of the -* Flag Status Register will be written. +* Flag Status Register will be written. Should be at least 2 +* bytes. * * Return: 0 on success, -errno otherwise. */
@@ -415,6 +421,11 @@ static int spi_nor_read_fsr(struct spi_nor *nor, u8 *fsr) op.addr.nbytes = addr_bytes; op.addr.val =0 ; op.dummy.nbytes = dummy; +/* +* We don't want to read only one byte in DTR mode. So, +* read 2 and then discard the second byte. +*/ + op.data.nbytes =2 ; }spi_nor_spimem_setup_op (nor, &op, nor->reg_proto);
Signature · 1 line
2.26.2
PATCH v6 12/19 mtd: spi-nor: core: enable octal DTR mode when possible
In reply to Pratyush YadavAllow flashes to specify a hook to enable octal DTR mode. Use this hook whenever possible to get optimal transfer speeds.
--- drivers/mtd/spi-nor/core.c | 35 +++++++++++++++++++++++++++++++++++ drivers/mtd/spi-nor/core.h | 2 ++ 2 files changed, 37 insertions(+)
drivers/mtd/spi-nor/core.c +35 -0
@@ -3097,6 +3097,35 @@ static int spi_nor_init_params(struct spi_nor *nor)return 0 ; } +/** spi_nor_octal_dtr_enable() - enable Octal DTR I/O if needed +* @nor: pointer to a 'struct spi_nor' +* @enable: whether to enable or disable Octal DTR +* +* Return: 0 on success, -errno otherwise. +*/ +static int spi_nor_octal_dtr_enable (struct spi_nor *nor,bool enable) +{ +int ret; + +if (!nor->params->octal_dtr_enable) +return 0 ; + +if (!(nor->read_proto ==SNOR_PROTO_8_8_8_DTR && + nor->write_proto ==SNOR_PROTO_8_8_8_DTR )) +return 0 ; + + ret = nor->params->octal_dtr_enable (nor, enable); +if (ret) +return ret; + +if (enable) + nor->reg_proto =SNOR_PROTO_8_8_8_DTR ; +else + nor->reg_proto =SNOR_PROTO_1_1_1 ; + +return 0 ; +} +/** * spi_nor_quad_enable() - enable Quad I/O if needed. * @nor: pointer to a 'struct spi_nor'
@@ -3136,6 +3165,12 @@ static int spi_nor_init(struct spi_nor *nor) {int err; + err =spi_nor_octal_dtr_enable (nor, true); +if (err) { +dev_dbg (nor->dev,"octal mode not supported\n" ); +return err; + } + err =spi_nor_quad_enable (nor);if (err) {dev_dbg (nor->dev,"quad mode not supported\n" );
drivers/mtd/spi-nor/core.h +2 -0
@@ -203,6 +203,7 @@ struct spi_nor_locking_ops {* higher index in the array, the higher priority. * @erase_map: the erase map parsed from the SFDP Sector Map Parameter * Table. +* @octal_dtr_enable: enables SPI NOR octal DTR mode. * @quad_enable: enables SPI NOR quad mode. * @set_4byte_addr_mode: puts the SPI NOR in 4 byte addressing mode. * @convert_addr: converts an absolute address into something the flash
@@ -226,6 +227,7 @@ struct spi_nor_flash_parameter {struct spi_nor_erase_map erase_map; +int (*octal_dtr_enable)(struct spi_nor *nor,bool enable);int (*quad_enable)(struct spi_nor *nor);int (*set_4byte_addr_mode)(struct spi_nor *nor,bool enable);u32 (*convert_addr)(struct spi_nor *nor,u32 addr);
Signature · 1 line
2.26.2
PATCH v6 13/19 mtd: spi-nor: sfdp: do not make invalid quad enable fatal
In reply to Pratyush YadavThe Micron MT35XU512ABA flash does not support the quad enable bit. But instead of programming the Quad Enable Require field to 000b ("Device does not have a QE bit"), it is programmed to 111b ("Reserved").
While this is technically incorrect, it is not reason enough to abort BFPT parsing. Instead, continue BFPT parsing assuming there is no quad enable bit present.
--- drivers/mtd/spi-nor/sfdp.c | 8 +++----- 1 file changed, 3 insertions(+), 5 deletions(-)
drivers/mtd/spi-nor/sfdp.c +3 -5
@@ -576,10 +576,6 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,/* Quad Enable Requirements. */ switch (bfpt.dwords[BFPT_DWORD (15 )] &BFPT_DWORD15_QER_MASK ) { -case BFPT_DWORD15_QER_NONE : - params->quad_enable =NULL ; -break ; -case BFPT_DWORD15_QER_SR2_BIT1_BUGGY :/* * Writing only one byte to the Status Register has the
@@ -616,8 +612,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor, params->quad_enable = spi_nor_sr2_bit1_quad_enable;break ; +case BFPT_DWORD15_QER_NONE :default : -return -EINVAL ; + params->quad_enable =NULL ; +break ; }/* Stop here if JESD216 rev B. */
Signature · 1 line
2.26.2
PATCH v6 14/19 mtd: spi-nor: sfdp: detect Soft Reset sequence support from BFPT
In reply to Pratyush YadavA Soft Reset sequence will return the flash to Power-on-Reset (POR) state. It consists of two commands: Soft Reset Enable and Soft Reset. Find out if the sequence is supported from BFPT DWORD 16.
--- drivers/mtd/spi-nor/core.h | 1 + drivers/mtd/spi-nor/sfdp.c | 4 ++++ drivers/mtd/spi-nor/sfdp.h | 2 ++ 3 files changed, 7 insertions(+)
drivers/mtd/spi-nor/core.h +1 -0
@@ -26,6 +26,7 @@ enum spi_nor_option_flags {SNOR_F_HAS_SR_TB_BIT6 =BIT (11 ),SNOR_F_HAS_4BIT_BP =BIT (12 ),SNOR_F_HAS_SR_BP3_BIT6 =BIT (13 ), + SNOR_F_SOFT_RESET = BIT(14), }; struct spi_nor_read_command {
drivers/mtd/spi-nor/sfdp.c +4 -0
@@ -618,6 +618,10 @@ static int spi_nor_parse_bfpt(struct spi_nor *nor,break ; } +/* Soft Reset support. */ +if (bfpt.dwords[BFPT_DWORD (16 )] &BFPT_DWORD16_SOFT_RST ) + nor->flags |=SNOR_F_SOFT_RESET ; +/* Stop here if JESD216 rev B. */ if (bfpt_header->length ==BFPT_DWORD_MAX_JESD216B ) return spi_nor_post_bfpt_fixups(nor, bfpt_header, &bfpt,
drivers/mtd/spi-nor/sfdp.h +2 -0
@@ -84,6 +84,8 @@ struct sfdp_bfpt {#define BFPT_DWORD15_QER_SR2_BIT1_NO_RD (0x4UL << 20)#define BFPT_DWORD15_QER_SR2_BIT1 (0x5UL << 20)/* Spansion */ +#define BFPT_DWORD16_SOFT_RST BIT(12) +#define BFPT_DWORD18_CMD_EXT_MASK GENMASK(30, 29)#define BFPT_DWORD18_CMD_EXT_REP (0x0UL << 29)/* Repeat */ #define BFPT_DWORD18_CMD_EXT_INV (0x1UL << 29)/* Invert */
Signature · 1 line
2.26.2
PATCH v6 15/19 mtd: spi-nor: core: perform a Soft Reset on shutdown
In reply to Pratyush YadavPerform a Soft Reset on shutdown on flashes that support it so that the flash can be reset to its initial state and any configurations made by spi-nor (given that they're only done in volatile registers) will be reset. This will hand back the flash in pristine state for any further operations on it.
--- drivers/mtd/spi-nor/core.c | 42 +++++++++++++++++++++++++++++++++++++ include/linux/mtd/spi-nor.h | 2 ++ 2 files changed, 44 insertions(+)
drivers/mtd/spi-nor/core.c +42 -0
@@ -40,6 +40,9 @@#define SPI_NOR_MAX_ADDR_WIDTH 4 +#define SPI_NOR_SRST_SLEEP_MIN 200 +#define SPI_NOR_SRST_SLEEP_MAX 400 +/** * spi_nor_get_cmd_ext() - Get the command opcode extension based on the * extension type.
@@ -3201,6 +3204,41 @@ static int spi_nor_init(struct spi_nor *nor)return 0 ; } +static void spi_nor_soft_reset (struct spi_nor *nor) +{ +struct spi_mem_op op; +int ret; + + op = (struct spi_mem_op )SPI_MEM_OP (SPI_MEM_OP_CMD (SPINOR_OP_SRSTEN ,8 ), +SPI_MEM_OP_NO_DUMMY , +SPI_MEM_OP_NO_ADDR , +SPI_MEM_OP_NO_DATA ); +spi_nor_spimem_setup_op (nor, &op,SNOR_PROTO_8_8_8_DTR ); + ret =spi_mem_exec_op (nor->spimem, &op); +if (ret) { +dev_warn (nor->dev,"Software reset failed: %d\n" , ret); +return ; + } + + op = (struct spi_mem_op )SPI_MEM_OP (SPI_MEM_OP_CMD (SPINOR_OP_SRST ,8 ), +SPI_MEM_OP_NO_DUMMY , +SPI_MEM_OP_NO_ADDR , +SPI_MEM_OP_NO_DATA ); +spi_nor_spimem_setup_op (nor, &op,SNOR_PROTO_8_8_8_DTR ); + ret =spi_mem_exec_op (nor->spimem, &op); +if (ret) { +dev_warn (nor->dev,"Software reset failed: %d\n" , ret); +return ; + } + +/* +* Software Reset is not instant, and the delay varies from flash to +* flash. Looking at a few flashes, most range somewhere below 100 +* microseconds. So, sleep for a range of 200-400 us. +*/ +usleep_range (SPI_NOR_SRST_SLEEP_MIN ,SPI_NOR_SRST_SLEEP_MAX ); +} +/* mtd resume handler */ static void spi_nor_resume (struct mtd_info *mtd) {
@@ -3220,6 +3258,10 @@ void spi_nor_restore(struct spi_nor *nor)if (nor->addr_width ==4 && !(nor->flags &SNOR_F_4B_OPCODES ) && nor->flags &SNOR_F_BROKEN_RESET ) nor->params->set_4byte_addr_mode (nor, false); + +if (nor->info->flags &SPI_NOR_OCTAL_DTR_READ && + nor->flags &SNOR_F_SOFT_RESET ) +spi_nor_soft_reset (nor); }EXPORT_SYMBOL_GPL (spi_nor_restore);
include/linux/mtd/spi-nor.h +2 -0
@@ -51,6 +51,8 @@#define SPINOR_OP_CLFSR 0x50/* Clear flag status register */ #define SPINOR_OP_RDEAR 0xc8/* Read Extended Address Register */ #define SPINOR_OP_WREAR 0xc5/* Write Extended Address Register */ +#define SPINOR_OP_SRSTEN 0x66/* Software Reset Enable */ +#define SPINOR_OP_SRST 0x99/* Software Reset */ /* 4-byte address opcodes - used on Spansion and some Macronix flashes. */ #define SPINOR_OP_READ_4B 0x13/* Read data bytes (low frequency) */
Signature · 1 line
2.26.2
PATCH v6 16/19 mtd: spi-nor: core: disable Octal DTR mode on suspend.
In reply to Pratyush YadavOn resume, the init procedure will be run that will re-enable it.
--- drivers/mtd/spi-nor/core.c | 18 ++++++++++++++++++ 1 file changed, 18 insertions(+)
drivers/mtd/spi-nor/core.c +18 -0
@@ -3239,6 +3239,23 @@ static void spi_nor_soft_reset(struct spi_nor *nor)usleep_range (SPI_NOR_SRST_SLEEP_MIN ,SPI_NOR_SRST_SLEEP_MAX ); } +/* mtd suspend handler */ +static int spi_nor_suspend (struct mtd_info *mtd) +{ +struct spi_nor *nor =mtd_to_spi_nor (mtd); +struct device *dev = nor->dev; +int ret; + +/* Disable octal DTR mode if we enabled it. */ + ret =spi_nor_octal_dtr_enable (nor, false); +if (ret) { +dev_err (dev,"suspend() failed\n" ); +return ret; + } + +return 0 ; +} +/* mtd resume handler */ static void spi_nor_resume (struct mtd_info *mtd) {
@@ -3432,6 +3449,7 @@ int spi_nor_scan(struct spi_nor *nor, const char *name, mtd->size = nor->params->size; mtd->_erase = spi_nor_erase; mtd->_read = spi_nor_read; + mtd->_suspend = spi_nor_suspend; mtd->_resume = spi_nor_resume;if (nor->params->locking_ops) {
Signature · 1 line
2.26.2
PATCH v6 17/19 mtd: spi-nor: core: expose spi_nor_default_setup() in core.h
In reply to Pratyush YadavFlashes might want to add a custom setup hook to configure the flash in the proper mode for operation. But after that, they would still want to run the default setup hook because it selects the read, program, and erase operations. Since there is little point in repeating all that code, expose the spi_nor_default_setup() in core.h to manufacturer-specific files.
--- drivers/mtd/spi-nor/core.c | 4 ++-- drivers/mtd/spi-nor/core.h | 3 +++ 2 files changed, 5 insertions(+), 2 deletions(-)
drivers/mtd/spi-nor/core.c +2 -2
@@ -2790,8 +2790,8 @@ static int spi_nor_select_erase(struct spi_nor *nor)return 0 ; } -static int spi_nor_default_setup (struct spi_nor *nor, -const struct spi_nor_hwcaps *hwcaps) +int spi_nor_default_setup (struct spi_nor *nor, +const struct spi_nor_hwcaps *hwcaps) {struct spi_nor_flash_parameter *params = nor->params;u32 ignored_mask, shared_mask;
drivers/mtd/spi-nor/core.h +3 -0
@@ -452,6 +452,9 @@ int spi_nor_post_bfpt_fixups(struct spi_nor *nor,const struct sfdp_bfpt *bfpt, struct spi_nor_flash_parameter *params); +int spi_nor_default_setup (struct spi_nor *nor, +const struct spi_nor_hwcaps *hwcaps); +static struct spi_nor __maybe_unused *mtd_to_spi_nor (struct mtd_info *mtd) {return mtd->priv;
Signature · 1 line
2.26.2
PATCH v6 18/19 mtd: spi-nor: spansion: add support for Cypress Semper flash
In reply to Pratyush YadavThe Cypress Semper flash is an xSPI compliant octal DTR flash. Add support for using it in octal DTR mode.
The flash by default boots in a hybrid sector mode. But the sector map table on the part I had was programmed incorrectly and the SMPT values on the flash don't match the public datasheet. Specifically, in some places erase type 3 was used instead of 4. In addition, the region sizes were incorrect in some places. So, for testing I set CFR3N[3] to enable uniform sector sizes. Since the uniform sector mode bit is a non-volatile bit, this series does not change it to avoid making any permanent changes to the flash configuration. The correct data to implement a fixup is not available right now and will be done in a follow-up patch if needed.
--- drivers/mtd/spi-nor/spansion.c | 167 +++++++++++++++++++++++++++++++++ 1 file changed, 167 insertions(+)
drivers/mtd/spi-nor/spansion.c +167 -0
@@ -8,6 +8,169 @@#include "core.h" +/* For Cypress flash. */ +#define SPINOR_OP_RD_ANY_REG 0x65/* Read any register */ +#define SPINOR_OP_WR_ANY_REG 0x71/* Write any register */ +#define SPINOR_REG_CYPRESS_CFR2V 0x00800003 +#define SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 0xb +#define SPINOR_REG_CYPRESS_CFR3V 0x00800004 +#define SPINOR_REG_CYPRESS_CFR3V_PGSZ BIT(4)/* Page size. */ +#define SPINOR_REG_CYPRESS_CFR5V 0x00800006 +#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN 0x3 +#define SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS 0 +#define SPINOR_OP_CYPRESS_RD_FAST 0xee + +/** +* spi_nor_cypress_octal_dtr_enable() - Enable octal DTR on Cypress flashes. +* @nor: pointer to a 'struct spi_nor' +* +* This also sets the memory access latency cycles to 24 to allow the flash to +* run at up to 200MHz. +* +* Return: 0 on success, -errno otherwise. +*/ +static int spi_nor_cypress_octal_dtr_enable (struct spi_nor *nor,bool enable) +{ +struct spi_mem_op op; +u8 *buf = nor->bouncebuf; +u8 addr_width; +int ret; + +if (enable) + addr_width =3 ; +else + addr_width =4 ; + +if (enable) { +/* Use 24 dummy cycles for memory array reads. */ + ret =spi_nor_write_enable (nor); +if (ret) +return ret; + + *buf =SPINOR_REG_CYPRESS_CFR2V_MEMLAT_11_24 ; + op = (struct spi_mem_op ) +SPI_MEM_OP (SPI_MEM_OP_CMD (SPINOR_OP_WR_ANY_REG ,1 ), +SPI_MEM_OP_ADDR (addr_width, +SPINOR_REG_CYPRESS_CFR2V , +1 ), +SPI_MEM_OP_NO_DUMMY , +SPI_MEM_OP_DATA_OUT (1 , buf,1 )); + ret =spi_mem_exec_op (nor->spimem, &op); +if (ret) { +dev_warn (nor->dev, +"failed to set default memory latency value: %d\n" , + ret); +return ret; + } + ret =spi_nor_wait_till_ready (nor); +if (ret) +return ret; + + nor->read_dummy =24 ; + } + +/* Set/unset the octal and DTR enable bits. */ + ret =spi_nor_write_enable (nor); +if (ret) +return ret; + +if (enable) + *buf =SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_EN ; +else + *buf =SPINOR_REG_CYPRESS_CFR5V_OCT_DTR_DS ; + op = (struct spi_mem_op ) +SPI_MEM_OP (SPI_MEM_OP_CMD (SPINOR_OP_WR_ANY_REG ,1 ), +SPI_MEM_OP_ADDR (addr_width, +SPINOR_REG_CYPRESS_CFR5V , +1 ), +SPI_MEM_OP_NO_DUMMY , +SPI_MEM_OP_DATA_OUT (1 , buf,1 )); + +if (!enable) +spi_nor_spimem_setup_op (nor, &op,SNOR_PROTO_8_8_8_DTR ); + + ret =spi_mem_exec_op (nor->spimem, &op); +if (ret) { +dev_warn (nor->dev,"Failed to enable octal DTR mode\n" ); +return ret; + } + +return 0 ; +} + +static void s28hs512t_default_init (struct spi_nor *nor) +{ + nor->params->octal_dtr_enable = spi_nor_cypress_octal_dtr_enable; +} + +static void s28hs512t_post_sfdp_fixup (struct spi_nor *nor) +{ +/* +* On older versions of the flash the xSPI Profile 1.0 table has the +* 8D-8D-8D Fast Read opcode as 0x00. But it actually should be 0xEE. +*/ +if (nor->params->reads[SNOR_CMD_READ_8_8_8_DTR ].opcode ==0 ) + nor->params->reads[SNOR_CMD_READ_8_8_8_DTR ].opcode = +SPINOR_OP_CYPRESS_RD_FAST ; + + nor->params->hwcaps.mask |=SNOR_HWCAPS_PP_8_8_8_DTR ; + +/* This flash is also missing the 4-byte Page Program opcode bit. */ +spi_nor_set_pp_settings (&nor->params->page_programs[SNOR_CMD_PP ], +SPINOR_OP_PP_4B ,SNOR_PROTO_1_1_1 ); +/* +* Since xSPI Page Program opcode is backward compatible with +* Legacy SPI, use Legacy SPI opcode there as well. +*/ +spi_nor_set_pp_settings (&nor->params->page_programs[SNOR_CMD_PP_8_8_8_DTR ], +SPINOR_OP_PP_4B ,SNOR_PROTO_8_8_8_DTR ); + +/* +* The xSPI Profile 1.0 table advertises the number of additional +* address bytes needed for Read Status Register command as 0 but the +* actual value for that is 4. +*/ + nor->params->rdsr_addr_nbytes =4 ; +} + +static int s28hs512t_post_bfpt_fixup (struct spi_nor *nor, +const struct sfdp_parameter_header *bfpt_header, +const struct sfdp_bfpt *bfpt, +struct spi_nor_flash_parameter *params) +{ +struct spi_mem_op op; +u8 *buf = nor->bouncebuf; +u8 addr_width =3 ; +int ret; + +/* +* The BFPT table advertises a 512B page size but the page size is +* actually configurable (with the default being 256B). Read from +* CFR3V[4] and set the correct size. +*/ + op = (struct spi_mem_op ) +SPI_MEM_OP (SPI_MEM_OP_CMD (SPINOR_OP_RD_ANY_REG ,1 ), +SPI_MEM_OP_ADDR (addr_width,SPINOR_REG_CYPRESS_CFR3V ,1 ), +SPI_MEM_OP_NO_DUMMY , +SPI_MEM_OP_DATA_IN (1 , buf,1 )); + ret =spi_mem_exec_op (nor->spimem, &op); +if (ret) +return ret; + +if (*buf &SPINOR_REG_CYPRESS_CFR3V_PGSZ ) + params->page_size =512 ; +else + params->page_size =256 ; + +return 0 ; +} + +static struct spi_nor_fixups s28hs512t_fixups = { + .default_init = s28hs512t_default_init, + .post_sfdp = s28hs512t_post_sfdp_fixup, + .post_bfpt = s28hs512t_post_bfpt_fixup, +}; +static const struct flash_info spansion_parts[] = {/* Spansion/Cypress -- single (large) sector size only, at least * for the chips listed here (without boot sectors).
@@ -72,6 +235,10 @@ static const struct flash_info spansion_parts[] = { {"s25fl256l" ,INFO (0x016019 ,0 ,64 *1024 ,512 ,SECT_4K |SPI_NOR_DUAL_READ |SPI_NOR_QUAD_READ | SPI_NOR_4B_OPCODES) }, + { "s28hs512t", INFO(0x345b1a, 0, 256 * 1024, 256, +SECT_4K |SPI_NOR_OCTAL_DTR_READ ) + .fixups = &s28hs512t_fixups, + }, };static void spansion_post_sfdp_fixups (struct spi_nor *nor)
Signature · 1 line
2.26.2
PATCH v6 19/19 mtd: spi-nor: micron-st: allow using MT35XU512ABA in Octal DTR mode
In reply to Pratyush YadavSince this flash doesn't have a Profile 1.0 table, the Octal DTR capabilities are enabled in the post SFDP fixup, along with the 8D-8D-8D fast read settings.
Enable Octal DTR mode with 20 dummy cycles to allow running at the maximum supported frequency of 200Mhz.
The flash supports the soft reset sequence. So, add the flag in the flash's info.
--- drivers/mtd/spi-nor/micron-st.c | 112 +++++++++++++++++++++++++++++++- 1 file changed, 111 insertions(+), 1 deletion(-)
drivers/mtd/spi-nor/micron-st.c +111 -1
@@ -8,10 +8,120 @@#include "core.h" +#define SPINOR_OP_MT_DTR_RD 0xfd/* Fast Read opcode in DTR mode */ +#define SPINOR_OP_MT_RD_ANY_REG 0x85/* Read volatile register */ +#define SPINOR_OP_MT_WR_ANY_REG 0x81/* Write volatile register */ +#define SPINOR_REG_MT_CFR0V 0x00/* For setting octal DTR mode */ +#define SPINOR_REG_MT_CFR1V 0x01/* For setting dummy cycles */ +#define SPINOR_MT_DTR_NO_DQS 0xc7/* Enable Octal DTR without DQS. */ +#define SPINOR_MT_EXSPI 0xff/* Enable Extended SPI (default) */ + +static int spi_nor_micron_octal_dtr_enable (struct spi_nor *nor,bool enable) +{ +struct spi_mem_op op; +u8 *buf = nor->bouncebuf; +u8 addr_width; +int ret; + +if (enable) + addr_width =3 ; +else + addr_width =4 ; + + ret =spi_nor_write_enable (nor); +if (ret) +return ret; + +if (enable) + *buf =SPINOR_MT_DTR_NO_DQS ; +else + *buf =SPINOR_MT_EXSPI ; + op = (struct spi_mem_op ) +SPI_MEM_OP (SPI_MEM_OP_CMD (SPINOR_OP_MT_WR_ANY_REG ,1 ), +SPI_MEM_OP_ADDR (addr_width,SPINOR_REG_MT_CFR0V ,1 ), +SPI_MEM_OP_NO_DUMMY , +SPI_MEM_OP_DATA_OUT (1 , buf,1 )); + +if (!enable) +spi_nor_spimem_setup_op (nor, &op,SNOR_PROTO_8_8_8_DTR ); + + ret =spi_mem_exec_op (nor->spimem, &op); +if (ret) { +dev_err (nor->dev,"Failed to enable octal DTR mode\n" ); +return ret; + } + +return 0 ; +} + +static int mt35xu512aba_setup (struct spi_nor *nor, +const struct spi_nor_hwcaps *hwcaps) +{ +struct spi_mem_op op; +u8 *buf = nor->bouncebuf; +u8 addr_width =3 ; +int ret; + +if (!nor->spimem) { +dev_err (nor->dev, +"operation not supported for non-spimem drivers\n" ); +return -ENOTSUPP ; + } + +/* Set dummy cycles for Fast Read to the default of 20. */ + ret =spi_nor_write_enable (nor); +if (ret) +return ret; + + *buf =20 ; + op = (struct spi_mem_op ) +SPI_MEM_OP (SPI_MEM_OP_CMD (SPINOR_OP_MT_WR_ANY_REG ,1 ), +SPI_MEM_OP_ADDR (addr_width,SPINOR_REG_MT_CFR1V ,1 ), +SPI_MEM_OP_NO_DUMMY , +SPI_MEM_OP_DATA_OUT (1 , buf,1 )); + ret =spi_mem_exec_op (nor->spimem, &op); +if (ret) +return ret; + + ret =spi_nor_wait_till_ready (nor); +if (ret) +return ret; + + +return spi_nor_default_setup (nor, hwcaps); +} + +static void mt35xu512aba_default_init (struct spi_nor *nor) +{ + nor->params->octal_dtr_enable = spi_nor_micron_octal_dtr_enable; + nor->params->setup = mt35xu512aba_setup; +} + +static void mt35xu512aba_post_sfdp_fixup (struct spi_nor *nor) +{ +/* Set the Fast Read settings. */ + nor->params->hwcaps.mask |=SNOR_HWCAPS_READ_8_8_8_DTR ; +spi_nor_set_read_settings (&nor->params->reads[SNOR_CMD_READ_8_8_8_DTR ], +0 ,20 ,SPINOR_OP_MT_DTR_RD , +SNOR_PROTO_8_8_8_DTR ); + + nor->params->hwcaps.mask |=SNOR_HWCAPS_PP_8_8_8_DTR ; + + nor->cmd_ext_type =SPI_NOR_EXT_REPEAT ; + nor->params->rdsr_dummy =8 ; + nor->params->rdsr_addr_nbytes =0 ; +} + +static struct spi_nor_fixups mt35xu512aba_fixups = { + .default_init = mt35xu512aba_default_init, + .post_sfdp = mt35xu512aba_post_sfdp_fixup, +}; +static const struct flash_info micron_parts[] = { {"mt35xu512aba" ,INFO (0x2c5b1a ,0 ,128 *1024 ,512 ,SECT_4K |USE_FSR |SPI_NOR_OCTAL_READ | -SPI_NOR_4B_OPCODES ) }, +SPI_NOR_4B_OPCODES |SPI_NOR_OCTAL_DTR_READ ) + .fixups = &mt35xu512aba_fixups}, {"mt35xu02g" ,INFO (0x2c5b1c ,0 ,128 *1024 ,2048 ,SECT_4K |USE_FSR |SPI_NOR_OCTAL_READ |SPI_NOR_4B_OPCODES ) },
Signature · 1 line
2.26.2
Mark Brown
maintainerQuoted 6 lines · Pratyush Yadav
Hi,
This series adds support for octal DTR flashes in the spi-nor framework, and then adds hooks for the Cypress Semper and Mircom Xcella flashes to allow running them in octal DTR mode. This series assumes that the flash is handed to the kernel in Legacy SPI mode.
Are people happy with the SPI bits of this from a MTD point of view? I don't have any concerns and could apply them on a branch even if more revisions are needed for the MTD side.
Hi Mark,
Quoted 11 lines · Mark Brown
Quoted 6 lines · Pratyush Yadav
Hi,
This series adds support for octal DTR flashes in the spi-nor framework, and then adds hooks for the Cypress Semper and Mircom Xcella flashes to allow running them in octal DTR mode. This series assumes that the flash is handed to the kernel in Legacy SPI mode.
Are people happy with the SPI bits of this from a MTD point of view? I don't have any concerns and could apply them on a branch even if more revisions are needed for the MTD side.
There were a couple small changes suggested for spi-mem. Will send a re-roll in a few minutes.
Signature · 8 lines
Regards, Pratyush Yadav Texas Instruments India _______________________________________________ linux-arm-kernel mailing list [email protected] http://lists.infradead.org/mailman/listinfo/linux-arm-kernel