drm/bridge: Add mux input selection bridge

new file mode 100644
index 000000000000..4029cf63ee5c
@@ -0,0 +1,123 @@
+# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
+%YAML 1.2
+---
+$id: http://devicetree.org/schemas/display/bridge/mux-input-bridge.yaml#
+$schema: http://devicetree.org/meta-schemas/core.yaml#
+
+title: DRM input source selection via multiplexer
+
+maintainers:
+  - Guido Gúnther <[email protected]>
+
+description: |
+  The input multiplexer bridge allows to select an input source
+  via an associated mux controller.
+
+properties:
+  compatible:
+    const: mux-input-bridge
+
+  '#address-cells':
+    const: 1
+
+  '#size-cells':
+    const: 0
+
+  default-input:
+    description: The default input to use
+
+  mux-controls:
+    description:
+      mux controller node to use for operating the input mux
+
+  ports:
+    type: object
+    properties:
+      '#address-cells':
+        const: 1
+      '#size-cells':
+        const: 0
+
+    patternProperties:
+      "^port@[0-9]+":
+        type: object
+        description:
+          At least three nodes containing endpoints connecting to the
+          pixel data inputs and outputs. The last port is always the
+          output port.
+
+        properties:
+          reg:
+            maxItems: 1
+
+          endpoint:
+            description: sub-node describing the input
+            type: object
+
+        required:
+          - reg
+
+        additionalProperties: false
+
+    required:
+      - port@0
+      - port@1
+      - port@2
+
+    additionalProperties: false
+
+required:
+  - '#address-cells'
+  - '#size-cells'
+  - mux-controls
+  - ports
+
+additionalProperties: false
+
+examples:
+ - |
+   #include <dt-bindings/gpio/gpio.h>
+
+   mux: mux-controller {
+           compatible = "gpio-mux";
+           #mux-control-cells = <0>;
+
+           mux-gpios = <&gpio1 15 GPIO_ACTIVE_HIGH>;
+   };
+
+   mipi-mux {
+           compatible = "mux-input-bridge";
+           default-input = <0>;
+           mux-controls = <&mux 0>;
+           #address-cells = <1>;
+           #size-cells = <0>;
+
+           ports {
+                   #address-cells = <1>;
+                   #size-cells = <0>;
+
+                   port@0 {
+                           reg = <0>;
+
+                           dpi_mux_from_lcdif: endpoint {
+                                   remote-endpoint = <&lcdif_dpi_out>;
+                           };
+                   };
+
+                   port@1 {
+                           reg = <1>;
+
+                           dpi_mux_from_dccss: endpoint {
+                                   remote-endpoint = <&dcss_dpi_out>;
+                           };
+                   };
+
+                   port@2 {
+                           reg = <2>;
+
+                           dpi_mux_out: endpoint {
+                                   remote-endpoint = <&nwl_dpi_in>;
+                           };
+                   };
+           };
+   };

index 04f876e985de..3886c0f41bdd 100644
@@ -206,6 +206,15 @@ config DRM_TI_TPD12S015
 	  Texas Instruments TPD12S015 HDMI level shifter and ESD protection
 	  driver.
 
+config DRM_MUX_INPUT
+	tristate "Bridge to select a video input source"
+	depends on OF
+	depends on DRM_BRIDGE
+	select MULTIPLEXER
+	help
+	  Select this option if you want to select the input source to
+	  a DRM bridge or panel via a separate mux chip.
+
 source "drivers/gpu/drm/bridge/analogix/Kconfig"
 
 source "drivers/gpu/drm/bridge/adv7511/Kconfig"

index d63d4b7e4347..9f3370ce7e07 100644
@@ -4,6 +4,7 @@ obj-$(CONFIG_DRM_CHRONTEL_CH7033) += chrontel-ch7033.o
 obj-$(CONFIG_DRM_DISPLAY_CONNECTOR) += display-connector.o
 obj-$(CONFIG_DRM_LVDS_CODEC) += lvds-codec.o
 obj-$(CONFIG_DRM_MEGACHIPS_STDPXXXX_GE_B850V3_FW) += megachips-stdpxxxx-ge-b850v3-fw.o
+obj-$(CONFIG_DRM_MUX_INPUT) += mux-input.o
 obj-$(CONFIG_DRM_NXP_PTN3460) += nxp-ptn3460.o
 obj-$(CONFIG_DRM_PARADE_PS8622) += parade-ps8622.o
 obj-$(CONFIG_DRM_PARADE_PS8640) += parade-ps8640.o

index 8aff2d68fc33..d2c2d4e19a25 100644
@@ -46,10 +46,6 @@ properties:
       - const: phy_ref
       - const: lcdif
 
-  mux-controls:
-    description:
-      mux controller node to use for operating the input mux
-
   phys:
     maxItems: 1
     description:

@@ -151,7 +147,6 @@ required:
   - clocks
   - compatible
   - interrupts
-  - mux-controls
   - phy-names
   - phys
   - ports

@@ -180,7 +175,6 @@ examples:
                        <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
               clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
               interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
-              mux-controls = <&mux 0>;
               power-domains = <&pgc_mipi>;
               resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
                        <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,

index 3886c0f41bdd..11444f841e35 100644
@@ -78,7 +78,6 @@ config DRM_NWL_MIPI_DSI
 	select DRM_PANEL_BRIDGE
 	select GENERIC_PHY_MIPI_DPHY
 	select MFD_SYSCON
-	select MULTIPLEXER
 	select REGMAP_MMIO
 	help
 	  This enables the Northwest Logic MIPI DSI Host controller as

index 0142f06ead12..6bbbf44e6be0 100644
@@ -889,6 +889,37 @@ sec_jr2: jr@3000 {
 				};
 			};
 
+			mipi_dsi: mipi-dsi@30a00000 {
+				#address-cells = <1>;
+				#size-cells = <0>;
+				compatible = "fsl,imx8mq-nwl-dsi";
+				reg = <0x30a00000 0x300>;
+				clocks = <&clk IMX8MQ_CLK_DSI_CORE>,
+					 <&clk IMX8MQ_CLK_DSI_AHB>,
+					 <&clk IMX8MQ_CLK_DSI_IPG_DIV>,
+					 <&clk IMX8MQ_CLK_DSI_PHY_REF>,
+					 <&clk IMX8MQ_CLK_LCDIF_PIXEL>;
+				clock-names = "core", "rx_esc", "tx_esc", "phy_ref", "lcdif";
+				assigned-clocks = <&clk IMX8MQ_CLK_DSI_AHB>,
+						  <&clk IMX8MQ_CLK_DSI_CORE>,
+						  <&clk IMX8MQ_CLK_DSI_IPG_DIV>;
+				assigned-clock-parents = <&clk IMX8MQ_SYS1_PLL_80M>,
+							 <&clk IMX8MQ_SYS1_PLL_266M>;
+				assigned-clock-rates = <80000000>,
+						       <266000000>,
+						       <20000000>;
+				interrupts = <GIC_SPI 34 IRQ_TYPE_LEVEL_HIGH>;
+				resets = <&src IMX8MQ_RESET_MIPI_DSI_RESET_BYTE_N>,
+					 <&src IMX8MQ_RESET_MIPI_DSI_DPI_RESET_N>,
+					 <&src IMX8MQ_RESET_MIPI_DSI_ESC_RESET_N>,
+					 <&src IMX8MQ_RESET_MIPI_DSI_PCLK_RESET_N>;
+				reset-names = "byte", "dpi", "esc", "pclk";
+				phys = <&dphy>;
+				phy-names = "dphy";
+				power-domains = <&pgc_mipi>;
+				status = "disabled";
+			 };
+
 			dphy: dphy@30a00300 {
 				compatible = "fsl,imx8mq-mipi-dphy";
 				reg = <0x30a00300 0x100>;

index 7fc31c71a626..d98f9b8dede8 100644
@@ -841,6 +841,87 @@ MX8MQ_IOMUXC_NAND_DATA03_GPIO3_IO9	0x19 /* WWAN_RESET */
 	};
 };
 
+&lcdif {
+	status = "okay";
+
+	port@0 {
+		lcdif_dpi_out: endpoint {
+			remote-endpoint = <&dpi_mux_from_lcdif>;
+		};
+	};
+};
+
+&iomuxc_gpr {
+	mipi_mux: mipi-mux {
+		compatible = "mux-input-bridge";
+		mux-controls = <&mux 0>;
+		#address-cells = <1>;
+		#size-cells = <0>;
+		status = "okay";
+		default-input = <0>;
+
+		ports {
+			#address-cells = <1>;
+			#size-cells = <0>;
+
+			port@0 {
+				reg = <0>;
+
+				dpi_mux_from_lcdif: endpoint {
+					remote-endpoint = <&lcdif_dpi_out>;
+				};
+			};
+
+			port@1 { /* dcss */
+				reg = <1>;
+			};
+
+			port@2 {
+				reg = <2>;
+				dpi_mux_out: endpoint {
+					remote-endpoint = <&nwl_dpi_in>;
+				};
+
+			};
+		};
+	};
+};
+
+&mipi_dsi {
+	status = "okay";
+	panel@0 {
+		compatible = "rocktech,jh057n00900";
+		reg = <0>;
+		backlight = <&backlight_dsi>;
+		reset-gpios = <&gpio3 13 GPIO_ACTIVE_LOW>;
+		vcc-supply = <&reg_2v8_p>;
+		iovcc-supply = <&reg_1v8_p>;
+		port@0 {
+			panel_in: endpoint {
+				remote-endpoint = <&nwl_dsi_out>;
+			};
+		};
+	};
+
+	ports {
+		#address-cells = <1>;
+		#size-cells = <0>;
+
+		port@0 {
+			reg = <0>;
+			nwl_dpi_in: endpoint {
+				remote-endpoint = <&dpi_mux_out>;
+			};
+		};
+		port@1 {
+			reg = <1>;
+			nwl_dsi_out: endpoint {
+				remote-endpoint = <&panel_in>;
+			};
+		};
+	};
+};
+
 &pgc_gpu {
 	power-supply = <&buck3_reg>;
 };