pinctrl: update realtek DHC pinctrl driver

index d69716243297..60bf8c283a7a 100644
@@ -304,7 +304,7 @@ static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data)
 			/* Check for function */
 			for (k = 0; k < data->info->num_functions; k++) {
 				if (strcmp(data->info->functions[k].name,
-				           data->info->muxes[i].functions[j].name) == 0)
+					data->info->muxes[i].functions[j].name) == 0)
 					break;
 			}
 			if (k == data->info->num_functions)

@@ -314,7 +314,7 @@ static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data)
 
 			/* Check for duplicate mux value - assumption: ascending order */
 			if (j > 0 && data->info->muxes[i].functions[j].mux_value
-			          <= data->info->muxes[i].functions[j - 1].mux_value)
+				< data->info->muxes[i].functions[j - 1].mux_value)
 				dev_warn(data->pcdev->dev, "Mux %s function %s has unexpected value\n",
 					 data->info->muxes[i].name,
 					 data->info->muxes[i].functions[j].name);

406 lines not on this page · raw message

index 60bf8c283a7a..e8c818c38b83 100644
@@ -36,6 +36,26 @@ struct rtd119x_pin_mux_desc {
 	u32 mux_value;
 };
 
+struct rtd119x_pin_sconfig_desc {
+	const char *name;
+	unsigned int reg_offset;
+	unsigned int ndrive_offset;
+	unsigned int ndrive_maskbits;
+	unsigned int pdrive_offset;
+	unsigned int pdrive_maskbits;
+};
+
+struct rtd119x_pin_config_desc {
+	const char *name;
+	unsigned int reg_offset;
+	unsigned int base_bit;
+	unsigned int pud_en_offset;
+	unsigned int pud_sel_offset;
+	unsigned int curr_offset;
+	unsigned int smt_offset;
+	unsigned int curr_type;
+};
+
 struct rtd119x_pin_desc {
 	const char *name;
 	unsigned int mux_offset;

@@ -43,6 +63,31 @@ struct rtd119x_pin_desc {
 	const struct rtd119x_pin_mux_desc *functions;
 };
 
+#define RTK_PIN_SCONFIG(_name, _reg_off, _n_offset, _n_mask, _p_offset, _p_mask) \
+		{ \
+			.name = # _name, \
+			.reg_offset = _reg_off, \
+			.ndrive_offset = _n_offset, \
+			.ndrive_maskbits = _n_mask, \
+			.pdrive_offset = _p_offset, \
+			.pdrive_maskbits = _p_mask, \
+		}
+
+
+#define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \
+		_pud_sel_off, _curr_off, _smt_off, _curr_type) \
+	{ \
+		.name = # _name, \
+		.reg_offset = _reg_off, \
+		.base_bit = _base_bit, \
+		.pud_en_offset = _pud_en_off, \
+		.pud_sel_offset = _pud_sel_off, \
+		.curr_offset = _curr_off, \
+		.smt_offset = _smt_off, \
+		.curr_type = _curr_type, \
+	}
+
+
 #define RTK_PIN_MUX(_name, _mux_off, _mux_mask, ...) \
 	{ \
 		.name = # _name, \

@@ -68,8 +113,17 @@ struct rtd119x_pinctrl_desc {
 	unsigned int num_functions;
 	const struct rtd119x_pin_desc *muxes;
 	unsigned int num_muxes;
+	const struct rtd119x_pin_config_desc *configs;
+	unsigned int num_configs;
+	const struct rtd119x_pin_sconfig_desc *sconfigs;
+	unsigned int num_sconfigs;
 };
 
+#define PCONF_UNSUPP 0xffffffff
+#define PADDRI_4_8 1
+#define PADDRI_2_4 0
+
+
 #include "pinctrl-rtd1195.h"
 #include "pinctrl-rtd1295.h"
 

@@ -80,6 +134,15 @@ struct rtd119x_pinctrl {
 	const struct rtd119x_pinctrl_desc *info;
 };
 
+/* custom pinconf parameters */
+#define RTK_P_DRIVE	(PIN_CONFIG_END + 1)
+#define RTK_N_DRIVE	(PIN_CONFIG_END + 2)
+
+static const struct pinconf_generic_params rtd119x_custom_bindings[] = {
+	{"rtk,pdrive",  RTK_P_DRIVE,	0},
+	{"rtk,ndrive",	RTK_N_DRIVE,	0},
+};
+
 static int rtd119x_pinctrl_get_groups_count(struct pinctrl_dev *pcdev)
 {
 	struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);

@@ -165,6 +228,32 @@ static const struct rtd119x_pin_desc *rtd119x_pinctrl_find_mux(struct rtd119x_pi
 	return NULL;
 }
 
+static const struct rtd119x_pin_config_desc *rtd119x_pinctrl_find_config(struct rtd119x_pinctrl *data, const char *name)
+{
+	int i;
+
+	for (i = 0; i < data->info->num_configs; i++) {
+		if (strcmp(data->info->configs[i].name, name) == 0)
+			return &data->info->configs[i];
+	}
+
+	return NULL;
+}
+
+static const struct rtd119x_pin_sconfig_desc *rtd119x_pinctrl_find_sconfig(struct rtd119x_pinctrl *data, const char *name)
+{
+	int i;
+
+	for (i = 0; i < data->info->num_configs; i++) {
+		if (strcmp(data->info->sconfigs[i].name, name) == 0)
+			return &data->info->sconfigs[i];
+	}
+
+	return NULL;
+}
+
+
+
 static int rtd119x_pinctrl_set_one_mux(struct pinctrl_dev *pcdev,
 	unsigned int pin, const char *func_name)
 {

@@ -247,10 +336,123 @@ static const struct pinmux_ops rtd119x_pinmux_ops = {
 	.gpio_request_enable = rtd119x_pinctrl_gpio_request_enable,
 };
 
+
+static int rtd119x_pconf_parse_conf(struct rtd119x_pinctrl *data,
+	const char *pin_name, enum pin_config_param param,
+	enum pin_config_param arg)
+{
+	u8 set_val = 0;
+	u16 strength;
+	u32 val, mask;
+	int pulsel_off, pulen_off, smt_off, curr_off;
+	const struct rtd119x_pin_config_desc *config_desc;
+	const struct rtd119x_pin_sconfig_desc *sconfig_desc;
+
+	config_desc = rtd119x_pinctrl_find_config(data, pin_name);
+	if (!config_desc)
+		return -ENOTSUPP;
+
+	smt_off = config_desc->base_bit + config_desc->smt_offset;
+	curr_off = config_desc->base_bit + config_desc->curr_offset;
+	pulsel_off = config_desc->base_bit + config_desc->pud_sel_offset;
+	pulen_off = config_desc->base_bit + config_desc->pud_en_offset;
+
+	switch ((u32)param) {
+	case PIN_CONFIG_INPUT_SCHMITT:
+	case PIN_CONFIG_INPUT_SCHMITT_ENABLE:
+		set_val = arg;
+		val = readl(data->base + config_desc->reg_offset);
+		if (set_val)
+			val |= BIT(smt_off);
+		else
+			val &= ~BIT(smt_off);
+		writel(val, data->base + config_desc->reg_offset);
+		break;
+	case PIN_CONFIG_DRIVE_PUSH_PULL:
+		val = readl(data->base + config_desc->reg_offset);
+		if (set_val)
+			val |= BIT(pulen_off);
+		else
+			val &= ~BIT(pulen_off);
+		writel(val, data->base + config_desc->reg_offset);
+		break;
+	case PIN_CONFIG_BIAS_DISABLE:
+		val = readl(data->base + config_desc->reg_offset);
+		val &= ~BIT(pulen_off);
+		writel(val, data->base + config_desc->reg_offset);
+		break;
+	case PIN_CONFIG_BIAS_PULL_UP:
+		val = readl(data->base + config_desc->reg_offset);
+		val |= BIT(pulen_off) | BIT(pulsel_off);
+		writel(val, data->base + config_desc->reg_offset);
+		break;
+	case PIN_CONFIG_BIAS_PULL_DOWN:
+		val = readl(data->base + config_desc->reg_offset);
+		val |= BIT(pulen_off);
+		val &= ~BIT(pulsel_off);
+		writel(val, data->base + config_desc->reg_offset);
+		break;
+	case PIN_CONFIG_DRIVE_STRENGTH:
+		strength = arg;
+		val = readl(data->base + config_desc->reg_offset);
+		switch (config_desc->curr_type) {
+		case PADDRI_4_8:
+			if (strength == 4)
+				val &= ~BIT(curr_off);
+			else if (strength == 8)
+				val |= BIT(curr_off);
+			else
+				return -EINVAL;
+			break;
+		case PADDRI_2_4:
+			if (strength == 2)
+				val &= ~BIT(curr_off);
+			else if (strength == 4)
+				val |= BIT(curr_off);
+			else
+				return -EINVAL;
+			break;
+		case PCONF_UNSUPP:
+			pr_err("[%s] not support drive strength\n", config_desc->name);
+			return -ENOTSUPP;
+			break;
+		default:
+			return -EINVAL;
+		}
+		writel(val, data->base + config_desc->reg_offset);
+		break;
+	case RTK_P_DRIVE:
+		sconfig_desc = rtd119x_pinctrl_find_sconfig(data, pin_name);
+		if (!sconfig_desc)
+			return -ENOTSUPP;
+		set_val = arg;
+		val = readl(data->base + sconfig_desc->reg_offset);
+		mask = GENMASK(sconfig_desc->pdrive_offset +
+				sconfig_desc->pdrive_maskbits - 1, sconfig_desc->pdrive_offset);
+		val = (val & ~mask) | (set_val << sconfig_desc->pdrive_offset);
+		writel(val, data->base + sconfig_desc->reg_offset);
+		break;
+	case RTK_N_DRIVE:
+		sconfig_desc = rtd119x_pinctrl_find_sconfig(data, pin_name);
+		if (!sconfig_desc)
+			return -ENOTSUPP;
+		set_val = arg;
+		val = readl(data->base + sconfig_desc->reg_offset);
+		mask = GENMASK(sconfig_desc->ndrive_offset +
+				sconfig_desc->ndrive_maskbits - 1, sconfig_desc->ndrive_offset);
+		val = (val & ~mask) | (set_val << sconfig_desc->ndrive_offset);
+		writel(val, data->base + sconfig_desc->reg_offset);
+		break;
+	default:
+		break;
+	}
+
+	return 0;
+}
+
 static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned pinnr,
 		unsigned long *config)
 {
-	//struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
 	unsigned int param = pinconf_to_config_param(*config);
 	unsigned int arg = 0;
 

@@ -266,15 +468,62 @@ static int rtd119x_pin_config_get(struct pinctrl_dev *pcdev, unsigned pinnr,
 static int rtd119x_pin_config_set(struct pinctrl_dev *pcdev, unsigned pinnr,
 		unsigned long *configs, unsigned num_configs)
 {
-	//struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+	struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+	const struct pinctrl_pin_desc *pin_desc;
+	const char *pin_name;
+	int i;
+	int ret = 0;
+
+	pin_desc = rtd119x_pinctrl_get_pin_by_number(data, pinnr);
+	if (!pin_desc)
+		return -ENOTSUPP;
+
+	pin_name = pin_desc->name;
+
+	for (i = 0; i < num_configs; i++) {
+		ret = rtd119x_pconf_parse_conf(data, pin_name,
+			pinconf_to_config_param(configs[i]),
+			pinconf_to_config_argument(configs[i]));
+		if (ret < 0)
+			return ret;
+	}
 
 	return 0;
 }
 
+
+static int rtd119x_pin_config_group_set(struct pinctrl_dev *pcdev, unsigned group,
+				unsigned long *configs, unsigned num_configs)
+{
+	struct rtd119x_pinctrl *data = pinctrl_dev_get_drvdata(pcdev);
+	const unsigned int *pins;
+	unsigned int num_pins;
+	const char *group_name;
+	int i, ret;
+
+		group_name = data->info->groups[group].name;
+
+	ret = rtd119x_pinctrl_get_group_pins(pcdev, group, &pins, &num_pins);
+	if (ret) {
+		dev_err(pcdev->dev, "Getting pins for group %s failed\n", group_name);
+		return ret;
+	}
+
+	for (i = 0; i < num_pins; i++) {
+		ret = rtd119x_pin_config_set(pcdev, pins[i], configs, num_configs);
+		if (ret)
+			return ret;
+	}
+
+	return 0;
+ }
+
+
 static const struct pinconf_ops rtd119x_pinconf_ops = {
 	.is_generic = true,
 	.pin_config_get = rtd119x_pin_config_get,
 	.pin_config_set = rtd119x_pin_config_set,
+	.pin_config_group_set = rtd119x_pin_config_group_set,
 };
 
 static void rtd119x_pinctrl_selftest(struct rtd119x_pinctrl *data)

@@ -356,8 +605,8 @@ static int rtd119x_pinctrl_probe(struct platform_device *pdev)
 	data->desc.pctlops = &rtd119x_pinctrl_ops;
 	data->desc.pmxops = &rtd119x_pinmux_ops;
 	data->desc.confops = &rtd119x_pinconf_ops;
-	data->desc.custom_params = NULL;
-	data->desc.num_custom_params = 0;
+	data->desc.custom_params = rtd119x_custom_bindings;
+	data->desc.num_custom_params = ARRAY_SIZE(rtd119x_custom_bindings);
 	data->desc.owner = THIS_MODULE;
 
 	data->pcdev = pinctrl_register(&data->desc, &pdev->dev, data);

242 lines not on this page · raw message

index 8eaab8a0dbf3..9f3471d02221 100644
@@ -23,6 +23,11 @@ enum rtd1195_iso_pins {
 	RTD1195_ISO_ETN_LED_RXTX,
 	RTD1195_ISO_I2C_SCL_6,
 	RTD1195_ISO_I2C_SDA_6,
+	RTD1195_ISO_AI_LOC,
+	RTD1195_ISO_EJTAG_AVCPU_LOC,
+	RTD1195_ISO_UR1_LOC,
+	RTD1195_ISO_PWM_01_OPEN_DRAIN,
+	RTD1195_ISO_PWM_23_OPEN_DRAIN,
 };
 
 static const struct pinctrl_pin_desc rtd1195_iso_pins[] = {

@@ -47,6 +52,11 @@ static const struct pinctrl_pin_desc rtd1195_iso_pins[] = {
 	PINCTRL_PIN(RTD1195_ISO_ETN_LED_RXTX, "etn_led_rxtx"),
 	PINCTRL_PIN(RTD1195_ISO_I2C_SCL_6, "i2c_scl_6"),
 	PINCTRL_PIN(RTD1195_ISO_I2C_SDA_6, "i2c_sda_6"),
+	PINCTRL_PIN(RTD1195_ISO_AI_LOC, "ai_loc"),
+	PINCTRL_PIN(RTD1195_ISO_EJTAG_AVCPU_LOC, "ejtag_avcpu_loc"),
+	PINCTRL_PIN(RTD1195_ISO_UR1_LOC, "ur1_loc"),
+	PINCTRL_PIN(RTD1195_ISO_PWM_01_OPEN_DRAIN, "pwm_01_open_drain"),
+	PINCTRL_PIN(RTD1195_ISO_PWM_23_OPEN_DRAIN, "pwm_23_open_drain"),
 };
 
 static const unsigned int rtd1195_iso_gpio_0_pins[] = { RTD1195_ISO_GPIO_0 };

@@ -70,6 +80,12 @@ static const unsigned int rtd1195_etn_led_link_pins[] = { RTD1195_ISO_ETN_LED_LI
 static const unsigned int rtd1195_etn_led_rxtx_pins[] = { RTD1195_ISO_ETN_LED_RXTX };
 static const unsigned int rtd1195_i2c_scl_6_pins[] = { RTD1195_ISO_I2C_SCL_6 };
 static const unsigned int rtd1195_i2c_sda_6_pins[] = { RTD1195_ISO_I2C_SDA_6 };
+static const unsigned int rtd1195_ai_loc_pins[] = { RTD1195_ISO_AI_LOC };
+static const unsigned int rtd1195_ejtag_avcpu_loc_pins[] = { RTD1195_ISO_EJTAG_AVCPU_LOC };
+static const unsigned int rtd1195_ur1_loc_pins[] = { RTD1195_ISO_UR1_LOC };
+static const unsigned int rtd1195_pwm_01_open_drain_pins[] = { RTD1195_ISO_PWM_01_OPEN_DRAIN };
+static const unsigned int rtd1195_pwm_23_open_drain_pins[] = { RTD1195_ISO_PWM_23_OPEN_DRAIN };
+
 
 #define RTD1195_GROUP(_name) \
 	{ \

@@ -100,6 +116,11 @@ static const struct rtd119x_pin_group_desc rtd1195_iso_pin_groups[] = {
 	RTD1195_GROUP(etn_led_rxtx),
 	RTD1195_GROUP(i2c_scl_6),
 	RTD1195_GROUP(i2c_sda_6),
+	RTD1195_GROUP(ai_loc),
+	RTD1195_GROUP(ejtag_avcpu_loc),
+	RTD1195_GROUP(ur1_loc),
+	RTD1195_GROUP(pwm_01_open_drain),
+	RTD1195_GROUP(pwm_23_open_drain),
 };
 
 static const char * const rtd1195_iso_gpio_groups[] = {

@@ -112,13 +133,22 @@ static const char * const rtd1195_iso_gpio_groups[] = {
 	"etn_led_link", "etn_led_rxtx",
 	"i2c_scl_6", "i2c_sda_6",
 };
-static const char * const rtd1195_iso_ai_groups[] = {
-	"usb0", "usb1", "vfd_cs_n", "vfd_clk",
-	"ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n"
+static const char * const rtd1195_iso_ai_ur1_groups[] = {
+	"ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ai_loc"
+};
+
+static const char * const rtd1195_iso_ai_vfd_groups[] = {
+	"usb0", "usb1", "vfd_cs_n", "vfd_clk", "ai_loc"
+};
+
+static const char * const rtd1195_iso_avcpu_ejtag_iso_groups[] = {
+	"vfd_cs_n", "vfd_clk", "vfd_d", "usb0", "usb1", "ejtag_avcpu_loc"
 };
-static const char * const rtd1195_iso_avcpu_ejtag_groups[] = {
-	"vfd_cs_n", "vfd_clk", "vfd_d", "usb0", "usb1"
+static const char * const rtd1195_iso_avcpu_ejtag_misc_loc_groups[] = {
+	"ejtag_avcpu_loc"
 };
+
+
 static const char * const rtd1195_iso_etn_led_groups[] = { "etn_led_link", "etn_led_rxtx" };
 static const char * const rtd1195_iso_i2c0_groups[] = { "i2c_scl_0", "i2c_sda_0" };
 static const char * const rtd1195_iso_i2c2_groups[] = { "vfd_d" };

@@ -131,8 +161,16 @@ static const char * const rtd1195_iso_pwm_groups[] = {
 };
 static const char * const rtd1195_iso_standby_dbg_groups[] = { "ir_rx", "usb0", "usb1" };
 static const char * const rtd1195_iso_uart0_groups[] = { "ur0_rx", "ur0_tx" };
-static const char * const rtd1195_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n" };
+static const char * const rtd1195_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ur1_loc" };
+static const char * const rtd1195_iso_ur1_misc_groups[] = { "ur1_loc" };
 static const char * const rtd1195_iso_vfd_groups[] = { "vfd_cs_n", "vfd_clk", "vfd_d" };
+static const char * const rtd1195_iso_pwm_01_normal_groups[] = { "pwm_01_open_drain" };
+static const char * const rtd1195_iso_pwm_23_normal_groups[] = { "pwm_23_open_drain" };
+static const char * const rtd1195_iso_pwm_01_open_drain_groups[] = { "pwm_01_open_drain" };
+static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = { "pwm_23_open_drain" };
+
+
+
 
 #define RTD1195_FUNC(_name) \
 	{ \

@@ -143,8 +181,10 @@ static const char * const rtd1195_iso_vfd_groups[] = { "vfd_cs_n", "vfd_clk", "v
 
 static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = {
 	RTD1195_FUNC(gpio),
-	RTD1195_FUNC(ai),
-	RTD1195_FUNC(avcpu_ejtag),
+	RTD1195_FUNC(ai_ur1),
+	RTD1195_FUNC(ai_vfd),
+	RTD1195_FUNC(avcpu_ejtag_iso),
+	RTD1195_FUNC(avcpu_ejtag_misc_loc),
 	RTD1195_FUNC(etn_led),
 	RTD1195_FUNC(i2c0),
 	RTD1195_FUNC(i2c2),

@@ -156,7 +196,12 @@ static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = {
 	RTD1195_FUNC(standby_dbg),
 	RTD1195_FUNC(uart0),
 	RTD1195_FUNC(uart1),
+	RTD1195_FUNC(ur1_misc),
 	RTD1195_FUNC(vfd),
+	RTD1195_FUNC(pwm_01_normal),
+	RTD1195_FUNC(pwm_23_normal),
+	RTD1195_FUNC(pwm_01_open_drain),
+	RTD1195_FUNC(pwm_23_open_drain),
 };
 
 #undef RTD1195_FUNC

@@ -166,17 +211,17 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = {
 		RTK_PIN_FUNC(0x0 << 0, "gpio"),
 		RTK_PIN_FUNC(0x1 << 0, "vfd"),
 		RTK_PIN_FUNC(0x2 << 0, "i2c2"),
-		RTK_PIN_FUNC(0x3 << 0, "avcpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 0, "avcpu_ejtag_iso")),
 	RTK_PIN_MUX(vfd_clk, 0x10, GENMASK(3, 2),
 		RTK_PIN_FUNC(0x0 << 2, "gpio"),
 		RTK_PIN_FUNC(0x1 << 2, "vfd"),
-		RTK_PIN_FUNC(0x2 << 2, "ai"),
-		RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag")),
+		RTK_PIN_FUNC(0x2 << 2, "ai_vfd"),
+		RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag_iso")),
 	RTK_PIN_MUX(vfd_cs_n, 0x10, GENMASK(5, 4),
 		RTK_PIN_FUNC(0x0 << 4, "gpio"),
 		RTK_PIN_FUNC(0x1 << 4, "vfd"),
-		RTK_PIN_FUNC(0x2 << 4, "ai"),
-		RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag")),
+		RTK_PIN_FUNC(0x2 << 4, "ai_vfd"),
+		RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag_iso")),
 	RTK_PIN_MUX(ir_rx, 0x10, GENMASK(7, 6),
 		RTK_PIN_FUNC(0x0 << 6, "gpio"),
 		RTK_PIN_FUNC(0x1 << 6, "ir_rx"),

@@ -184,31 +229,31 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = {
 	RTK_PIN_MUX(usb0, 0x10, GENMASK(9, 8),
 		RTK_PIN_FUNC(0x0 << 8, "gpio"),
 		RTK_PIN_FUNC(0x1 << 8, "standby_dbg"),
-		RTK_PIN_FUNC(0x2 << 8, "ai"),
-		RTK_PIN_FUNC(0x3 << 8, "avcpu_ejtag")),
+		RTK_PIN_FUNC(0x2 << 8, "ai_vfd"),
+		RTK_PIN_FUNC(0x3 << 8, "avcpu_ejtag_iso")),
 	RTK_PIN_MUX(usb1, 0x10, GENMASK(11, 10),
 		RTK_PIN_FUNC(0x0 << 10, "gpio"),
 		RTK_PIN_FUNC(0x1 << 10, "standby_dbg"),
-		RTK_PIN_FUNC(0x2 << 10, "ai"),
-		RTK_PIN_FUNC(0x3 << 10, "avcpu_ejtag")),
+		RTK_PIN_FUNC(0x2 << 10, "ai_vfd"),
+		RTK_PIN_FUNC(0x3 << 10, "avcpu_ejtag_iso")),
 	RTK_PIN_MUX(ur1_rx, 0x10, GENMASK(13, 12),
 		RTK_PIN_FUNC(0x0 << 12, "gpio"),
 		RTK_PIN_FUNC(0x1 << 12, "uart1"),
-		RTK_PIN_FUNC(0x2 << 12, "ai"),
+		RTK_PIN_FUNC(0x2 << 12, "ai_ur1"),
 		RTK_PIN_FUNC(0x3 << 12, "pwm")),
 	RTK_PIN_MUX(ur1_tx, 0x10, GENMASK(15, 14),
 		RTK_PIN_FUNC(0x0 << 14, "gpio"),
 		RTK_PIN_FUNC(0x1 << 14, "uart1"),
-		RTK_PIN_FUNC(0x2 << 14, "ai"),
+		RTK_PIN_FUNC(0x2 << 14, "ai_ur1"),
 		RTK_PIN_FUNC(0x3 << 14, "pwm")),
 	RTK_PIN_MUX(ur1_rts_n, 0x10, GENMASK(17, 16),
 		RTK_PIN_FUNC(0x0 << 16, "gpio"),
 		RTK_PIN_FUNC(0x1 << 16, "uart1"),
-		RTK_PIN_FUNC(0x2 << 16, "ai")),
+		RTK_PIN_FUNC(0x2 << 16, "ai_ur1")),
 	RTK_PIN_MUX(ur1_cts_n, 0x10, GENMASK(19, 18),
 		RTK_PIN_FUNC(0x0 << 18, "gpio"),
 		RTK_PIN_FUNC(0x1 << 18, "uart1"),
-		RTK_PIN_FUNC(0x2 << 18, "ai")),
+		RTK_PIN_FUNC(0x2 << 18, "ai_ur1")),
 	RTK_PIN_MUX(ur0_rx, 0x10, GENMASK(21, 20),
 		RTK_PIN_FUNC(0x0 << 20, "gpio"),
 		RTK_PIN_FUNC(0x1 << 20, "uart0"),

@@ -242,13 +287,44 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = {
 		RTK_PIN_FUNC(0x0 << 4, "gpio"),
 		RTK_PIN_FUNC(0x1 << 4, "ir_tx"),
 		RTK_PIN_FUNC(0x2 << 4, "i2c3")),
-	/* pwm_23_open_drain_switch */
-	/* pwm_01_open_drain_switch */
-	/* ur1_loc */
-	/* ejtag_avcpu_loc */
-	/* ai_loc */
+	RTK_PIN_MUX(pwm_23_open_drain, 0x14, GENMASK(24, 24),
+		RTK_PIN_FUNC(0x0 << 24, "pwm_23_normal"),
+		RTK_PIN_FUNC(0x1 << 24, "pwm_23_open_drain")),
+	RTK_PIN_MUX(pwm_01_open_drain, 0x14, GENMASK(25, 25),
+		RTK_PIN_FUNC(0x0 << 25, "pwm_01_normal"),
+		RTK_PIN_FUNC(0x1 << 25, "pwm_01_open_drain")),
+	RTK_PIN_MUX(ur1_loc, 0x14, GENMASK(27, 26),
+		RTK_PIN_FUNC(0x1 << 26, "uart1"),
+		RTK_PIN_FUNC(0x2 << 26, "ur1_misc")),
+	RTK_PIN_MUX(ejtag_avcpu_loc, 0x14, GENMASK(29, 28),
+		RTK_PIN_FUNC(0x1 << 28, "avcpu_ejtag_iso"),
+		RTK_PIN_FUNC(0x2 << 28, "avcpu_ejtag_misc_loc")),
+	RTK_PIN_MUX(ai_loc, 0x14, GENMASK(31, 30),
+		RTK_PIN_FUNC(0x1 << 30, "ai_ur1"),
+		RTK_PIN_FUNC(0x2 << 30, "ai_vfd")),
+};
+
+static const struct rtd119x_pin_config_desc rtd1195_iso_configs[] = {
+	RTK_PIN_CONFIG(ir_rx, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(vfd_cs_n, 0x0, 12, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(vfd_clk, 0x0, 16, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(vfd_d, 0x0, 20, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(i2c_sda_0, 0x0, 24, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(i2c_scl_0, 0x0, 28, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(ur1_rx, 0x4, 0, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(ur1_tx, 0x4, 4, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(ur1_rts_n, 0x4, 8, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(ur1_cts_n, 0x4, 12, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(ur0_rx, 0x4, 16, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(ur0_tx, 0x4, 20, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(etn_led_link, 0x4, 24, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(etn_led_rxtx, 0x4, 28, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(i2c_sda_6, 0x8, 12, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(i2c_scl_6, 0x8, 16, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(ir_tx, 0x8, 20, 1, 0, 2, 3, PADDRI_2_4),
 };
 
+
 static const struct rtd119x_pinctrl_desc rtd1195_iso_pinctrl_desc = {
 	.pins = rtd1195_iso_pins,
 	.num_pins = ARRAY_SIZE(rtd1195_iso_pins),

@@ -258,6 +334,8 @@ static const struct rtd119x_pinctrl_desc rtd1195_iso_pinctrl_desc = {
 	.num_functions = ARRAY_SIZE(rtd1195_iso_pin_functions),
 	.muxes = rtd1195_iso_muxes,
 	.num_muxes = ARRAY_SIZE(rtd1195_iso_muxes),
+	.configs = rtd1195_iso_configs,
+	.num_configs = ARRAY_SIZE(rtd1195_iso_configs),
 };
 
 /* CRT */

@@ -323,6 +401,9 @@ enum rtd1195_crt_pins {
 	RTD1195_SENSOR_RST,
 	RTD1195_SENSOR_STB_0,
 	RTD1195_SENSOR_STB_1,
+	RTD1195_EJTAG_SCPU_LOC,
+	RTD1195_HI_LOC,
+	RTD1195_AO_LOC,
 };
 
 static const struct pinctrl_pin_desc rtd1195_crt_pins[] = {

@@ -386,6 +467,9 @@ static const struct pinctrl_pin_desc rtd1195_crt_pins[] = {
 	PINCTRL_PIN(RTD1195_SENSOR_RST, "sensor_rst"),
 	PINCTRL_PIN(RTD1195_SENSOR_STB_0, "sensor_stb_0"),
 	PINCTRL_PIN(RTD1195_SENSOR_STB_1, "sensor_stb_1"),
+	PINCTRL_PIN(RTD1195_EJTAG_SCPU_LOC, "ejtag_scpu_loc"),
+	PINCTRL_PIN(RTD1195_HI_LOC, "hif_loc"),
+	PINCTRL_PIN(RTD1195_AO_LOC, "ao_loc"),
 };
 
 static const unsigned int rtd1195_gpio_0_pins[] = { RTD1195_GPIO_0 };

@@ -448,6 +532,14 @@ static const unsigned int rtd1195_sensor_cko_1_pins[] = { RTD1195_SENSOR_CKO_1 }
 static const unsigned int rtd1195_sensor_rst_pins[] = { RTD1195_SENSOR_RST };
 static const unsigned int rtd1195_sensor_stb_0_pins[] = { RTD1195_SENSOR_STB_0 };
 static const unsigned int rtd1195_sensor_stb_1_pins[] = { RTD1195_SENSOR_STB_1 };
+static const unsigned int rtd1195_ejtag_scpu_loc_pins[] = { RTD1195_EJTAG_SCPU_LOC };
+static const unsigned int rtd1195_hif_loc_pins[] = { RTD1195_HI_LOC };
+static const unsigned int rtd1195_ao_loc_pins[] = { RTD1195_AO_LOC };
+
+
+
+
+
 
 #define RTD1195_GROUP(_name) \
 	{ \

@@ -517,6 +609,9 @@ static const struct rtd119x_pin_group_desc rtd1195_crt_pin_groups[] = {
 	RTD1195_GROUP(sensor_rst),
 	RTD1195_GROUP(sensor_stb_0),
 	RTD1195_GROUP(sensor_stb_1),
+	RTD1195_GROUP(ejtag_scpu_loc),
+	RTD1195_GROUP(hif_loc),
+	RTD1195_GROUP(ao_loc),
 };
 
 static const char * const rtd1195_crt_gpio_groups[] = {

@@ -540,11 +635,16 @@ static const char * const rtd1195_crt_gpio_groups[] = {
 	"sensor_stb_0", "sensor_stb_1",
 };
 
-static const char * const rtd1195_crt_ao_groups[] = {
-	"gpio_4", "gpio_5", "gpio_6", "gpio_7",
-	"tp0_data", "tp0_sync", "tp0_valid", "tp0_clk",
+static const char * const rtd1195_crt_ao_tp0_groups[] = {
+	"tp0_data", "tp0_sync", "tp0_valid", "tp0_clk", "ao_loc"
+};
+
+static const char * const rtd1195_crt_ao_gpio_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7", "ao_loc"
 };
-static const char * const rtd1195_crt_avcpu_ejtag_groups[] = {
+
+
+static const char * const rtd1195_crt_avcpu_ejtag_misc_groups[] = {
 	"nf_rdy", "nf_rd_n", "nf_dd_5", "nf_dd_6", "nf_dd_7"
 };
 static const char * const rtd1195_crt_cpu_loop_groups[] = { "usb_id" };

@@ -555,10 +655,15 @@ static const char * const rtd1195_crt_emmc_groups[] = {
 static const char * const rtd1195_crt_gspi_groups[] = {
 	"gpio_0", "gpio_1", "gpio_2", "gpio_3",
 };
-static const char * const rtd1195_crt_hif_groups[] = {
-	"gpio_0", "gpio_1", "gpio_2", "gpio_3",
-	"nf_dd_4", "nf_wr_n", "nf_ale", "nf_cle",
+static const char * const rtd1195_crt_hif_nf_groups[] = {
+	"nf_dd_4", "nf_wr_n", "nf_ale", "nf_cle", "hif_loc"
 };
+
+static const char * const rtd1195_crt_hif_misc_groups[] = {
+	"gpio_0", "gpio_1", "gpio_2", "gpio_3", "hif_loc"
+};
+
+
 static const char * const rtd1195_crt_i2c1_groups[] = { "i2c_scl_1", "i2c_sda_1" };
 static const char * const rtd1195_crt_i2c2_groups[] = { "tp1_sync", "tp1_clk" };
 static const char * const rtd1195_crt_i2c3_groups[] = { "tp1_data", "tp1_valid" };

@@ -572,9 +677,13 @@ static const char * const rtd1195_crt_nand_groups[] = {
 	"nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
 	"nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1",
 };
-static const char * const rtd1195_crt_scpu_ejtag_groups[] = {
-	"mmc_data_0", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp"
+static const char * const rtd1195_crt_scpu_ejtag_gpio_groups[] = {
+	"gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc"
+};
+static const char * const rtd1195_crt_scpu_ejtag_cr_groups[] = {
+	"mmc_data_0", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp", "ejtag_scpu_loc"
 };
+
 static const char * const rtd1195_crt_sdio_groups[] = {
 	"sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "sdio_cmd",
 };

@@ -598,12 +707,14 @@ static const char * const rtd1195_crt_usb_groups[] = { "sensor_cko_1" };
 
 static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = {
 	RTD1195_FUNC(gpio),
-	RTD1195_FUNC(ao),
-	RTD1195_FUNC(avcpu_ejtag),
+	RTD1195_FUNC(ao_tp0),
+	RTD1195_FUNC(ao_gpio),
+	RTD1195_FUNC(avcpu_ejtag_misc),
 	RTD1195_FUNC(cpu_loop),
 	RTD1195_FUNC(emmc),
 	RTD1195_FUNC(gspi),
-	RTD1195_FUNC(hif),
+	RTD1195_FUNC(hif_misc),
+	RTD1195_FUNC(hif_nf),
 	RTD1195_FUNC(i2c1),
 	RTD1195_FUNC(i2c2),
 	RTD1195_FUNC(i2c3),

@@ -611,7 +722,8 @@ static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = {
 	RTD1195_FUNC(i2c5),
 	RTD1195_FUNC(mmc),
 	RTD1195_FUNC(nand),
-	RTD1195_FUNC(scpu_ejtag),
+	RTD1195_FUNC(scpu_ejtag_gpio),
+	RTD1195_FUNC(scpu_ejtag_cr),
 	RTD1195_FUNC(sdio),
 	RTD1195_FUNC(sensor),
 	RTD1195_FUNC(spdif),

@@ -628,27 +740,27 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
 		RTK_PIN_FUNC(0x0 << 2, "gpio"),
 		RTK_PIN_FUNC(0x1 << 2, "nand"),
 		RTK_PIN_FUNC(0x2 << 2, "emmc"),
-		RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 2, "avcpu_ejtag_misc")),
 	RTK_PIN_MUX(nf_rd_n, 0x60, GENMASK(5, 4),
 		RTK_PIN_FUNC(0x0 << 4, "gpio"),
 		RTK_PIN_FUNC(0x1 << 4, "nand"),
 		RTK_PIN_FUNC(0x2 << 4, "emmc"),
-		RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 4, "avcpu_ejtag_misc")),
 	RTK_PIN_MUX(nf_wr_n, 0x60, GENMASK(7, 6),
 		RTK_PIN_FUNC(0x0 << 6, "gpio"),
 		RTK_PIN_FUNC(0x1 << 6, "nand"),
 		RTK_PIN_FUNC(0x2 << 6, "emmc"),
-		RTK_PIN_FUNC(0x3 << 6, "hif")),
+		RTK_PIN_FUNC(0x3 << 6, "hif_nf")),
 	RTK_PIN_MUX(nf_ale, 0x60, GENMASK(9, 8),
 		RTK_PIN_FUNC(0x0 << 8, "gpio"),
 		RTK_PIN_FUNC(0x1 << 8, "nand"),
 		RTK_PIN_FUNC(0x2 << 8, "emmc"),
-		RTK_PIN_FUNC(0x3 << 8, "hif")),
+		RTK_PIN_FUNC(0x3 << 8, "hif_nf")),
 	RTK_PIN_MUX(nf_cle, 0x60, GENMASK(11, 10),
 		RTK_PIN_FUNC(0x0 << 10, "gpio"),
 		RTK_PIN_FUNC(0x1 << 10, "nand"),
 		RTK_PIN_FUNC(0x2 << 10, "emmc"),
-		RTK_PIN_FUNC(0x3 << 10, "hif")),
+		RTK_PIN_FUNC(0x3 << 10, "hif_nf")),
 	RTK_PIN_MUX(nf_ce_n_0, 0x60, GENMASK(13, 12),
 		RTK_PIN_FUNC(0x0 << 12, "gpio"),
 		RTK_PIN_FUNC(0x1 << 12, "nand")),

@@ -675,22 +787,22 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
 		RTK_PIN_FUNC(0x0 << 24, "gpio"),
 		RTK_PIN_FUNC(0x1 << 24, "nand"),
 		RTK_PIN_FUNC(0x2 << 24, "emmc"),
-		RTK_PIN_FUNC(0x3 << 24, "hif")),
+		RTK_PIN_FUNC(0x3 << 24, "hif_nf")),
 	RTK_PIN_MUX(nf_dd_5, 0x60, GENMASK(27, 26),
 		RTK_PIN_FUNC(0x0 << 26, "gpio"),
 		RTK_PIN_FUNC(0x1 << 26, "nand"),
 		RTK_PIN_FUNC(0x2 << 26, "emmc"),
-		RTK_PIN_FUNC(0x3 << 26, "avcpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 26, "avcpu_ejtag_misc")),
 	RTK_PIN_MUX(nf_dd_6, 0x60, GENMASK(29, 28),
 		RTK_PIN_FUNC(0x0 << 28, "gpio"),
 		RTK_PIN_FUNC(0x1 << 28, "nand"),
 		RTK_PIN_FUNC(0x2 << 28, "emmc"),
-		RTK_PIN_FUNC(0x3 << 28, "avcpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 28, "avcpu_ejtag_misc")),
 	RTK_PIN_MUX(nf_dd_7, 0x60, GENMASK(31, 30),
 		RTK_PIN_FUNC(0x0 << 30, "gpio"),
 		RTK_PIN_FUNC(0x1 << 30, "nand"),
 		RTK_PIN_FUNC(0x2 << 30, "emmc"),
-		RTK_PIN_FUNC(0x3 << 30, "avcpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 30, "avcpu_ejtag_misc")),
 
 	RTK_PIN_MUX(sdio_cmd, 0x64, GENMASK(1, 0),
 		RTK_PIN_FUNC(0x0 << 0, "gpio"),

@@ -714,22 +826,22 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
 	RTK_PIN_MUX(mmc_cmd, 0x64, GENMASK(17, 16),
 		RTK_PIN_FUNC(0x0 << 16, "gpio"),
 		RTK_PIN_FUNC(0x1 << 16, "mmc"),
-		RTK_PIN_FUNC(0x3 << 16, "scpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 16, "scpu_ejtag_cr")),
 	RTK_PIN_MUX(mmc_clk, 0x64, GENMASK(19, 18),
 		RTK_PIN_FUNC(0x0 << 18, "gpio"),
 		RTK_PIN_FUNC(0x1 << 18, "mmc"),
-		RTK_PIN_FUNC(0x3 << 18, "scpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 18, "scpu_ejtag_cr")),
 	RTK_PIN_MUX(mmc_wp, 0x64, GENMASK(21, 20),
 		RTK_PIN_FUNC(0x0 << 20, "gpio"),
 		RTK_PIN_FUNC(0x1 << 20, "mmc"),
-		RTK_PIN_FUNC(0x3 << 20, "scpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 20, "scpu_ejtag_cr")),
 	RTK_PIN_MUX(mmc_cd, 0x64, GENMASK(23, 22),
 		RTK_PIN_FUNC(0x0 << 22, "gpio"),
 		RTK_PIN_FUNC(0x1 << 22, "mmc")),
 	RTK_PIN_MUX(mmc_data_0, 0x64, GENMASK(25, 24),
 		RTK_PIN_FUNC(0x0 << 24, "gpio"),
 		RTK_PIN_FUNC(0x1 << 24, "mmc"),
-		RTK_PIN_FUNC(0x3 << 24, "scpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 24, "scpu_ejtag_cr")),
 	RTK_PIN_MUX(mmc_data_1, 0x64, GENMASK(27, 26),
 		RTK_PIN_FUNC(0x0 << 26, "gpio"),
 		RTK_PIN_FUNC(0x1 << 26, "mmc")),

@@ -739,28 +851,28 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
 	RTK_PIN_MUX(mmc_data_3, 0x64, GENMASK(31, 30),
 		RTK_PIN_FUNC(0x0 << 30, "gpio"),
 		RTK_PIN_FUNC(0x1 << 30, "mmc"),
-		RTK_PIN_FUNC(0x3 << 30, "scpu_ejtag")),
+		RTK_PIN_FUNC(0x3 << 30, "scpu_ejtag_cr")),
 
 	RTK_PIN_MUX(tp0_data, 0x68, GENMASK(1, 0),
 		RTK_PIN_FUNC(0x0 << 0, "tp0"),
 		RTK_PIN_FUNC(0x1 << 0, "tp1"),
 		RTK_PIN_FUNC(0x2 << 0, "gpio"),
-		RTK_PIN_FUNC(0x3 << 0, "ao")),
+		RTK_PIN_FUNC(0x3 << 0, "ao_tp0")),
 	RTK_PIN_MUX(tp0_sync, 0x68, GENMASK(3, 2),
 		RTK_PIN_FUNC(0x0 << 2, "tp0"),
 		RTK_PIN_FUNC(0x1 << 2, "tp1"),
 		RTK_PIN_FUNC(0x2 << 2, "gpio"),
-		RTK_PIN_FUNC(0x3 << 2, "ao")),
+		RTK_PIN_FUNC(0x3 << 2, "ao_tp0")),
 	RTK_PIN_MUX(tp0_valid, 0x68, GENMASK(5, 4),
 		RTK_PIN_FUNC(0x0 << 4, "tp0"),
 		RTK_PIN_FUNC(0x1 << 4, "tp1"),
 		RTK_PIN_FUNC(0x2 << 4, "gpio"),
-		RTK_PIN_FUNC(0x3 << 4, "ao")),
+		RTK_PIN_FUNC(0x3 << 4, "ao_tp0")),
 	RTK_PIN_MUX(tp0_clk, 0x68, GENMASK(7, 6),
 		RTK_PIN_FUNC(0x0 << 6, "tp0"),
 		RTK_PIN_FUNC(0x1 << 6, "tp1"),
 		RTK_PIN_FUNC(0x2 << 6, "gpio"),
-		RTK_PIN_FUNC(0x3 << 6, "ao")),
+		RTK_PIN_FUNC(0x3 << 6, "ao_tp0")),
 	RTK_PIN_MUX(tp1_data, 0x68, GENMASK(17, 16),
 		RTK_PIN_FUNC(0x0 << 16, "tp1"),
 		RTK_PIN_FUNC(0x1 << 16, "tp0"),

@@ -810,8 +922,12 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
 	RTK_PIN_MUX(usb_id, 0x6c, GENMASK(17, 16),
 		RTK_PIN_FUNC(0x1 << 16, "gpio"),
 		RTK_PIN_FUNC(0x2 << 16, "cpu_loop")),
-	/* hi_loc */
-	/* ejtag_scpu_loc */
+	RTK_PIN_MUX(hif_loc, 0x6c, GENMASK(19, 18),
+		RTK_PIN_FUNC(0x1 << 18, "hif_misc"),
+		RTK_PIN_FUNC(0x2 << 18, "hif_nf")),
+	RTK_PIN_MUX(ejtag_scpu_loc, 0x6c, GENMASK(21, 20),
+		RTK_PIN_FUNC(0x1 << 20, "scpu_ejtag_gpio"),
+		RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag_cr")),
 	RTK_PIN_MUX(sensor_stb_1, 0x6c, GENMASK(23, 22),
 		RTK_PIN_FUNC(0x0 << 22, "gpio")),
 	RTK_PIN_MUX(sensor_stb_0, 0x6c, GENMASK(25, 24),

@@ -829,47 +945,113 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
 	RTK_PIN_MUX(gpio_0, 0x70, GENMASK(2, 0),
 		RTK_PIN_FUNC(0x1 << 0, "gpio"),
 		RTK_PIN_FUNC(0x2 << 0, "uart1"),
-		RTK_PIN_FUNC(0x3 << 0, "hif"),
+		RTK_PIN_FUNC(0x3 << 0, "hif_misc"),
 		RTK_PIN_FUNC(0x4 << 0, "gspi")),
 	RTK_PIN_MUX(gpio_1, 0x70, GENMASK(5, 3),
 		RTK_PIN_FUNC(0x1 << 3, "gpio"),
 		RTK_PIN_FUNC(0x2 << 3, "uart1"),
-		RTK_PIN_FUNC(0x3 << 3, "hif"),
+		RTK_PIN_FUNC(0x3 << 3, "hif_misc"),
 		RTK_PIN_FUNC(0x4 << 3, "gspi")),
 	RTK_PIN_MUX(gpio_2, 0x70, GENMASK(8, 6),
 		RTK_PIN_FUNC(0x1 << 6, "gpio"),
 		RTK_PIN_FUNC(0x2 << 6, "uart1"),
-		RTK_PIN_FUNC(0x3 << 6, "hif"),
+		RTK_PIN_FUNC(0x3 << 6, "hif_misc"),
 		RTK_PIN_FUNC(0x4 << 6, "gspi")),
 	RTK_PIN_MUX(gpio_3, 0x70, GENMASK(11, 9),
 		RTK_PIN_FUNC(0x1 << 9, "gpio"),
 		RTK_PIN_FUNC(0x2 << 9, "uart1"),
-		RTK_PIN_FUNC(0x3 << 9, "hif"),
+		RTK_PIN_FUNC(0x3 << 9, "hif_misc"),
 		RTK_PIN_FUNC(0x4 << 9, "gspi")),
 	RTK_PIN_MUX(gpio_4, 0x70, GENMASK(13, 12),
 		RTK_PIN_FUNC(0x1 << 12, "gpio"),
-		RTK_PIN_FUNC(0x2 << 12, "scpu_ejtag"),
-		RTK_PIN_FUNC(0x3 << 12, "ao")),
+		RTK_PIN_FUNC(0x2 << 12, "scpu_ejtag_gpio"),
+		RTK_PIN_FUNC(0x3 << 12, "ao_gpio")),
 	RTK_PIN_MUX(gpio_5, 0x70, GENMASK(15, 14),
 		RTK_PIN_FUNC(0x1 << 14, "gpio"),
-		RTK_PIN_FUNC(0x2 << 14, "scpu_ejtag"),
-		RTK_PIN_FUNC(0x3 << 14, "ao")),
+		RTK_PIN_FUNC(0x2 << 14, "scpu_ejtag_gpio"),
+		RTK_PIN_FUNC(0x3 << 14, "ao_gpio")),
 	RTK_PIN_MUX(gpio_6, 0x70, GENMASK(17, 16),
 		RTK_PIN_FUNC(0x1 << 16, "gpio"),
-		RTK_PIN_FUNC(0x2 << 16, "scpu_ejtag"),
-		RTK_PIN_FUNC(0x3 << 16, "ao")),
+		RTK_PIN_FUNC(0x2 << 16, "scpu_ejtag_gpio"),
+		RTK_PIN_FUNC(0x3 << 16, "ao_gpio")),
 	RTK_PIN_MUX(gpio_7, 0x70, GENMASK(19, 18),
 		RTK_PIN_FUNC(0x1 << 18, "gpio"),
-		RTK_PIN_FUNC(0x2 << 18, "scpu_ejtag"),
-		RTK_PIN_FUNC(0x3 << 18, "ao")),
+		RTK_PIN_FUNC(0x2 << 18, "scpu_ejtag_gpio"),
+		RTK_PIN_FUNC(0x3 << 18, "ao_gpio")),
 	RTK_PIN_MUX(gpio_8, 0x70, GENMASK(21, 20),
 		RTK_PIN_FUNC(0x1 << 20, "gpio"),
-		RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag")),
+		RTK_PIN_FUNC(0x2 << 20, "scpu_ejtag_gpio")),
+	RTK_PIN_MUX(ao_loc, 0x74, GENMASK(3, 2),
+		RTK_PIN_FUNC(0x1 << 2, "ao_tp0"),
+		RTK_PIN_FUNC(0x2 << 2, "ao_gpio")),
+};
 
-	/* sf_en */
-	/* ao_loc */
+static const struct rtd119x_pin_config_desc rtd1195_crt_configs[] = {
+	RTK_PIN_CONFIG(nf_ale, 0x78, 4, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_ce_n_0, 0x78, 8, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_ce_n_1, 0x78, 12, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_rdy, 0x78, 16, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_rd_n, 0x78, 20, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_wr_n, 0x78, 24, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_cle, 0x78, 28, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_dd_0, 0x7c, 0, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_dd_1, 0x7c, 4, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_dd_2, 0x7c, 8, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_dd_3, 0x7c, 12, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_dd_4, 0x7c, 16, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_dd_5, 0x7c, 20, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_dd_6, 0x7c, 24, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(nf_dd_7, 0x7c, 28, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(mmc_cmd, 0x80, 0, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(mmc_clk, 0x80, 4, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(mmc_wp, 0x80, 8, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(mmc_cd, 0x80, 12, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(mmc_data_0, 0x80, 16, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(mmc_data_1, 0x80, 20, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(mmc_data_2, 0x80, 24, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(mmc_data_3, 0x80, 28, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(sdio_cmd, 0x84, 0, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(sdio_clk, 0x84, 4, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(sdio_wp, 0x84, 8, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(sdio_cd, 0x84, 12, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(sdio_data_0, 0x84, 16, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(sdio_data_1, 0x84, 20, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(sdio_data_2, 0x84, 24, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(sdio_data_3, 0x84, 28, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(spdif, 0x88, 0, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(tp0_clk, 0x8c, 0, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(tp0_sync, 0x8c, 4, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(tp0_valid, 0x8c, 8, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(tp0_data, 0x8c, 12, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(tp1_clk, 0x90, 0, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(tp1_sync, 0x90, 4, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(tp1_valid, 0x90, 8, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(tp1_data, 0x90, 12, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(i2c_sda_1, 0x94, 0, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(i2c_scl_1, 0x94, 4, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(i2c_sda_4, 0x94, 8, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(i2c_scl_4, 0x94, 12, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(i2c_sda_5, 0x94, 16, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(i2c_scl_5, 0x94, 20, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(gpio_0, 0x98, 0, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(gpio_1, 0x98, 4, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(gpio_2, 0x98, 8, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(gpio_3, 0x98, 12, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(gpio_4, 0x98, 16, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(gpio_5, 0x98, 20, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(gpio_6, 0x98, 24, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(gpio_7, 0x98, 28, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(gpio_8, 0x9c, 0, 1, 0, 2, 3, PADDRI_4_8),
+	RTK_PIN_CONFIG(hdmi_hpd, 0x9c, 4, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(usb_id, 0x9c, 8, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(sensor_stb_0, 0x9c, 12, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(sensor_stb_1, 0x9c, 16, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(sensor_rst, 0x9c, 20, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(sensor_cko_0, 0x9c, 24, 1, 0, 2, 3, PADDRI_2_4),
+	RTK_PIN_CONFIG(sensor_cko_1, 0x9c, 28, 1, 0, 2, 3, PADDRI_2_4),
 };
 
+
 static const struct rtd119x_pinctrl_desc rtd1195_crt_pinctrl_desc = {
 	.pins = rtd1195_crt_pins,
 	.num_pins = ARRAY_SIZE(rtd1195_crt_pins),

@@ -879,6 +1061,8 @@ static const struct rtd119x_pinctrl_desc rtd1195_crt_pinctrl_desc = {
 	.num_functions = ARRAY_SIZE(rtd1195_crt_pin_functions),
 	.muxes = rtd1195_crt_muxes,
 	.num_muxes = ARRAY_SIZE(rtd1195_crt_muxes),
+	.configs = rtd1195_crt_configs,
+	.num_configs = ARRAY_SIZE(rtd1195_crt_configs),
 };
 
 #endif

index 9f3471d02221..f0dd91f416e8 100644
@@ -1,3 +1,11 @@
+/* SPDX-License-Identifier: GPL-2.0-or-later OR BSD-2-Clause */
+
+/*
+ * Realtek RTD1195 pin controller driver
+ *
+ * Copyright (c) 2019 Realtek Semiconductor Corp.
+ */
+
 #ifndef PINCTRL_RTD1195_H
 #define PINCTRL_RTD1195_H
 

@@ -76,15 +84,20 @@ static const unsigned int rtd1195_ur1_cts_n_pins[] = { RTD1195_ISO_UR1_CTS_N };
 static const unsigned int rtd1195_ur1_rts_n_pins[] = { RTD1195_ISO_UR1_RTS_N };
 static const unsigned int rtd1195_i2c_scl_0_pins[] = { RTD1195_ISO_I2C_SCL_0 };
 static const unsigned int rtd1195_i2c_sda_0_pins[] = { RTD1195_ISO_I2C_SDA_0 };
-static const unsigned int rtd1195_etn_led_link_pins[] = { RTD1195_ISO_ETN_LED_LINK };
-static const unsigned int rtd1195_etn_led_rxtx_pins[] = { RTD1195_ISO_ETN_LED_RXTX };
+static const unsigned int rtd1195_etn_led_link_pins[] = {
+				RTD1195_ISO_ETN_LED_LINK };
+static const unsigned int rtd1195_etn_led_rxtx_pins[] = {
+				RTD1195_ISO_ETN_LED_RXTX };
 static const unsigned int rtd1195_i2c_scl_6_pins[] = { RTD1195_ISO_I2C_SCL_6 };
 static const unsigned int rtd1195_i2c_sda_6_pins[] = { RTD1195_ISO_I2C_SDA_6 };
 static const unsigned int rtd1195_ai_loc_pins[] = { RTD1195_ISO_AI_LOC };
-static const unsigned int rtd1195_ejtag_avcpu_loc_pins[] = { RTD1195_ISO_EJTAG_AVCPU_LOC };
+static const unsigned int rtd1195_ejtag_avcpu_loc_pins[] = {
+				RTD1195_ISO_EJTAG_AVCPU_LOC };
 static const unsigned int rtd1195_ur1_loc_pins[] = { RTD1195_ISO_UR1_LOC };
-static const unsigned int rtd1195_pwm_01_open_drain_pins[] = { RTD1195_ISO_PWM_01_OPEN_DRAIN };
-static const unsigned int rtd1195_pwm_23_open_drain_pins[] = { RTD1195_ISO_PWM_23_OPEN_DRAIN };
+static const unsigned int rtd1195_pwm_01_open_drain_pins[] = {
+				RTD1195_ISO_PWM_01_OPEN_DRAIN };
+static const unsigned int rtd1195_pwm_23_open_drain_pins[] = {
+				RTD1195_ISO_PWM_23_OPEN_DRAIN };
 
 
 #define RTD1195_GROUP(_name) \

@@ -148,26 +161,46 @@ static const char * const rtd1195_iso_avcpu_ejtag_misc_loc_groups[] = {
 	"ejtag_avcpu_loc"
 };
 
-
-static const char * const rtd1195_iso_etn_led_groups[] = { "etn_led_link", "etn_led_rxtx" };
-static const char * const rtd1195_iso_i2c0_groups[] = { "i2c_scl_0", "i2c_sda_0" };
+static const char * const rtd1195_iso_etn_led_groups[] = {
+	"etn_led_link", "etn_led_rxtx"
+};
+static const char * const rtd1195_iso_i2c0_groups[] = {
+	"i2c_scl_0", "i2c_sda_0"
+};
 static const char * const rtd1195_iso_i2c2_groups[] = { "vfd_d" };
 static const char * const rtd1195_iso_i2c3_groups[] = { "ir_tx" };
-static const char * const rtd1195_iso_i2c6_groups[] = { "i2c_scl_6", "i2c_sda_6" };
+static const char * const rtd1195_iso_i2c6_groups[] = {
+	"i2c_scl_6", "i2c_sda_6"
+};
 static const char * const rtd1195_iso_ir_rx_groups[] = { "ir_rx" };
 static const char * const rtd1195_iso_ir_tx_groups[] = { "ir_tx" };
 static const char * const rtd1195_iso_pwm_groups[] = {
 	"ur0_rx", "ur0_tx", "ur1_rx", "ur1_tx", "etn_led_link", "etn_led_rxtx"
 };
-static const char * const rtd1195_iso_standby_dbg_groups[] = { "ir_rx", "usb0", "usb1" };
+static const char * const rtd1195_iso_standby_dbg_groups[] = {
+	"ir_rx", "usb0", "usb1"
+};
 static const char * const rtd1195_iso_uart0_groups[] = { "ur0_rx", "ur0_tx" };
-static const char * const rtd1195_iso_uart1_groups[] = { "ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ur1_loc" };
+static const char * const rtd1195_iso_uart1_groups[] = {
+	"ur1_rx", "ur1_tx", "ur1_cts_n", "ur1_rts_n", "ur1_loc"
+};
 static const char * const rtd1195_iso_ur1_misc_groups[] = { "ur1_loc" };
-static const char * const rtd1195_iso_vfd_groups[] = { "vfd_cs_n", "vfd_clk", "vfd_d" };
-static const char * const rtd1195_iso_pwm_01_normal_groups[] = { "pwm_01_open_drain" };
-static const char * const rtd1195_iso_pwm_23_normal_groups[] = { "pwm_23_open_drain" };
-static const char * const rtd1195_iso_pwm_01_open_drain_groups[] = { "pwm_01_open_drain" };
-static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = { "pwm_23_open_drain" };
+static const char * const rtd1195_iso_vfd_groups[] = {
+	"vfd_cs_n", "vfd_clk", "vfd_d"
+};
+static const char * const rtd1195_iso_pwm_01_normal_groups[] = {
+	"pwm_01_open_drain"
+};
+static const char * const rtd1195_iso_pwm_23_normal_groups[] = {
+	"pwm_23_open_drain"
+};
+static const char * const rtd1195_iso_pwm_01_open_drain_groups[] = {
+	"pwm_01_open_drain"
+};
+static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = {
+	"pwm_23_open_drain"
+
+};
 
 
 

@@ -527,12 +560,17 @@ static const unsigned int rtd1195_i2c_scl_1_pins[] = { RTD1195_I2C_SCL_1 };
 static const unsigned int rtd1195_i2c_sda_1_pins[] = { RTD1195_I2C_SDA_1 };
 static const unsigned int rtd1195_i2c_scl_4_pins[] = { RTD1195_I2C_SCL_4 };
 static const unsigned int rtd1195_i2c_sda_4_pins[] = { RTD1195_I2C_SDA_4 };
-static const unsigned int rtd1195_sensor_cko_0_pins[] = { RTD1195_SENSOR_CKO_0 };
-static const unsigned int rtd1195_sensor_cko_1_pins[] = { RTD1195_SENSOR_CKO_1 };
+static const unsigned int rtd1195_sensor_cko_0_pins[] = {
+					RTD1195_SENSOR_CKO_0 };
+static const unsigned int rtd1195_sensor_cko_1_pins[] = {
+					RTD1195_SENSOR_CKO_1 };
 static const unsigned int rtd1195_sensor_rst_pins[] = { RTD1195_SENSOR_RST };
-static const unsigned int rtd1195_sensor_stb_0_pins[] = { RTD1195_SENSOR_STB_0 };
-static const unsigned int rtd1195_sensor_stb_1_pins[] = { RTD1195_SENSOR_STB_1 };
-static const unsigned int rtd1195_ejtag_scpu_loc_pins[] = { RTD1195_EJTAG_SCPU_LOC };
+static const unsigned int rtd1195_sensor_stb_0_pins[] = {
+					RTD1195_SENSOR_STB_0 };
+static const unsigned int rtd1195_sensor_stb_1_pins[] = {
+					RTD1195_SENSOR_STB_1 };
+static const unsigned int rtd1195_ejtag_scpu_loc_pins[] = {
+					RTD1195_EJTAG_SCPU_LOC };
 static const unsigned int rtd1195_hif_loc_pins[] = { RTD1195_HI_LOC };
 static const unsigned int rtd1195_ao_loc_pins[] = { RTD1195_AO_LOC };
 

@@ -617,11 +655,14 @@ static const struct rtd119x_pin_group_desc rtd1195_crt_pin_groups[] = {
 static const char * const rtd1195_crt_gpio_groups[] = {
 	"gpio_0", "gpio_1", "gpio_2", "gpio_3",
 	"gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8",
-	"nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
-	"nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1",
+	"nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3",
+	"nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
+	"nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale",
+	"nf_cle", "nf_ce_n_0", "nf_ce_n_1",
 	"mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3",
 	"mmc_clk", "mmc_cmd", "mmc_wp", "mmc_cd",
-	"sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "sdio_cmd",
+	"sdio_clk", "sdio_data_0", "sdio_data_1",
+	"sdio_data_2", "sdio_data_3", "sdio_cmd",
 	"i2c_scl_5", "i2c_sda_5",
 	"tp1_data", "tp1_clk", "tp1_valid", "tp1_sync",
 	"tp0_data", "tp0_clk", "tp0_valid", "tp0_sync",

@@ -649,7 +690,8 @@ static const char * const rtd1195_crt_avcpu_ejtag_misc_groups[] = {
 };
 static const char * const rtd1195_crt_cpu_loop_groups[] = { "usb_id" };
 static const char * const rtd1195_crt_emmc_groups[] = {
-	"nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
+	"nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3",
+	"nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
 	"nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle",
 };
 static const char * const rtd1195_crt_gspi_groups[] = {

@@ -664,30 +706,45 @@ static const char * const rtd1195_crt_hif_misc_groups[] = {
 };
 
 
-static const char * const rtd1195_crt_i2c1_groups[] = { "i2c_scl_1", "i2c_sda_1" };
-static const char * const rtd1195_crt_i2c2_groups[] = { "tp1_sync", "tp1_clk" };
-static const char * const rtd1195_crt_i2c3_groups[] = { "tp1_data", "tp1_valid" };
-static const char * const rtd1195_crt_i2c4_groups[] = { "i2c_scl_4", "i2c_sda_4" };
-static const char * const rtd1195_crt_i2c5_groups[] = { "i2c_scl_5", "i2c_sda_5" };
+static const char * const rtd1195_crt_i2c1_groups[] = {
+	"i2c_scl_1", "i2c_sda_1"
+};
+static const char * const rtd1195_crt_i2c2_groups[] = {
+	"tp1_sync", "tp1_clk"
+};
+static const char * const rtd1195_crt_i2c3_groups[] = {
+	"tp1_data", "tp1_valid" };
+static const char * const rtd1195_crt_i2c4_groups[] = {
+	"i2c_scl_4", "i2c_sda_4"
+};
+static const char * const rtd1195_crt_i2c5_groups[] = {
+	"i2c_scl_5", "i2c_sda_5"
+};
 static const char * const rtd1195_crt_mmc_groups[] = {
 	"mmc_data_0", "mmc_data_1", "mmc_data_2", "mmc_data_3",
 	"mmc_clk", "mmc_cmd", "mmc_wp", "mmc_cd",
 };
 static const char * const rtd1195_crt_nand_groups[] = {
-	"nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3", "nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
-	"nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale", "nf_cle", "nf_ce_n_0", "nf_ce_n_1",
+	"nf_dd_0", "nf_dd_1", "nf_dd_2", "nf_dd_3",
+	"nf_dd_4", "nf_dd_5", "nf_dd_6", "nf_dd_7",
+	"nf_rdy", "nf_rd_n", "nf_wr_n", "nf_ale",
+	"nf_cle", "nf_ce_n_0", "nf_ce_n_1",
 };
 static const char * const rtd1195_crt_scpu_ejtag_gpio_groups[] = {
 	"gpio_4", "gpio_5", "gpio_6", "gpio_7", "gpio_8", "ejtag_scpu_loc"
 };
 static const char * const rtd1195_crt_scpu_ejtag_cr_groups[] = {
-	"mmc_data_0", "mmc_data_3", "mmc_clk", "mmc_cmd", "mmc_wp", "ejtag_scpu_loc"
+	"mmc_data_0", "mmc_data_3", "mmc_clk",
+	"mmc_cmd", "mmc_wp", "ejtag_scpu_loc"
 };
 
 static const char * const rtd1195_crt_sdio_groups[] = {
-	"sdio_clk", "sdio_data_0", "sdio_data_1", "sdio_data_2", "sdio_data_3", "sdio_cmd",
+	"sdio_clk", "sdio_data_0", "sdio_data_1",
+	"sdio_data_2", "sdio_data_3", "sdio_cmd",
+};
+static const char * const rtd1195_crt_sensor_groups[] = {
+	"sensor_cko_0", "sensor_cko_1"
 };
-static const char * const rtd1195_crt_sensor_groups[] = { "sensor_cko_0", "sensor_cko_1" };
 static const char * const rtd1195_crt_spdif_groups[] = { "spdif" };
 static const char * const rtd1195_crt_tp0_groups[] = {
 	"tp0_data", "tp0_clk", "tp0_valid", "tp0_sync",

@@ -695,7 +752,9 @@ static const char * const rtd1195_crt_tp0_groups[] = {
 static const char * const rtd1195_crt_tp1_groups[] = {
 	"tp1_data", "tp1_clk", "tp1_valid", "tp1_sync",
 };
-static const char * const rtd1195_crt_uart1_groups[] = { "gpio_0", "gpio_1", "gpio_2", "gpio_3" };
+static const char * const rtd1195_crt_uart1_groups[] = {
+	"gpio_0", "gpio_1", "gpio_2", "gpio_3"
+};
 static const char * const rtd1195_crt_usb_groups[] = { "sensor_cko_1" };
 
 #define RTD1195_FUNC(_name) \

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similarity index 98%
rename from drivers/pinctrl/pinctrl-rtd1195.h
rename to drivers/pinctrl/realtek/pinctrl-rtd1195.h
index f0dd91f416e8..74139345083c 100644
@@ -107,7 +107,7 @@ static const unsigned int rtd1195_pwm_23_open_drain_pins[] = {
 		.num_pins = ARRAY_SIZE(rtd1195_ ## _name ## _pins), \
 	}
 
-static const struct rtd119x_pin_group_desc rtd1195_iso_pin_groups[] = {
+static const struct rtd_pin_group_desc rtd1195_iso_pin_groups[] = {
 	RTD1195_GROUP(iso_gpio_0),
 	RTD1195_GROUP(iso_gpio_1),
 	RTD1195_GROUP(usb0),

@@ -212,7 +212,7 @@ static const char * const rtd1195_iso_pwm_23_open_drain_groups[] = {
 		.num_groups = ARRAY_SIZE(rtd1195_iso_ ## _name ## _groups), \
 	}
 
-static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = {
+static const struct rtd_pin_func_desc rtd1195_iso_pin_functions[] = {
 	RTD1195_FUNC(gpio),
 	RTD1195_FUNC(ai_ur1),
 	RTD1195_FUNC(ai_vfd),

@@ -239,7 +239,7 @@ static const struct rtd119x_pin_func_desc rtd1195_iso_pin_functions[] = {
 
 #undef RTD1195_FUNC
 
-static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = {
+static const struct rtd_pin_desc rtd1195_iso_muxes[] = {
 	RTK_PIN_MUX(vfd_d, 0x10, GENMASK(1, 0),
 		RTK_PIN_FUNC(0x0 << 0, "gpio"),
 		RTK_PIN_FUNC(0x1 << 0, "vfd"),

@@ -337,7 +337,7 @@ static const struct rtd119x_pin_desc rtd1195_iso_muxes[] = {
 		RTK_PIN_FUNC(0x2 << 30, "ai_vfd")),
 };
 
-static const struct rtd119x_pin_config_desc rtd1195_iso_configs[] = {
+static const struct rtd_pin_config_desc rtd1195_iso_configs[] = {
 	RTK_PIN_CONFIG(ir_rx, 0x0, 8, 1, 0, 2, 3, PADDRI_2_4),
 	RTK_PIN_CONFIG(vfd_cs_n, 0x0, 12, 1, 0, 2, 3, PADDRI_2_4),
 	RTK_PIN_CONFIG(vfd_clk, 0x0, 16, 1, 0, 2, 3, PADDRI_2_4),

@@ -358,7 +358,7 @@ static const struct rtd119x_pin_config_desc rtd1195_iso_configs[] = {
 };
 
 
-static const struct rtd119x_pinctrl_desc rtd1195_iso_pinctrl_desc = {
+static const struct rtd_pinctrl_desc rtd1195_iso_pinctrl_desc = {
 	.pins = rtd1195_iso_pins,
 	.num_pins = ARRAY_SIZE(rtd1195_iso_pins),
 	.groups = rtd1195_iso_pin_groups,

@@ -586,7 +586,7 @@ static const unsigned int rtd1195_ao_loc_pins[] = { RTD1195_AO_LOC };
 		.num_pins = ARRAY_SIZE(rtd1195_ ## _name ## _pins), \
 	}
 
-static const struct rtd119x_pin_group_desc rtd1195_crt_pin_groups[] = {
+static const struct rtd_pin_group_desc rtd1195_crt_pin_groups[] = {
 	RTD1195_GROUP(gpio_0),
 	RTD1195_GROUP(gpio_1),
 	RTD1195_GROUP(gpio_2),

@@ -764,7 +764,7 @@ static const char * const rtd1195_crt_usb_groups[] = { "sensor_cko_1" };
 		.num_groups = ARRAY_SIZE(rtd1195_crt_ ## _name ## _groups), \
 	}
 
-static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = {
+static const struct rtd_pin_func_desc rtd1195_crt_pin_functions[] = {
 	RTD1195_FUNC(gpio),
 	RTD1195_FUNC(ao_tp0),
 	RTD1195_FUNC(ao_gpio),

@@ -794,7 +794,7 @@ static const struct rtd119x_pin_func_desc rtd1195_crt_pin_functions[] = {
 
 #undef RTD1195_FUNC
 
-static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
+static const struct rtd_pin_desc rtd1195_crt_muxes[] = {
 	RTK_PIN_MUX(nf_rdy, 0x60, GENMASK(3, 2),
 		RTK_PIN_FUNC(0x0 << 2, "gpio"),
 		RTK_PIN_FUNC(0x1 << 2, "nand"),

@@ -1045,7 +1045,7 @@ static const struct rtd119x_pin_desc rtd1195_crt_muxes[] = {
 		RTK_PIN_FUNC(0x2 << 2, "ao_gpio")),
 };
 
-static const struct rtd119x_pin_config_desc rtd1195_crt_configs[] = {
+static const struct rtd_pin_config_desc rtd1195_crt_configs[] = {
 	RTK_PIN_CONFIG(nf_ale, 0x78, 4, 1, 0, 2, 3, PADDRI_4_8),
 	RTK_PIN_CONFIG(nf_ce_n_0, 0x78, 8, 1, 0, 2, 3, PADDRI_4_8),
 	RTK_PIN_CONFIG(nf_ce_n_1, 0x78, 12, 1, 0, 2, 3, PADDRI_4_8),

@@ -1111,7 +1111,7 @@ static const struct rtd119x_pin_config_desc rtd1195_crt_configs[] = {
 };
 
 
-static const struct rtd119x_pinctrl_desc rtd1195_crt_pinctrl_desc = {
+static const struct rtd_pinctrl_desc rtd1195_crt_pinctrl_desc = {
 	.pins = rtd1195_crt_pins,
 	.num_pins = ARRAY_SIZE(rtd1195_crt_pins),
 	.groups = rtd1195_crt_pin_groups,

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index 5dc4fac9c8bb..2fc2d4d46928 100644
@@ -77,6 +77,12 @@ struct rtd_pin_desc {
 		}
 
 
+struct rtd_pin_reg_list {
+	unsigned int reg_offset;
+	unsigned int val;
+};
+
+
 #define RTK_PIN_CONFIG(_name, _reg_off, _base_bit, _pud_en_off, \
 		_pud_sel_off, _curr_off, _smt_off, _curr_type) \
 	{ \

@@ -120,6 +126,8 @@ struct rtd_pinctrl_desc {
 	unsigned int num_configs;
 	const struct rtd_pin_sconfig_desc *sconfigs;
 	unsigned int num_sconfigs;
+	struct rtd_pin_reg_list *lists;
+	unsigned int num_regs;
 };
 
 #define PCONF_UNSUPP 0xffffffff

@@ -643,8 +651,39 @@ static int rtd_pinctrl_probe(struct platform_device *pdev)
 	return 0;
 }
 
+static int rtd_pinctrl_suspend(struct platform_device *pdev, pm_message_t state)
+{
+	struct rtd_pinctrl *data = platform_get_drvdata(pdev);
+	struct rtd_pin_reg_list *list;
+	int i;
+
+	for (i = 0; i < data->info->num_regs; i++) {
+		list = &data->info->lists[i];
+		list->val = readl(data->base + list->reg_offset);
+	}
+
+	return 0;
+}
+
+static int rtd_pinctrl_resume(struct platform_device *pdev)
+{
+	struct rtd_pinctrl *data = platform_get_drvdata(pdev);
+	const struct rtd_pin_reg_list *list;
+	int i;
+
+	for (i = 0; i < data->info->num_regs; i++) {
+		list = &data->info->lists[i];
+		writel(list->val, data->base + list->reg_offset);
+	}
+
+	return 0;
+}
+
+
 static struct platform_driver rtd_pinctrl_driver = {
 	.probe = rtd_pinctrl_probe,
+	.suspend = rtd_pinctrl_suspend,
+	.resume = rtd_pinctrl_resume,
 	.driver = {
 		.name = "rtd-pinctrl",
 		.of_match_table	= rtd_pinctrl_dt_ids,

index 74139345083c..c9d6e7894d66 100644
@@ -358,6 +358,16 @@ static const struct rtd_pin_config_desc rtd1195_iso_configs[] = {
 };
 
 
+static struct rtd_pin_reg_list rtd1195_iso_reg_lists[] = {
+	{.reg_offset = 0x0},
+	{.reg_offset = 0x4},
+	{.reg_offset = 0x8},
+	{.reg_offset = 0xc},
+	{.reg_offset = 0x10},
+	{.reg_offset = 0x14},
+};
+
+
 static const struct rtd_pinctrl_desc rtd1195_iso_pinctrl_desc = {
 	.pins = rtd1195_iso_pins,
 	.num_pins = ARRAY_SIZE(rtd1195_iso_pins),

@@ -369,6 +379,8 @@ static const struct rtd_pinctrl_desc rtd1195_iso_pinctrl_desc = {
 	.num_muxes = ARRAY_SIZE(rtd1195_iso_muxes),
 	.configs = rtd1195_iso_configs,
 	.num_configs = ARRAY_SIZE(rtd1195_iso_configs),
+	.lists = rtd1195_iso_reg_lists,
+	.num_regs = ARRAY_SIZE(rtd1195_iso_reg_lists),
 };
 
 /* CRT */

@@ -1110,6 +1122,25 @@ static const struct rtd_pin_config_desc rtd1195_crt_configs[] = {
 	RTK_PIN_CONFIG(sensor_cko_1, 0x9c, 28, 1, 0, 2, 3, PADDRI_2_4),
 };
 
+static struct rtd_pin_reg_list rtd1195_crt_reg_lists[] = {
+	{.reg_offset = 0x60},
+	{.reg_offset = 0x64},
+	{.reg_offset = 0x68},
+	{.reg_offset = 0x6c},
+	{.reg_offset = 0x70},
+	{.reg_offset = 0x74},
+	{.reg_offset = 0x78},
+	{.reg_offset = 0x7c},
+	{.reg_offset = 0x80},
+	{.reg_offset = 0x84},
+	{.reg_offset = 0x88},
+	{.reg_offset = 0x8c},
+	{.reg_offset = 0x90},
+	{.reg_offset = 0x94},
+	{.reg_offset = 0x98},
+	{.reg_offset = 0x9c},
+};
+
 
 static const struct rtd_pinctrl_desc rtd1195_crt_pinctrl_desc = {
 	.pins = rtd1195_crt_pins,

@@ -1122,6 +1153,8 @@ static const struct rtd_pinctrl_desc rtd1195_crt_pinctrl_desc = {
 	.num_muxes = ARRAY_SIZE(rtd1195_crt_muxes),
 	.configs = rtd1195_crt_configs,
 	.num_configs = ARRAY_SIZE(rtd1195_crt_configs),
+	.lists = rtd1195_crt_reg_lists,
+	.num_regs = ARRAY_SIZE(rtd1195_crt_reg_lists),
 };
 
 #endif

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