qom: Automated conversion of type checking boilerplate

The PL1110 enum value name will conflict with the PL1110 type cast checker, when we replace the existing macro with an inline function. Rename it to PL1110_STOCK.

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/display/pl110.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

hw/display/pl110.c +0 -0

index c2991a28d2..4664fde3f2 100644

hw/display/pl110.c +5 -5

 };

@@ -372,12 +372,12 @@ static uint64_t pl110_read(void *opaque, hwaddr offset,
     case 5: /* LCDLPBASE */
         return s->lpbase;
     case 6: /* LCDIMSC */
-        if (s->version != PL110) {
+        if (s->version != PL110_STOCK) {
             return s->cr;
         }
         return s->int_mask;
     case 7: /* LCDControl */
-        if (s->version != PL110) {
+        if (s->version != PL110_STOCK) {
             return s->int_mask;
         }
         return s->cr;

@@ -437,7 +437,7 @@ static void pl110_write(void *opaque, hwaddr offset,
         s->lpbase = val;
         break;
     case 6: /* LCDIMSC */
-        if (s->version != PL110) {
+        if (s->version != PL110_STOCK) {
             goto control;
         }
     imsc:

@@ -445,7 +445,7 @@ static void pl110_write(void *opaque, hwaddr offset,
         pl110_update(s);
         break;
     case 7: /* LCDControl */
-        if (s->version != PL110) {
+        if (s->version != PL110_STOCK) {
             goto imsc;
         }
     control:

@@ -513,7 +513,7 @@ static void pl110_init(Object *obj)
 {
     PL110State *s = PL110(obj);
 
-    s->version = PL110;
+    s->version = PL110_STOCK;
 }
 
 static void pl110_versatile_init(Object *obj)

Quoted 3 lines · Eduardo Habkost

The PL1110 enum value name will conflict with the PL1110 type cast checker, when we replace the existing macro with an inline function. Rename it to PL1110_STOCK.

typo s/PL1110/PL110/ in subject and description.

Quoted 12 lines

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/display/pl110.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

hw/display/pl110.c +0 -0

index c2991a28d2..4664fde3f2 100644

hw/display/pl110.c enum pl110_bppmode · line 47

Quoted 7 lines

hw/display/pl110.c +1 -1

@@ -42,7 +42,7 @@ enum pl110_bppmode
 /* The Versatile/PB uses a slightly modified PL110 controller.  */
 enum pl110_version
 {
-    PL110,
+    PL110_STOCK,
     PL110_VERSATILE,
     PL111

For completeness I'd also rename PL111.

What about:

enum pl110_version

 {
    PL110_VERSION,
    PL110_VERSATILE_VERSION,
    PL111_VERSION

}

?

CCing maintainer (pmaydell).

Quoted 6 lines · Philippe Mathieu-Daudé

Quoted 3 lines · Eduardo Habkost

The PL1110 enum value name will conflict with the PL1110 type cast checker, when we replace the existing macro with an inline function. Rename it to PL1110_STOCK.

typo s/PL1110/PL110/ in subject and description.

Thanks for spotting that! Will be fixed in v2.

Quoted 24 lines

Quoted 12 lines

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/display/pl110.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

hw/display/pl110.c +0 -0

index c2991a28d2..4664fde3f2 100644

hw/display/pl110.c enum pl110_bppmode · line 47

Quoted 7 lines

hw/display/pl110.c +1 -1

@@ -42,7 +42,7 @@ enum pl110_bppmode
 /* The Versatile/PB uses a slightly modified PL110 controller.  */
 enum pl110_version
 {
-    PL110,
+    PL110_STOCK,
     PL110_VERSATILE,
     PL111

For completeness I'd also rename PL111.

What about:

Quoted 8 lines

enum pl110_version

 {
    PL110_VERSION,
    PL110_VERSATILE_VERSION,
    PL111_VERSION

}

?

That would work too, although I'm more used to enum values to have a common prefix instead of a common suffix.

Any objections to:

  enum pl110_version
  {
      VERSION_PL110,
      VERSION_PL110_VERSATILE,
      VERSION_PL111
  }

?

--
Eduardo

Rename the E1000_DEVICE_CLASS() and E1000_DEVICE_GET_CLASS() macros to be consistent with the E1000() instance cast macro.

This will allow us to register the type cast macros using OBJECT_DECLARE_TYPE later.

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/net/e1000.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Rename the MEGASAS_DEVICE_CLASS() and MEGASAS_DEVICE_GET_CLASS() macros to be consistent with the MEGASAS() instance cast macro.

This will allow us to register the type cast macros using OBJECT_DECLARE_TYPE later.

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/scsi/megasas.c | 12 ++++++------
 1 file changed, 6 insertions(+), 6 deletions(-)

Rename the PVSCSI_DEVICE_CLASS() and PVSCSI_DEVICE_GET_CLASS() macros to be consistent with the PVSCSI() instance cast macro.

This will allow us to register the type cast macros using OBJECT_DECLARE_TYPE later.

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/scsi/vmw_pvscsi.c | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

The macro definition had an extra semicolon. This was never noticed because the macro was only being used where it didn't make a difference.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/timer/aspeed_timer.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

include/hw/timer/aspeed_timer.h +0 -0

index 948329893c..d7c7d8ad28 100644

The macro definition had an extra semicolon. This was never noticed because the macro was only being used where it didn't make a difference.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/timer/aspeed_timer.h | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Some of the enum constant names conflict with the QOM type check macros. This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE().

Rename all the constants to AW_H3_DEV_*, to avoid conflicts.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/arm/allwinner-h3.h |  62 ++++++++---------
 hw/arm/allwinner-h3.c         | 124 +++++++++++++++++-----------------
 hw/arm/orangepi.c             |   6 +-
 3 files changed, 96 insertions(+), 96 deletions(-)

include/hw/arm/allwinner-h3.h +0 -25

index 82e4e59216..626139dcb3 100644
@@ -61,37 +61,37 @@
  * @see AwH3State
  */
 enum {
-    AW_H3_SRAM_A1,
-    AW_H3_SRAM_A2,
-    AW_H3_SRAM_C,
-    AW_H3_SYSCTRL,
-    AW_H3_MMC0,
-    AW_H3_SID,
-    AW_H3_EHCI0,
-    AW_H3_OHCI0,
-    AW_H3_EHCI1,
-    AW_H3_OHCI1,
-    AW_H3_EHCI2,
-    AW_H3_OHCI2,
-    AW_H3_EHCI3,
-    AW_H3_OHCI3,
-    AW_H3_CCU,
-    AW_H3_PIT,
-    AW_H3_UART0,
-    AW_H3_UART1,
-    AW_H3_UART2,
-    AW_H3_UART3,
-    AW_H3_EMAC,
-    AW_H3_DRAMCOM,
-    AW_H3_DRAMCTL,
-    AW_H3_DRAMPHY,
-    AW_H3_GIC_DIST,

include/hw/arm/allwinner-h3.h +27 -0

+    AW_H3_DEV_MMC0,
+    AW_H3_DEV_SID,
+    AW_H3_DEV_EHCI0,
+    AW_H3_DEV_OHCI0,
+    AW_H3_DEV_EHCI1,
+    AW_H3_DEV_OHCI1,
+    AW_H3_DEV_EHCI2,
+    AW_H3_DEV_OHCI2,
+    AW_H3_DEV_EHCI3,
+    AW_H3_DEV_OHCI3,
+    AW_H3_DEV_CCU,
+    AW_H3_DEV_PIT,
+    AW_H3_DEV_UART0,
+    AW_H3_DEV_UART1,
+    AW_H3_DEV_UART2,
+    AW_H3_DEV_UART3,
+    AW_H3_DEV_EMAC,
+    AW_H3_DEV_DRAMCOM,
+    AW_H3_DEV_DRAMCTL,
+    AW_H3_DEV_DRAMPHY,
+    AW_H3_DEV_GIC_DIST,
+    AW_H3_DEV_GIC_CPU,
+    AW_H3_DEV_GIC_HYP,
+    AW_H3_DEV_GIC_VCPU,
+    AW_H3_DEV_RTC,
+    AW_H3_DEV_CPUCFG,
+    AW_H3_DEV_SDRAM
 };
 
 /** Total number of CPU cores in the H3 SoC */

hw/arm/allwinner-h3.c +62 -62

index ff92ded82c..341abe6718 100644
@@ -35,37 +35,37 @@
 
 /* Memory map */
 const hwaddr allwinner_h3_memmap[] = {
-    [AW_H3_SRAM_A1]    = 0x00000000,
-    [AW_H3_SRAM_A2]    = 0x00044000,
-    [AW_H3_SRAM_C]     = 0x00010000,
-    [AW_H3_SYSCTRL]    = 0x01c00000,
-    [AW_H3_MMC0]       = 0x01c0f000,
-    [AW_H3_SID]        = 0x01c14000,
-    [AW_H3_EHCI0]      = 0x01c1a000,
-    [AW_H3_OHCI0]      = 0x01c1a400,
-    [AW_H3_EHCI1]      = 0x01c1b000,
-    [AW_H3_OHCI1]      = 0x01c1b400,
-    [AW_H3_EHCI2]      = 0x01c1c000,
-    [AW_H3_OHCI2]      = 0x01c1c400,
-    [AW_H3_EHCI3]      = 0x01c1d000,
-    [AW_H3_OHCI3]      = 0x01c1d400,
-    [AW_H3_CCU]        = 0x01c20000,
-    [AW_H3_PIT]        = 0x01c20c00,
-    [AW_H3_UART0]      = 0x01c28000,
-    [AW_H3_UART1]      = 0x01c28400,
-    [AW_H3_UART2]      = 0x01c28800,
-    [AW_H3_UART3]      = 0x01c28c00,
-    [AW_H3_EMAC]       = 0x01c30000,
-    [AW_H3_DRAMCOM]    = 0x01c62000,
-    [AW_H3_DRAMCTL]    = 0x01c63000,
-    [AW_H3_DRAMPHY]    = 0x01c65000,
-    [AW_H3_GIC_DIST]   = 0x01c81000,
-    [AW_H3_GIC_CPU]    = 0x01c82000,
-    [AW_H3_GIC_HYP]    = 0x01c84000,
-    [AW_H3_GIC_VCPU]   = 0x01c86000,
-    [AW_H3_RTC]        = 0x01f00000,
-    [AW_H3_CPUCFG]     = 0x01f01c00,
-    [AW_H3_SDRAM]      = 0x40000000
+    [AW_H3_DEV_SRAM_A1]    = 0x00000000,
+    [AW_H3_DEV_SRAM_A2]    = 0x00044000,
+    [AW_H3_DEV_SRAM_C]     = 0x00010000,
+    [AW_H3_DEV_SYSCTRL]    = 0x01c00000,
+    [AW_H3_DEV_MMC0]       = 0x01c0f000,
+    [AW_H3_DEV_SID]        = 0x01c14000,
+    [AW_H3_DEV_EHCI0]      = 0x01c1a000,
+    [AW_H3_DEV_OHCI0]      = 0x01c1a400,
+    [AW_H3_DEV_EHCI1]      = 0x01c1b000,
+    [AW_H3_DEV_OHCI1]      = 0x01c1b400,
+    [AW_H3_DEV_EHCI2]      = 0x01c1c000,
+    [AW_H3_DEV_OHCI2]      = 0x01c1c400,
+    [AW_H3_DEV_EHCI3]      = 0x01c1d000,
+    [AW_H3_DEV_OHCI3]      = 0x01c1d400,
+    [AW_H3_DEV_CCU]        = 0x01c20000,
+    [AW_H3_DEV_PIT]        = 0x01c20c00,
+    [AW_H3_DEV_UART0]      = 0x01c28000,
+    [AW_H3_DEV_UART1]      = 0x01c28400,
+    [AW_H3_DEV_UART2]      = 0x01c28800,
+    [AW_H3_DEV_UART3]      = 0x01c28c00,
+    [AW_H3_DEV_EMAC]       = 0x01c30000,
+    [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
+    [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
+    [AW_H3_DEV_DRAMPHY]    = 0x01c65000,
+    [AW_H3_DEV_GIC_DIST]   = 0x01c81000,
+    [AW_H3_DEV_GIC_CPU]    = 0x01c82000,
+    [AW_H3_DEV_GIC_HYP]    = 0x01c84000,
+    [AW_H3_DEV_GIC_VCPU]   = 0x01c86000,
+    [AW_H3_DEV_RTC]        = 0x01f00000,
+    [AW_H3_DEV_CPUCFG]     = 0x01f01c00,
+    [AW_H3_DEV_SDRAM]      = 0x40000000
 };
 
 /* List of unimplemented devices */

@@ -183,7 +183,7 @@ void allwinner_h3_bootrom_setup(AwH3State *s, BlockBackend *blk)
     }
 
     rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
-                  rom_size, s->memmap[AW_H3_SRAM_A1],
+                  rom_size, s->memmap[AW_H3_DEV_SRAM_A1],
                   NULL, NULL, NULL, NULL, false);
 }
 

@@ -262,10 +262,10 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
     qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions", true);
     sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
 
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_GIC_DIST]);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_GIC_CPU]);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_GIC_HYP]);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_GIC_VCPU]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0, s->memmap[AW_H3_DEV_GIC_DIST]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1, s->memmap[AW_H3_DEV_GIC_CPU]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2, s->memmap[AW_H3_DEV_GIC_HYP]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3, s->memmap[AW_H3_DEV_GIC_VCPU]);
 
     /*
      * Wire the outputs from each CPU's generic timer and the GICv3

@@ -312,7 +312,7 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
 
     /* Timer */
     sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_DEV_PIT]);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_TIMER0));
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,

@@ -325,32 +325,32 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
                             32 * KiB, &error_abort);
     memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
                             44 * KiB, &error_abort);
-    memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A1],
+    memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A1],
                                 &s->sram_a1);
-    memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_A2],
+    memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_A2],
                                 &s->sram_a2);
-    memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_SRAM_C],
+    memory_region_add_subregion(get_system_memory(), s->memmap[AW_H3_DEV_SRAM_C],
                                 &s->sram_c);
 
     /* Clock Control Unit */
     sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_DEV_CCU]);
 
     /* System Control */
     sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_SYSCTRL]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0, s->memmap[AW_H3_DEV_SYSCTRL]);
 
     /* CPU Configuration */
     sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_CPUCFG]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0, s->memmap[AW_H3_DEV_CPUCFG]);
 
     /* Security Identifier */
     sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_DEV_SID]);
 
     /* SD/MMC */
     sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_DEV_MMC0]);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_MMC0));
 

@@ -364,63 +364,63 @@ static void allwinner_h3_realize(DeviceState *dev, Error **errp)
         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
     }
     sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_DEV_EMAC]);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
                        qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_EMAC));
 
     /* Universal Serial Bus */
-    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
+    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI0],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_EHCI0));
-    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
+    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI1],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_EHCI1));
-    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
+    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI2],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_EHCI2));
-    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
+    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI3],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_EHCI3));
 
-    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
+    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI0],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_OHCI0));
-    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
+    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI1],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_OHCI1));
-    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
+    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI2],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_OHCI2));
-    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
+    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI3],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_OHCI3));
 
     /* UART0. For future clocktree API: All UARTS are connected to APB2_CLK. */
-    serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
+    serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
                    qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART0),
                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
     /* UART1 */
-    serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
+    serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
                    qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART1),
                    115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
     /* UART2 */
-    serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
+    serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
                    qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART2),
                    115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
     /* UART3 */
-    serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
+    serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
                    qdev_get_gpio_in(DEVICE(&s->gic), AW_H3_GIC_SPI_UART3),
                    115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
 
     /* DRAMC */
     sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DRAMCOM]);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DRAMCTL]);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DRAMPHY]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0, s->memmap[AW_H3_DEV_DRAMCOM]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1, s->memmap[AW_H3_DEV_DRAMCTL]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2, s->memmap[AW_H3_DEV_DRAMPHY]);
 
     /* RTC */
     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_DEV_RTC]);
 
     /* Unimplemented devices */
     for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {

hw/arm/orangepi.c +3 -3

index 1679468232..17a568a2b4 100644
@@ -79,7 +79,7 @@ static void orangepi_init(MachineState *machine)
     object_property_set_int(OBJECT(&h3->emac), "phy-addr", 1, &error_abort);
 
     /* DRAMC */
-    object_property_set_uint(OBJECT(h3), "ram-addr", h3->memmap[AW_H3_SDRAM],
+    object_property_set_uint(OBJECT(h3), "ram-addr", h3->memmap[AW_H3_DEV_SDRAM],
                              &error_abort);
     object_property_set_int(OBJECT(h3), "ram-size", machine->ram_size / MiB,
                             &error_abort);

@@ -98,7 +98,7 @@ static void orangepi_init(MachineState *machine)
     qdev_realize_and_unref(carddev, bus, &error_fatal);
 
     /* SDRAM */
-    memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_SDRAM],
+    memory_region_add_subregion(get_system_memory(), h3->memmap[AW_H3_DEV_SDRAM],
                                 machine->ram);
 
     /* Load target kernel or start using BootROM */

@@ -106,7 +106,7 @@ static void orangepi_init(MachineState *machine)
         /* Use Boot ROM to copy data from SD card to SRAM */
         allwinner_h3_bootrom_setup(h3, blk);
     }
-    orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
+    orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM];
     orangepi_binfo.ram_size = machine->ram_size;
     arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
 }

+Niek as maintainer.

Quoted 7 lines · Eduardo Habkost

Some of the enum constant names conflict with the QOM type check macros. This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE().

Rename all the constants to AW_H3_DEV_*, to avoid conflicts.

Review

Quoted 8 lines

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/arm/allwinner-h3.h |  62 ++++++++---------
 hw/arm/allwinner-h3.c         | 124 +++++++++++++++++-----------------
 hw/arm/orangepi.c             |   6 +-
 3 files changed, 96 insertions(+), 96 deletions(-)

(quoted diff) +0 -0

b/include/hw/arm/allwinner-h3.h

Quoted 32 lines

index 82e4e59216..626139dcb3 100644

include/hw/arm/allwinner-h3.h +0 -25

@@ -61,37 +61,37 @@
  * @see AwH3State
  */
 enum {
-    AW_H3_SRAM_A1,
-    AW_H3_SRAM_A2,
-    AW_H3_SRAM_C,
-    AW_H3_SYSCTRL,
-    AW_H3_MMC0,
-    AW_H3_SID,
-    AW_H3_EHCI0,
-    AW_H3_OHCI0,
-    AW_H3_EHCI1,
-    AW_H3_OHCI1,
-    AW_H3_EHCI2,
-    AW_H3_OHCI2,
-    AW_H3_EHCI3,
-    AW_H3_OHCI3,
-    AW_H3_CCU,
-    AW_H3_PIT,
-    AW_H3_UART0,
-    AW_H3_UART1,
-    AW_H3_UART2,
-    AW_H3_UART3,
-    AW_H3_EMAC,
-    AW_H3_DRAMCOM,
-    AW_H3_DRAMCTL,
-    AW_H3_DRAMPHY,
-    AW_H3_GIC_DIST,

include/hw/arm/allwinner-h3.h line 67

Quoted 10 lines

include/hw/arm/allwinner-h3.h +4 -6

-    AW_H3_GIC_CPU,
-    AW_H3_GIC_HYP,
-    AW_H3_GIC_VCPU,
-    AW_H3_RTC,
-    AW_H3_CPUCFG,
-    AW_H3_SDRAM
+    AW_H3_DEV_SRAM_A1,
+    AW_H3_DEV_SRAM_A2,
+    AW_H3_DEV_SRAM_C,
+    AW_H3_DEV_SYSCTRL,

My 2 cents:
These are not devices, but peripheral blocks or IP cores. Anyway, short change could be to name them E_AW_H3_xxx, but I don't understand why these are exposed. This enum should be locally declared in hw/arm/allwinner-h3.c, and the SoC might provide a get_sdram_base_address() method so the machine can access it.

hw/arm/allwinner-h3.c void allwinner_h3_bootrom_setup(AwH3State *s,

Quoted 104 lines

include/hw/arm/allwinner-h3.h +27 -0

+    AW_H3_DEV_MMC0,
+    AW_H3_DEV_SID,
+    AW_H3_DEV_EHCI0,
+    AW_H3_DEV_OHCI0,
+    AW_H3_DEV_EHCI1,
+    AW_H3_DEV_OHCI1,
+    AW_H3_DEV_EHCI2,
+    AW_H3_DEV_OHCI2,
+    AW_H3_DEV_EHCI3,
+    AW_H3_DEV_OHCI3,
+    AW_H3_DEV_CCU,
+    AW_H3_DEV_PIT,
+    AW_H3_DEV_UART0,
+    AW_H3_DEV_UART1,
+    AW_H3_DEV_UART2,
+    AW_H3_DEV_UART3,
+    AW_H3_DEV_EMAC,
+    AW_H3_DEV_DRAMCOM,
+    AW_H3_DEV_DRAMCTL,
+    AW_H3_DEV_DRAMPHY,
+    AW_H3_DEV_GIC_DIST,
+    AW_H3_DEV_GIC_CPU,
+    AW_H3_DEV_GIC_HYP,
+    AW_H3_DEV_GIC_VCPU,
+    AW_H3_DEV_RTC,
+    AW_H3_DEV_CPUCFG,
+    AW_H3_DEV_SDRAM
 };
 
 /** Total number of CPU cores in the H3 SoC */

hw/arm/allwinner-h3.c +31 -31

index ff92ded82c..341abe6718 100644
@@ -35,37 +35,37 @@
 
 /* Memory map */
 const hwaddr allwinner_h3_memmap[] = {
-    [AW_H3_SRAM_A1]    = 0x00000000,
-    [AW_H3_SRAM_A2]    = 0x00044000,
-    [AW_H3_SRAM_C]     = 0x00010000,
-    [AW_H3_SYSCTRL]    = 0x01c00000,
-    [AW_H3_MMC0]       = 0x01c0f000,
-    [AW_H3_SID]        = 0x01c14000,
-    [AW_H3_EHCI0]      = 0x01c1a000,
-    [AW_H3_OHCI0]      = 0x01c1a400,
-    [AW_H3_EHCI1]      = 0x01c1b000,
-    [AW_H3_OHCI1]      = 0x01c1b400,
-    [AW_H3_EHCI2]      = 0x01c1c000,
-    [AW_H3_OHCI2]      = 0x01c1c400,
-    [AW_H3_EHCI3]      = 0x01c1d000,
-    [AW_H3_OHCI3]      = 0x01c1d400,
-    [AW_H3_CCU]        = 0x01c20000,
-    [AW_H3_PIT]        = 0x01c20c00,
-    [AW_H3_UART0]      = 0x01c28000,
-    [AW_H3_UART1]      = 0x01c28400,
-    [AW_H3_UART2]      = 0x01c28800,
-    [AW_H3_UART3]      = 0x01c28c00,
-    [AW_H3_EMAC]       = 0x01c30000,
-    [AW_H3_DRAMCOM]    = 0x01c62000,
-    [AW_H3_DRAMCTL]    = 0x01c63000,
-    [AW_H3_DRAMPHY]    = 0x01c65000,
-    [AW_H3_GIC_DIST]   = 0x01c81000,
-    [AW_H3_GIC_CPU]    = 0x01c82000,
-    [AW_H3_GIC_HYP]    = 0x01c84000,
-    [AW_H3_GIC_VCPU]   = 0x01c86000,
-    [AW_H3_RTC]        = 0x01f00000,
-    [AW_H3_CPUCFG]     = 0x01f01c00,
-    [AW_H3_SDRAM]      = 0x40000000
+    [AW_H3_DEV_SRAM_A1]    = 0x00000000,
+    [AW_H3_DEV_SRAM_A2]    = 0x00044000,
+    [AW_H3_DEV_SRAM_C]     = 0x00010000,
+    [AW_H3_DEV_SYSCTRL]    = 0x01c00000,
+    [AW_H3_DEV_MMC0]       = 0x01c0f000,
+    [AW_H3_DEV_SID]        = 0x01c14000,
+    [AW_H3_DEV_EHCI0]      = 0x01c1a000,
+    [AW_H3_DEV_OHCI0]      = 0x01c1a400,
+    [AW_H3_DEV_EHCI1]      = 0x01c1b000,
+    [AW_H3_DEV_OHCI1]      = 0x01c1b400,
+    [AW_H3_DEV_EHCI2]      = 0x01c1c000,
+    [AW_H3_DEV_OHCI2]      = 0x01c1c400,
+    [AW_H3_DEV_EHCI3]      = 0x01c1d000,
+    [AW_H3_DEV_OHCI3]      = 0x01c1d400,
+    [AW_H3_DEV_CCU]        = 0x01c20000,
+    [AW_H3_DEV_PIT]        = 0x01c20c00,
+    [AW_H3_DEV_UART0]      = 0x01c28000,
+    [AW_H3_DEV_UART1]      = 0x01c28400,
+    [AW_H3_DEV_UART2]      = 0x01c28800,
+    [AW_H3_DEV_UART3]      = 0x01c28c00,
+    [AW_H3_DEV_EMAC]       = 0x01c30000,
+    [AW_H3_DEV_DRAMCOM]    = 0x01c62000,
+    [AW_H3_DEV_DRAMCTL]    = 0x01c63000,
+    [AW_H3_DEV_DRAMPHY]    = 0x01c65000,
+    [AW_H3_DEV_GIC_DIST]   = 0x01c81000,
+    [AW_H3_DEV_GIC_CPU]    = 0x01c82000,
+    [AW_H3_DEV_GIC_HYP]    = 0x01c84000,
+    [AW_H3_DEV_GIC_VCPU]   = 0x01c86000,
+    [AW_H3_DEV_RTC]        = 0x01f00000,
+    [AW_H3_DEV_CPUCFG]     = 0x01f01c00,
+    [AW_H3_DEV_SDRAM]      = 0x40000000
 };
 
 /* List of unimplemented devices */

@@ -183,7 +183,7 @@ void allwinner_h3_bootrom_setup(AwH3State *s,

BlockBackend *blk)

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev,

Quoted 9 lines

hw/arm/allwinner-h3.c +1 -1

     }
 
     rom_add_blob("allwinner-h3.bootrom", buffer, rom_size,
-                  rom_size, s->memmap[AW_H3_SRAM_A1],
+                  rom_size, s->memmap[AW_H3_DEV_SRAM_A1],
                   NULL, NULL, NULL, NULL, false);
 }
 

@@ -262,10 +262,10 @@ static void allwinner_h3_realize(DeviceState *dev,

Error **errp)

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 262

Quoted 1 line

hw/arm/allwinner-h3.c +0 -0

     qdev_prop_set_bit(DEVICE(&s->gic), "has-virtualization-extensions",

true);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 3 lines

hw/arm/allwinner-h3.c +0 -1

     sysbus_realize(SYS_BUS_DEVICE(&s->gic), &error_fatal);
 
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0,

s->memmap[AW_H3_GIC_DIST]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 266

Quoted 1 line

hw/arm/allwinner-h3.c +0 -1

-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1,

s->memmap[AW_H3_GIC_CPU]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 267

Quoted 1 line

hw/arm/allwinner-h3.c +0 -1

-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2,

s->memmap[AW_H3_GIC_HYP]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 268

Quoted 1 line

hw/arm/allwinner-h3.c +0 -1

-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3,

s->memmap[AW_H3_GIC_VCPU]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 265

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 0,

s->memmap[AW_H3_DEV_GIC_DIST]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 266

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 1,

s->memmap[AW_H3_DEV_GIC_CPU]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 267

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 2,

s->memmap[AW_H3_DEV_GIC_HYP]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 268

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gic), 3,

s->memmap[AW_H3_DEV_GIC_VCPU]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev,

Quoted 4 lines

hw/arm/allwinner-h3.c +0 -0

     /*
      * Wire the outputs from each CPU's generic timer and the GICv3

@@ -312,7 +312,7 @@ static void allwinner_h3_realize(DeviceState *dev,

Error **errp)

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 5 lines

hw/arm/allwinner-h3.c +1 -1

     /* Timer */
     sysbus_realize(SYS_BUS_DEVICE(&s->timer), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0, s->memmap[AW_H3_PIT]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->timer), 0,

s->memmap[AW_H3_DEV_PIT]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 316

Quoted 2 lines

hw/arm/allwinner-h3.c +0 -0

     sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 0,
                        qdev_get_gpio_in(DEVICE(&s->gic),

AW_H3_GIC_SPI_TIMER0));

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev,

Quoted 2 lines

hw/arm/allwinner-h3.c +0 -0

     sysbus_connect_irq(SYS_BUS_DEVICE(&s->timer), 1,

@@ -325,32 +325,32 @@ static void allwinner_h3_realize(DeviceState *dev,

Error **errp)

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 4 lines

hw/arm/allwinner-h3.c +0 -1

                             32 * KiB, &error_abort);
     memory_region_init_ram(&s->sram_c, OBJECT(dev), "sram C",
                             44 * KiB, &error_abort);
-    memory_region_add_subregion(get_system_memory(),

s->memmap[AW_H3_SRAM_A1],

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 328

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    memory_region_add_subregion(get_system_memory(),

s->memmap[AW_H3_DEV_SRAM_A1],

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 330

Quoted 2 lines

hw/arm/allwinner-h3.c +0 -1

                                 &s->sram_a1);
-    memory_region_add_subregion(get_system_memory(),

s->memmap[AW_H3_SRAM_A2],

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 330

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    memory_region_add_subregion(get_system_memory(),

s->memmap[AW_H3_DEV_SRAM_A2],

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 332

Quoted 2 lines

hw/arm/allwinner-h3.c +0 -1

                                 &s->sram_a2);
-    memory_region_add_subregion(get_system_memory(),

s->memmap[AW_H3_SRAM_C],

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 332

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    memory_region_add_subregion(get_system_memory(),

s->memmap[AW_H3_DEV_SRAM_C],

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 6 lines

hw/arm/allwinner-h3.c +1 -1

                                 &s->sram_c);
 
     /* Clock Control Unit */
     sysbus_realize(SYS_BUS_DEVICE(&s->ccu), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0, s->memmap[AW_H3_CCU]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->ccu), 0,

s->memmap[AW_H3_DEV_CCU]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 4 lines

hw/arm/allwinner-h3.c +0 -1

     /* System Control */
     sysbus_realize(SYS_BUS_DEVICE(&s->sysctrl), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0,

s->memmap[AW_H3_SYSCTRL]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 340

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sysctrl), 0,

s->memmap[AW_H3_DEV_SYSCTRL]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 4 lines

hw/arm/allwinner-h3.c +0 -1

     /* CPU Configuration */
     sysbus_realize(SYS_BUS_DEVICE(&s->cpucfg), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0,

s->memmap[AW_H3_CPUCFG]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 343

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->cpucfg), 0,

s->memmap[AW_H3_DEV_CPUCFG]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 5 lines

hw/arm/allwinner-h3.c +1 -1

     /* Security Identifier */
     sysbus_realize(SYS_BUS_DEVICE(&s->sid), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0, s->memmap[AW_H3_SID]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->sid), 0,

s->memmap[AW_H3_DEV_SID]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 5 lines

hw/arm/allwinner-h3.c +1 -1

     /* SD/MMC */
     sysbus_realize(SYS_BUS_DEVICE(&s->mmc0), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0, s->memmap[AW_H3_MMC0]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->mmc0), 0,

s->memmap[AW_H3_DEV_MMC0]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 351

Quoted 2 lines

hw/arm/allwinner-h3.c +0 -0

     sysbus_connect_irq(SYS_BUS_DEVICE(&s->mmc0), 0,
                        qdev_get_gpio_in(DEVICE(&s->gic),

AW_H3_GIC_SPI_MMC0));

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev,

Quoted 2 lines

hw/arm/allwinner-h3.c +0 -0

@@ -364,63 +364,63 @@ static void allwinner_h3_realize(DeviceState *dev,

Error **errp)

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 5 lines

hw/arm/allwinner-h3.c +1 -1

         qdev_set_nic_properties(DEVICE(&s->emac), &nd_table[0]);
     }
     sysbus_realize(SYS_BUS_DEVICE(&s->emac), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0, s->memmap[AW_H3_EMAC]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->emac), 0,

s->memmap[AW_H3_DEV_EMAC]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 369

Quoted 2 lines

hw/arm/allwinner-h3.c +0 -0

     sysbus_connect_irq(SYS_BUS_DEVICE(&s->emac), 0,
                        qdev_get_gpio_in(DEVICE(&s->gic),

AW_H3_GIC_SPI_EMAC));

Quoted 27 lines

hw/arm/allwinner-h3.c +6 -6

     /* Universal Serial Bus */
-    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI0],
+    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI0],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_EHCI0));
-    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI1],
+    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI1],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_EHCI1));
-    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI2],
+    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI2],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_EHCI2));
-    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_EHCI3],
+    sysbus_create_simple(TYPE_AW_H3_EHCI, s->memmap[AW_H3_DEV_EHCI3],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_EHCI3));
 
-    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI0],
+    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI0],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_OHCI0));
-    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI1],
+    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI1],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_OHCI1));

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 10 lines

hw/arm/allwinner-h3.c +2 -2

-    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI2],
+    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI2],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_OHCI2));
-    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_OHCI3],
+    sysbus_create_simple("sysbus-ohci", s->memmap[AW_H3_DEV_OHCI3],
                          qdev_get_gpio_in(DEVICE(&s->gic),
                                           AW_H3_GIC_SPI_OHCI3));
 
     /* UART0. For future clocktree API: All UARTS are connected to

APB2_CLK. */

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 3 lines

hw/arm/allwinner-h3.c +1 -1

-    serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART0], 2,
+    serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART0], 2,
                    qdev_get_gpio_in(DEVICE(&s->gic),

AW_H3_GIC_SPI_UART0),

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 5 lines

hw/arm/allwinner-h3.c +1 -1

                    115200, serial_hd(0), DEVICE_NATIVE_ENDIAN);
     /* UART1 */
-    serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART1], 2,
+    serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART1], 2,
                    qdev_get_gpio_in(DEVICE(&s->gic),

AW_H3_GIC_SPI_UART1),

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 5 lines

hw/arm/allwinner-h3.c +1 -1

                    115200, serial_hd(1), DEVICE_NATIVE_ENDIAN);
     /* UART2 */
-    serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART2], 2,
+    serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART2], 2,
                    qdev_get_gpio_in(DEVICE(&s->gic),

AW_H3_GIC_SPI_UART2),

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 5 lines

hw/arm/allwinner-h3.c +1 -1

                    115200, serial_hd(2), DEVICE_NATIVE_ENDIAN);
     /* UART3 */
-    serial_mm_init(get_system_memory(), s->memmap[AW_H3_UART3], 2,
+    serial_mm_init(get_system_memory(), s->memmap[AW_H3_DEV_UART3], 2,
                    qdev_get_gpio_in(DEVICE(&s->gic),

AW_H3_GIC_SPI_UART3),

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 5 lines

hw/arm/allwinner-h3.c +0 -1

                    115200, serial_hd(3), DEVICE_NATIVE_ENDIAN);
 
     /* DRAMC */
     sysbus_realize(SYS_BUS_DEVICE(&s->dramc), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0,

s->memmap[AW_H3_DRAMCOM]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 417

Quoted 1 line

hw/arm/allwinner-h3.c +0 -1

-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1,

s->memmap[AW_H3_DRAMCTL]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 418

Quoted 1 line

hw/arm/allwinner-h3.c +0 -1

-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2,

s->memmap[AW_H3_DRAMPHY]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 416

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 0,

s->memmap[AW_H3_DEV_DRAMCOM]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 417

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 1,

s->memmap[AW_H3_DEV_DRAMCTL]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, · line 418

Quoted 1 line

hw/arm/allwinner-h3.c +1 -0

+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->dramc), 2,

s->memmap[AW_H3_DEV_DRAMPHY]);

hw/arm/allwinner-h3.c static void allwinner_h3_realize(DeviceState *dev, Error **errp)

Quoted 5 lines

hw/arm/allwinner-h3.c +1 -1

     /* RTC */
     sysbus_realize(SYS_BUS_DEVICE(&s->rtc), &error_fatal);
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0, s->memmap[AW_H3_RTC]);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->rtc), 0,

s->memmap[AW_H3_DEV_RTC]);

hw/arm/orangepi.c static void orangepi_init(MachineState *machine) · line 79

Quoted 9 lines

hw/arm/allwinner-h3.c +0 -0

     /* Unimplemented devices */
     for (i = 0; i < ARRAY_SIZE(unimplemented); i++) {

hw/arm/orangepi.c +0 -0

index 1679468232..17a568a2b4 100644
@@ -79,7 +79,7 @@ static void orangepi_init(MachineState *machine)
     object_property_set_int(OBJECT(&h3->emac), "phy-addr", 1,

&error_abort);

hw/arm/orangepi.c static void orangepi_init(MachineState *machine) · line 81

Quoted 3 lines

hw/arm/orangepi.c +0 -1

     /* DRAMC */
-    object_property_set_uint(OBJECT(h3), "ram-addr",

h3->memmap[AW_H3_SDRAM],

hw/arm/orangepi.c static void orangepi_init(MachineState *machine) · line 81

Quoted 1 line

hw/arm/orangepi.c +1 -0

+    object_property_set_uint(OBJECT(h3), "ram-addr",

h3->memmap[AW_H3_DEV_SDRAM],

hw/arm/orangepi.c static void orangepi_init(MachineState *machine) · line 83

Quoted 2 lines

hw/arm/orangepi.c +0 -0

                              &error_abort);
     object_property_set_int(OBJECT(h3), "ram-size", machine->ram_size /

MiB,

hw/arm/orangepi.c static void orangepi_init(MachineState *machine) · line 101

Quoted 6 lines

hw/arm/orangepi.c +0 -1

                             &error_abort);

@@ -98,7 +98,7 @@ static void orangepi_init(MachineState *machine)
     qdev_realize_and_unref(carddev, bus, &error_fatal);
 
     /* SDRAM */
-    memory_region_add_subregion(get_system_memory(),

h3->memmap[AW_H3_SDRAM],

hw/arm/orangepi.c static void orangepi_init(MachineState *machine) · line 101

Quoted 1 line

hw/arm/orangepi.c +1 -0

+    memory_region_add_subregion(get_system_memory(),

h3->memmap[AW_H3_DEV_SDRAM],

Quoted 13 lines

hw/arm/orangepi.c +1 -1

                                 machine->ram);
 
     /* Load target kernel or start using BootROM */

@@ -106,7 +106,7 @@ static void orangepi_init(MachineState *machine)
         /* Use Boot ROM to copy data from SD card to SRAM */
         allwinner_h3_bootrom_setup(h3, blk);
     }
-    orangepi_binfo.loader_start = h3->memmap[AW_H3_SDRAM];
+    orangepi_binfo.loader_start = h3->memmap[AW_H3_DEV_SDRAM];
     orangepi_binfo.ram_size = machine->ram_size;
     arm_load_kernel(ARM_CPU(first_cpu), machine, &orangepi_binfo);
 }

Hi,

Interesting suggestion Philippe. I modelled the initial code of the H3 SoC mostly in-line with the aspeed SoC,
to let it use commonly applied code structures where possible. And it looks like in this series, aspeed_soc.h is also
getting the same change. I'll see if I can find some time to make a small patch to move the enum to the local allwinner-h3.c file like you suggested.

For Eduardo's work, I'm OK with a rename for now to AW_H3_DEV_*. I see it is also done like that in aspeed_soc.h and similar files.
I do have one follow-up question: which value(s) from the enum are actually in conflict? Could you add that in the commit message perhaps, for clarity?

With that answered:

Reviewed-by Niek Linnenbank <[email protected]>

Some of the enum constant names conflict with the QOM type check macros. This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE().

Rename all the constants to IBEX_DEV_*, to avoid conflicts.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/riscv/opentitan.h | 38 ++++++++--------
 hw/riscv/opentitan.c         | 84 ++++++++++++++++++------------------
 2 files changed, 61 insertions(+), 61 deletions(-)

include/hw/riscv/opentitan.h +19 -19

index 8f29b9cbbf..835a80f896 100644
@@ -49,25 +49,25 @@ typedef struct OpenTitanState {
 } OpenTitanState;
 
 enum {
-    IBEX_ROM,
-    IBEX_RAM,
-    IBEX_FLASH,
-    IBEX_UART,
-    IBEX_GPIO,
-    IBEX_SPI,
-    IBEX_FLASH_CTRL,
-    IBEX_RV_TIMER,
-    IBEX_AES,
-    IBEX_HMAC,
-    IBEX_PLIC,
-    IBEX_PWRMGR,
-    IBEX_RSTMGR,
-    IBEX_CLKMGR,
-    IBEX_PINMUX,
-    IBEX_ALERT_HANDLER,
-    IBEX_NMI_GEN,
-    IBEX_USBDEV,
-    IBEX_PADCTRL,
+    IBEX_DEV_ROM,
+    IBEX_DEV_RAM,
+    IBEX_DEV_FLASH,
+    IBEX_DEV_UART,
+    IBEX_DEV_GPIO,
+    IBEX_DEV_SPI,
+    IBEX_DEV_FLASH_CTRL,
+    IBEX_DEV_RV_TIMER,
+    IBEX_DEV_AES,
+    IBEX_DEV_HMAC,
+    IBEX_DEV_PLIC,
+    IBEX_DEV_PWRMGR,
+    IBEX_DEV_RSTMGR,
+    IBEX_DEV_CLKMGR,
+    IBEX_DEV_PINMUX,
+    IBEX_DEV_ALERT_HANDLER,
+    IBEX_DEV_NMI_GEN,
+    IBEX_DEV_USBDEV,
+    IBEX_DEV_PADCTRL,
 };
 
 enum {

hw/riscv/opentitan.c +42 -43

index a8f0039e51..23ba3b4bfc 100644
@@ -32,25 +32,25 @@ static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
 } ibex_memmap[] = {
-    [IBEX_ROM] =            {  0x00008000, 16 * KiB },
-    [IBEX_RAM] =            {  0x10000000,  0x10000 },
-    [IBEX_FLASH] =          {  0x20000000,  0x80000 },
-    [IBEX_UART] =           {  0x40000000,  0x10000 },
-    [IBEX_GPIO] =           {  0x40010000,  0x10000 },
-    [IBEX_SPI] =            {  0x40020000,  0x10000 },
-    [IBEX_FLASH_CTRL] =     {  0x40030000,  0x10000 },
-    [IBEX_PINMUX] =         {  0x40070000,  0x10000 },
-    [IBEX_RV_TIMER] =       {  0x40080000,  0x10000 },
-    [IBEX_PLIC] =           {  0x40090000,  0x10000 },
-    [IBEX_PWRMGR] =         {  0x400A0000,  0x10000 },
-    [IBEX_RSTMGR] =         {  0x400B0000,  0x10000 },
-    [IBEX_CLKMGR] =         {  0x400C0000,  0x10000 },
-    [IBEX_AES] =            {  0x40110000,  0x10000 },
-    [IBEX_HMAC] =           {  0x40120000,  0x10000 },
-    [IBEX_ALERT_HANDLER] =  {  0x40130000,  0x10000 },
-    [IBEX_NMI_GEN] =        {  0x40140000,  0x10000 },
-    [IBEX_USBDEV] =         {  0x40150000,  0x10000 },
-    [IBEX_PADCTRL] =        {  0x40160000,  0x10000 }
+    [IBEX_DEV_ROM] =            {  0x00008000, 16 * KiB },
+    [IBEX_DEV_RAM] =            {  0x10000000,  0x10000 },
+    [IBEX_DEV_FLASH] =          {  0x20000000,  0x80000 },
+    [IBEX_DEV_UART] =           {  0x40000000,  0x10000 },
+    [IBEX_DEV_GPIO] =           {  0x40010000,  0x10000 },
+    [IBEX_DEV_SPI] =            {  0x40020000,  0x10000 },
+    [IBEX_DEV_FLASH_CTRL] =     {  0x40030000,  0x10000 },
+    [IBEX_DEV_PINMUX] =         {  0x40070000,  0x10000 },
+    [IBEX_DEV_RV_TIMER] =       {  0x40080000,  0x10000 },
+    [IBEX_DEV_PLIC] =           {  0x40090000,  0x10000 },
+    [IBEX_DEV_PWRMGR] =         {  0x400A0000,  0x10000 },
+    [IBEX_DEV_RSTMGR] =         {  0x400B0000,  0x10000 },
+    [IBEX_DEV_CLKMGR] =         {  0x400C0000,  0x10000 },
+    [IBEX_DEV_AES] =            {  0x40110000,  0x10000 },
+    [IBEX_DEV_HMAC] =           {  0x40120000,  0x10000 },
+    [IBEX_DEV_ALERT_HANDLER] =  {  0x40130000,  0x10000 },
+    [IBEX_DEV_NMI_GEN] =        {  0x40140000,  0x10000 },
+    [IBEX_DEV_USBDEV] =         {  0x40150000,  0x10000 },
+    [IBEX_DEV_PADCTRL] =        {  0x40160000,  0x10000 }
 };
 
 static void opentitan_board_init(MachineState *machine)

@@ -66,12 +66,12 @@ static void opentitan_board_init(MachineState *machine)
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
     memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
-        memmap[IBEX_RAM].size, &error_fatal);
+        memmap[IBEX_DEV_RAM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
-        memmap[IBEX_RAM].base, main_mem);
+        memmap[IBEX_DEV_RAM].base, main_mem);
 
     if (machine->firmware) {
-        riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
+        riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
     }
 
     if (machine->kernel_filename) {

@@ -115,28 +115,28 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
 
     /* Boot ROM */
     memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
-                           memmap[IBEX_ROM].size, &error_fatal);
+                           memmap[IBEX_DEV_ROM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
-        memmap[IBEX_ROM].base, &s->rom);
+        memmap[IBEX_DEV_ROM].base, &s->rom);
 
     /* Flash memory */
     memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
-                           memmap[IBEX_FLASH].size, &error_fatal);
-    memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base,
+                           memmap[IBEX_DEV_FLASH].size, &error_fatal);
+    memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
                                 &s->flash_mem);
 
     /* PLIC */
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
         return;
     }
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_PLIC].base);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
 
     /* UART */
     qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
         return;
     }
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_UART].base);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
                        0, qdev_get_gpio_in(DEVICE(&s->plic),
                        IBEX_UART_TX_WATERMARK_IRQ));

@@ -151,33 +151,33 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                        IBEX_UART_RX_OVERFLOW_IRQ));
 
     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
-        memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size);
+        memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
     create_unimplemented_device("riscv.lowrisc.ibex.spi",
-        memmap[IBEX_SPI].base, memmap[IBEX_SPI].size);
+        memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
     create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
-        memmap[IBEX_FLASH_CTRL].base, memmap[IBEX_FLASH_CTRL].size);
+        memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
     create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
-        memmap[IBEX_RV_TIMER].base, memmap[IBEX_RV_TIMER].size);
+        memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
     create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
-        memmap[IBEX_PWRMGR].base, memmap[IBEX_PWRMGR].size);
+        memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
     create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
-        memmap[IBEX_RSTMGR].base, memmap[IBEX_RSTMGR].size);
+        memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
     create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
-        memmap[IBEX_CLKMGR].base, memmap[IBEX_CLKMGR].size);
+        memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
     create_unimplemented_device("riscv.lowrisc.ibex.aes",
-        memmap[IBEX_AES].base, memmap[IBEX_AES].size);
+        memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
     create_unimplemented_device("riscv.lowrisc.ibex.hmac",
-        memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size);
+        memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
     create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
-        memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size);
+        memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
     create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
-        memmap[IBEX_ALERT_HANDLER].base, memmap[IBEX_ALERT_HANDLER].size);
+        memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
     create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
-        memmap[IBEX_NMI_GEN].base, memmap[IBEX_NMI_GEN].size);
+        memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
     create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
-        memmap[IBEX_USBDEV].base, memmap[IBEX_USBDEV].size);
+        memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
     create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
-        memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
+        memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
 }
 
 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)
--

2.26.2

Some of the enum constant names conflict with the QOM type check macros. This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE().

Rename all the constants to IBEX_DEV_*, to avoid conflicts.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/riscv/opentitan.h | 38 ++++++++--------
 hw/riscv/opentitan.c         | 84 ++++++++++++++++++------------------
 2 files changed, 61 insertions(+), 61 deletions(-)

include/hw/riscv/opentitan.h +9 -19

index 8f29b9cbbf..835a80f896 100644
@@ -49,25 +49,25 @@ typedef struct OpenTitanState {
 } OpenTitanState;
 
 enum {
-    IBEX_ROM,
-    IBEX_RAM,
-    IBEX_FLASH,
-    IBEX_UART,
-    IBEX_GPIO,
-    IBEX_SPI,
-    IBEX_FLASH_CTRL,
-    IBEX_RV_TIMER,
-    IBEX_AES,
-    IBEX_HMAC,
-    IBEX_PLIC,
-    IBEX_PWRMGR,
-    IBEX_RSTMGR,
-    IBEX_CLKMGR,
-    IBEX_PINMUX,
-    IBEX_ALERT_HANDLER,
-    IBEX_NMI_GEN,
-    IBEX_USBDEV,
-    IBEX_PADCTRL,
+    IBEX_DEV_ROM,
+    IBEX_DEV_RAM,
+    IBEX_DEV_FLASH,
+    IBEX_DEV_UART,
+    IBEX_DEV_GPIO,
+    IBEX_DEV_SPI,
+    IBEX_DEV_FLASH_CTRL,
+    IBEX_DEV_RV_TIMER,
+    IBEX_DEV_AES,

include/hw/riscv/opentitan.h +0 -0

 };
 
 enum {

hw/riscv/opentitan.c +42 -42

index a8f0039e51..23ba3b4bfc 100644
@@ -32,25 +32,25 @@ static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
 } ibex_memmap[] = {
-    [IBEX_ROM] =            {  0x00008000, 16 * KiB },
-    [IBEX_RAM] =            {  0x10000000,  0x10000 },
-    [IBEX_FLASH] =          {  0x20000000,  0x80000 },
-    [IBEX_UART] =           {  0x40000000,  0x10000 },
-    [IBEX_GPIO] =           {  0x40010000,  0x10000 },
-    [IBEX_SPI] =            {  0x40020000,  0x10000 },
-    [IBEX_FLASH_CTRL] =     {  0x40030000,  0x10000 },
-    [IBEX_PINMUX] =         {  0x40070000,  0x10000 },
-    [IBEX_RV_TIMER] =       {  0x40080000,  0x10000 },
-    [IBEX_PLIC] =           {  0x40090000,  0x10000 },
-    [IBEX_PWRMGR] =         {  0x400A0000,  0x10000 },
-    [IBEX_RSTMGR] =         {  0x400B0000,  0x10000 },
-    [IBEX_CLKMGR] =         {  0x400C0000,  0x10000 },
-    [IBEX_AES] =            {  0x40110000,  0x10000 },
-    [IBEX_HMAC] =           {  0x40120000,  0x10000 },
-    [IBEX_ALERT_HANDLER] =  {  0x40130000,  0x10000 },
-    [IBEX_NMI_GEN] =        {  0x40140000,  0x10000 },
-    [IBEX_USBDEV] =         {  0x40150000,  0x10000 },
-    [IBEX_PADCTRL] =        {  0x40160000,  0x10000 }
+    [IBEX_DEV_ROM] =            {  0x00008000, 16 * KiB },
+    [IBEX_DEV_RAM] =            {  0x10000000,  0x10000 },
+    [IBEX_DEV_FLASH] =          {  0x20000000,  0x80000 },
+    [IBEX_DEV_UART] =           {  0x40000000,  0x10000 },
+    [IBEX_DEV_GPIO] =           {  0x40010000,  0x10000 },
+    [IBEX_DEV_SPI] =            {  0x40020000,  0x10000 },
+    [IBEX_DEV_FLASH_CTRL] =     {  0x40030000,  0x10000 },
+    [IBEX_DEV_PINMUX] =         {  0x40070000,  0x10000 },
+    [IBEX_DEV_RV_TIMER] =       {  0x40080000,  0x10000 },
+    [IBEX_DEV_PLIC] =           {  0x40090000,  0x10000 },
+    [IBEX_DEV_PWRMGR] =         {  0x400A0000,  0x10000 },
+    [IBEX_DEV_RSTMGR] =         {  0x400B0000,  0x10000 },
+    [IBEX_DEV_CLKMGR] =         {  0x400C0000,  0x10000 },
+    [IBEX_DEV_AES] =            {  0x40110000,  0x10000 },
+    [IBEX_DEV_HMAC] =           {  0x40120000,  0x10000 },
+    [IBEX_DEV_ALERT_HANDLER] =  {  0x40130000,  0x10000 },
+    [IBEX_DEV_NMI_GEN] =        {  0x40140000,  0x10000 },
+    [IBEX_DEV_USBDEV] =         {  0x40150000,  0x10000 },
+    [IBEX_DEV_PADCTRL] =        {  0x40160000,  0x10000 }
 };
 
 static void opentitan_board_init(MachineState *machine)

@@ -66,12 +66,12 @@ static void opentitan_board_init(MachineState *machine)
     qdev_realize(DEVICE(&s->soc), NULL, &error_abort);
 
     memory_region_init_ram(main_mem, NULL, "riscv.lowrisc.ibex.ram",
-        memmap[IBEX_RAM].size, &error_fatal);
+        memmap[IBEX_DEV_RAM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
-        memmap[IBEX_RAM].base, main_mem);
+        memmap[IBEX_DEV_RAM].base, main_mem);
 
     if (machine->firmware) {
-        riscv_load_firmware(machine->firmware, memmap[IBEX_RAM].base, NULL);
+        riscv_load_firmware(machine->firmware, memmap[IBEX_DEV_RAM].base, NULL);
     }
 
     if (machine->kernel_filename) {

@@ -115,28 +115,28 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
 
     /* Boot ROM */
     memory_region_init_rom(&s->rom, OBJECT(dev_soc), "riscv.lowrisc.ibex.rom",
-                           memmap[IBEX_ROM].size, &error_fatal);
+                           memmap[IBEX_DEV_ROM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
-        memmap[IBEX_ROM].base, &s->rom);
+        memmap[IBEX_DEV_ROM].base, &s->rom);
 
     /* Flash memory */
     memory_region_init_rom(&s->flash_mem, OBJECT(dev_soc), "riscv.lowrisc.ibex.flash",
-                           memmap[IBEX_FLASH].size, &error_fatal);
-    memory_region_add_subregion(sys_mem, memmap[IBEX_FLASH].base,
+                           memmap[IBEX_DEV_FLASH].size, &error_fatal);
+    memory_region_add_subregion(sys_mem, memmap[IBEX_DEV_FLASH].base,
                                 &s->flash_mem);
 
     /* PLIC */
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->plic), errp)) {
         return;
     }
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_PLIC].base);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->plic), 0, memmap[IBEX_DEV_PLIC].base);
 
     /* UART */
     qdev_prop_set_chr(DEVICE(&(s->uart)), "chardev", serial_hd(0));
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->uart), errp)) {
         return;
     }
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_UART].base);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->uart), 0, memmap[IBEX_DEV_UART].base);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->uart),
                        0, qdev_get_gpio_in(DEVICE(&s->plic),
                        IBEX_UART_TX_WATERMARK_IRQ));

@@ -151,33 +151,33 @@ static void lowrisc_ibex_soc_realize(DeviceState *dev_soc, Error **errp)
                        IBEX_UART_RX_OVERFLOW_IRQ));
 
     create_unimplemented_device("riscv.lowrisc.ibex.gpio",
-        memmap[IBEX_GPIO].base, memmap[IBEX_GPIO].size);
+        memmap[IBEX_DEV_GPIO].base, memmap[IBEX_DEV_GPIO].size);
     create_unimplemented_device("riscv.lowrisc.ibex.spi",
-        memmap[IBEX_SPI].base, memmap[IBEX_SPI].size);
+        memmap[IBEX_DEV_SPI].base, memmap[IBEX_DEV_SPI].size);
     create_unimplemented_device("riscv.lowrisc.ibex.flash_ctrl",
-        memmap[IBEX_FLASH_CTRL].base, memmap[IBEX_FLASH_CTRL].size);
+        memmap[IBEX_DEV_FLASH_CTRL].base, memmap[IBEX_DEV_FLASH_CTRL].size);
     create_unimplemented_device("riscv.lowrisc.ibex.rv_timer",
-        memmap[IBEX_RV_TIMER].base, memmap[IBEX_RV_TIMER].size);
+        memmap[IBEX_DEV_RV_TIMER].base, memmap[IBEX_DEV_RV_TIMER].size);
     create_unimplemented_device("riscv.lowrisc.ibex.pwrmgr",
-        memmap[IBEX_PWRMGR].base, memmap[IBEX_PWRMGR].size);
+        memmap[IBEX_DEV_PWRMGR].base, memmap[IBEX_DEV_PWRMGR].size);
     create_unimplemented_device("riscv.lowrisc.ibex.rstmgr",
-        memmap[IBEX_RSTMGR].base, memmap[IBEX_RSTMGR].size);
+        memmap[IBEX_DEV_RSTMGR].base, memmap[IBEX_DEV_RSTMGR].size);
     create_unimplemented_device("riscv.lowrisc.ibex.clkmgr",
-        memmap[IBEX_CLKMGR].base, memmap[IBEX_CLKMGR].size);
+        memmap[IBEX_DEV_CLKMGR].base, memmap[IBEX_DEV_CLKMGR].size);
     create_unimplemented_device("riscv.lowrisc.ibex.aes",
-        memmap[IBEX_AES].base, memmap[IBEX_AES].size);
+        memmap[IBEX_DEV_AES].base, memmap[IBEX_DEV_AES].size);
     create_unimplemented_device("riscv.lowrisc.ibex.hmac",
-        memmap[IBEX_HMAC].base, memmap[IBEX_HMAC].size);
+        memmap[IBEX_DEV_HMAC].base, memmap[IBEX_DEV_HMAC].size);
     create_unimplemented_device("riscv.lowrisc.ibex.pinmux",
-        memmap[IBEX_PINMUX].base, memmap[IBEX_PINMUX].size);
+        memmap[IBEX_DEV_PINMUX].base, memmap[IBEX_DEV_PINMUX].size);
     create_unimplemented_device("riscv.lowrisc.ibex.alert_handler",
-        memmap[IBEX_ALERT_HANDLER].base, memmap[IBEX_ALERT_HANDLER].size);
+        memmap[IBEX_DEV_ALERT_HANDLER].base, memmap[IBEX_DEV_ALERT_HANDLER].size);
     create_unimplemented_device("riscv.lowrisc.ibex.nmi_gen",
-        memmap[IBEX_NMI_GEN].base, memmap[IBEX_NMI_GEN].size);
+        memmap[IBEX_DEV_NMI_GEN].base, memmap[IBEX_DEV_NMI_GEN].size);
     create_unimplemented_device("riscv.lowrisc.ibex.usbdev",
-        memmap[IBEX_USBDEV].base, memmap[IBEX_USBDEV].size);
+        memmap[IBEX_DEV_USBDEV].base, memmap[IBEX_DEV_USBDEV].size);
     create_unimplemented_device("riscv.lowrisc.ibex.padctrl",
-        memmap[IBEX_PADCTRL].base, memmap[IBEX_PADCTRL].size);
+        memmap[IBEX_DEV_PADCTRL].base, memmap[IBEX_DEV_PADCTRL].size);
 }
 
 static void lowrisc_ibex_soc_class_init(ObjectClass *oc, void *data)

Quoted 54 lines · Eduardo Habkost

Some of the enum constant names conflict with the QOM type check macros. This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE().

Rename all the constants to IBEX_DEV_*, to avoid conflicts.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/riscv/opentitan.h | 38 ++++++++--------
 hw/riscv/opentitan.c         | 84 ++++++++++++++++++------------------
 2 files changed, 61 insertions(+), 61 deletions(-)

include/hw/riscv/opentitan.h +14 -19

index 8f29b9cbbf..835a80f896 100644
@@ -49,25 +49,25 @@ typedef struct OpenTitanState {
 } OpenTitanState;
 
 enum {
-    IBEX_ROM,
-    IBEX_RAM,
-    IBEX_FLASH,
-    IBEX_UART,
-    IBEX_GPIO,
-    IBEX_SPI,
-    IBEX_FLASH_CTRL,
-    IBEX_RV_TIMER,
-    IBEX_AES,
-    IBEX_HMAC,
-    IBEX_PLIC,
-    IBEX_PWRMGR,
-    IBEX_RSTMGR,
-    IBEX_CLKMGR,
-    IBEX_PINMUX,
-    IBEX_ALERT_HANDLER,
-    IBEX_NMI_GEN,
-    IBEX_USBDEV,
-    IBEX_PADCTRL,
+    IBEX_DEV_ROM,
+    IBEX_DEV_RAM,
+    IBEX_DEV_FLASH,
+    IBEX_DEV_UART,
+    IBEX_DEV_GPIO,
+    IBEX_DEV_SPI,
+    IBEX_DEV_FLASH_CTRL,
+    IBEX_DEV_RV_TIMER,
+    IBEX_DEV_AES,
+    IBEX_DEV_HMAC,
+    IBEX_DEV_PLIC,
+    IBEX_DEV_PWRMGR,
+    IBEX_DEV_RSTMGR,
+    IBEX_DEV_CLKMGR,

include/hw/riscv/opentitan.h typedef struct OpenTitanState { · line 70

Quoted 5 lines

include/hw/riscv/opentitan.h +5 -0

+    IBEX_DEV_PINMUX,
+    IBEX_DEV_ALERT_HANDLER,
+    IBEX_DEV_NMI_GEN,
+    IBEX_DEV_USBDEV,
+    IBEX_DEV_PADCTRL,

Similarly, why is this enum in a public header and not local to opentitan.c, only place where it is used?

Quoted 56 lines · Philippe Mathieu-Daudé

Quoted 54 lines · Eduardo Habkost

Some of the enum constant names conflict with the QOM type check macros. This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE().

Rename all the constants to IBEX_DEV_*, to avoid conflicts.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/riscv/opentitan.h | 38 ++++++++--------
 hw/riscv/opentitan.c         | 84 ++++++++++++++++++------------------
 2 files changed, 61 insertions(+), 61 deletions(-)

include/hw/riscv/opentitan.h +14 -19

index 8f29b9cbbf..835a80f896 100644
@@ -49,25 +49,25 @@ typedef struct OpenTitanState {
 } OpenTitanState;
 
 enum {
-    IBEX_ROM,
-    IBEX_RAM,
-    IBEX_FLASH,
-    IBEX_UART,
-    IBEX_GPIO,
-    IBEX_SPI,
-    IBEX_FLASH_CTRL,
-    IBEX_RV_TIMER,
-    IBEX_AES,
-    IBEX_HMAC,
-    IBEX_PLIC,
-    IBEX_PWRMGR,
-    IBEX_RSTMGR,
-    IBEX_CLKMGR,
-    IBEX_PINMUX,
-    IBEX_ALERT_HANDLER,
-    IBEX_NMI_GEN,
-    IBEX_USBDEV,
-    IBEX_PADCTRL,
+    IBEX_DEV_ROM,
+    IBEX_DEV_RAM,
+    IBEX_DEV_FLASH,
+    IBEX_DEV_UART,
+    IBEX_DEV_GPIO,
+    IBEX_DEV_SPI,
+    IBEX_DEV_FLASH_CTRL,
+    IBEX_DEV_RV_TIMER,
+    IBEX_DEV_AES,
+    IBEX_DEV_HMAC,
+    IBEX_DEV_PLIC,
+    IBEX_DEV_PWRMGR,
+    IBEX_DEV_RSTMGR,
+    IBEX_DEV_CLKMGR,

Quoted 9 lines

include/hw/riscv/opentitan.h typedef struct OpenTitanState { · line 70

Quoted 5 lines

include/hw/riscv/opentitan.h +5 -0

+    IBEX_DEV_PINMUX,
+    IBEX_DEV_ALERT_HANDLER,
+    IBEX_DEV_NMI_GEN,
+    IBEX_DEV_USBDEV,
+    IBEX_DEV_PADCTRL,

Similarly, why is this enum in a public header and not local to opentitan.c, only place where it is used?

I believe the reason is that opentitan.c implements both SoC and board stuff. These enums are helpful to define SoC peripherals hence technically another board that uses the same SoC may utilize these macros.

Unfortunately this is the case for all RISC-V boards so far. Should we clean this up, for example, splitting SoC and board codes into 2 files?

Regards,
Bin

Quoted 68 lines · Bin Meng

Quoted 56 lines · Philippe Mathieu-Daudé

Quoted 54 lines · Eduardo Habkost

Some of the enum constant names conflict with the QOM type check macros. This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE().

Rename all the constants to IBEX_DEV_*, to avoid conflicts.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/riscv/opentitan.h | 38 ++++++++--------
 hw/riscv/opentitan.c         | 84 ++++++++++++++++++------------------
 2 files changed, 61 insertions(+), 61 deletions(-)

include/hw/riscv/opentitan.h +14 -19

index 8f29b9cbbf..835a80f896 100644
@@ -49,25 +49,25 @@ typedef struct OpenTitanState {
 } OpenTitanState;
 
 enum {
-    IBEX_ROM,
-    IBEX_RAM,
-    IBEX_FLASH,
-    IBEX_UART,
-    IBEX_GPIO,
-    IBEX_SPI,
-    IBEX_FLASH_CTRL,
-    IBEX_RV_TIMER,
-    IBEX_AES,
-    IBEX_HMAC,
-    IBEX_PLIC,
-    IBEX_PWRMGR,
-    IBEX_RSTMGR,
-    IBEX_CLKMGR,
-    IBEX_PINMUX,
-    IBEX_ALERT_HANDLER,
-    IBEX_NMI_GEN,
-    IBEX_USBDEV,
-    IBEX_PADCTRL,
+    IBEX_DEV_ROM,
+    IBEX_DEV_RAM,
+    IBEX_DEV_FLASH,
+    IBEX_DEV_UART,
+    IBEX_DEV_GPIO,
+    IBEX_DEV_SPI,
+    IBEX_DEV_FLASH_CTRL,
+    IBEX_DEV_RV_TIMER,
+    IBEX_DEV_AES,
+    IBEX_DEV_HMAC,
+    IBEX_DEV_PLIC,
+    IBEX_DEV_PWRMGR,
+    IBEX_DEV_RSTMGR,
+    IBEX_DEV_CLKMGR,

Quoted 9 lines

include/hw/riscv/opentitan.h typedef struct OpenTitanState { · line 70

Quoted 5 lines

include/hw/riscv/opentitan.h +5 -0

+    IBEX_DEV_PINMUX,
+    IBEX_DEV_ALERT_HANDLER,
+    IBEX_DEV_NMI_GEN,
+    IBEX_DEV_USBDEV,
+    IBEX_DEV_PADCTRL,

Similarly, why is this enum in a public header and not local to opentitan.c, only place where it is used?

Quoted 8 lines

I believe the reason is that opentitan.c implements both SoC and board stuff. These enums are helpful to define SoC peripherals hence technically another board that uses the same SoC may utilize these macros.

Unfortunately this is the case for all RISC-V boards so far. Should we clean this up, for example, splitting SoC and board codes into 2 files?

Yeah the hw/riscv directory is a bit of a mess. We need to look at moving non machine parts out (like sifive_uart for example) and then it's probably worth splitting SoC and machine. It does result in some extra files (some of which are very simple) but the current setup is pretty confusing.

Are you volunteering Bin? Otherwise I can look at it.

Some of the enum constant names conflict with the QOM type check macros. This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE().

Rename all the constants to SIFIVE_E_DEV_*, to avoid conflicts.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/riscv/sifive_e.h | 38 ++++++++---------
 hw/riscv/sifive_e.c         | 82 ++++++++++++++++++-------------------
 2 files changed, 60 insertions(+), 60 deletions(-)

include/hw/riscv/sifive_e.h +19 -19

index 637414130b..7c2eb70189 100644
@@ -53,25 +53,25 @@ typedef struct SiFiveEState {
     OBJECT_CHECK(SiFiveEState, (obj), TYPE_RISCV_E_MACHINE)
 
 enum {
-    SIFIVE_E_DEBUG,
-    SIFIVE_E_MROM,
-    SIFIVE_E_OTP,
-    SIFIVE_E_CLINT,
-    SIFIVE_E_PLIC,
-    SIFIVE_E_AON,
-    SIFIVE_E_PRCI,
-    SIFIVE_E_OTP_CTRL,
-    SIFIVE_E_GPIO0,
-    SIFIVE_E_UART0,
-    SIFIVE_E_QSPI0,
-    SIFIVE_E_PWM0,
-    SIFIVE_E_UART1,
-    SIFIVE_E_QSPI1,
-    SIFIVE_E_PWM1,
-    SIFIVE_E_QSPI2,
-    SIFIVE_E_PWM2,
-    SIFIVE_E_XIP,
-    SIFIVE_E_DTIM
+    SIFIVE_E_DEV_DEBUG,
+    SIFIVE_E_DEV_MROM,
+    SIFIVE_E_DEV_OTP,
+    SIFIVE_E_DEV_CLINT,
+    SIFIVE_E_DEV_PLIC,
+    SIFIVE_E_DEV_AON,
+    SIFIVE_E_DEV_PRCI,
+    SIFIVE_E_DEV_OTP_CTRL,
+    SIFIVE_E_DEV_GPIO0,
+    SIFIVE_E_DEV_UART0,
+    SIFIVE_E_DEV_QSPI0,
+    SIFIVE_E_DEV_PWM0,
+    SIFIVE_E_DEV_UART1,
+    SIFIVE_E_DEV_QSPI1,
+    SIFIVE_E_DEV_PWM1,
+    SIFIVE_E_DEV_QSPI2,
+    SIFIVE_E_DEV_PWM2,
+    SIFIVE_E_DEV_XIP,
+    SIFIVE_E_DEV_DTIM
 };
 
 enum {

hw/riscv/sifive_e.c +41 -42

index c8b060486a..88b4524117 100644
@@ -54,25 +54,25 @@ static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
 } sifive_e_memmap[] = {
-    [SIFIVE_E_DEBUG] =    {        0x0,     0x1000 },
-    [SIFIVE_E_MROM] =     {     0x1000,     0x2000 },
-    [SIFIVE_E_OTP] =      {    0x20000,     0x2000 },
-    [SIFIVE_E_CLINT] =    {  0x2000000,    0x10000 },
-    [SIFIVE_E_PLIC] =     {  0xc000000,  0x4000000 },
-    [SIFIVE_E_AON] =      { 0x10000000,     0x8000 },
-    [SIFIVE_E_PRCI] =     { 0x10008000,     0x8000 },
-    [SIFIVE_E_OTP_CTRL] = { 0x10010000,     0x1000 },
-    [SIFIVE_E_GPIO0] =    { 0x10012000,     0x1000 },
-    [SIFIVE_E_UART0] =    { 0x10013000,     0x1000 },
-    [SIFIVE_E_QSPI0] =    { 0x10014000,     0x1000 },
-    [SIFIVE_E_PWM0] =     { 0x10015000,     0x1000 },
-    [SIFIVE_E_UART1] =    { 0x10023000,     0x1000 },
-    [SIFIVE_E_QSPI1] =    { 0x10024000,     0x1000 },
-    [SIFIVE_E_PWM1] =     { 0x10025000,     0x1000 },
-    [SIFIVE_E_QSPI2] =    { 0x10034000,     0x1000 },
-    [SIFIVE_E_PWM2] =     { 0x10035000,     0x1000 },
-    [SIFIVE_E_XIP] =      { 0x20000000, 0x20000000 },
-    [SIFIVE_E_DTIM] =     { 0x80000000,     0x4000 }
+    [SIFIVE_E_DEV_DEBUG] =    {        0x0,     0x1000 },
+    [SIFIVE_E_DEV_MROM] =     {     0x1000,     0x2000 },
+    [SIFIVE_E_DEV_OTP] =      {    0x20000,     0x2000 },
+    [SIFIVE_E_DEV_CLINT] =    {  0x2000000,    0x10000 },
+    [SIFIVE_E_DEV_PLIC] =     {  0xc000000,  0x4000000 },
+    [SIFIVE_E_DEV_AON] =      { 0x10000000,     0x8000 },
+    [SIFIVE_E_DEV_PRCI] =     { 0x10008000,     0x8000 },
+    [SIFIVE_E_DEV_OTP_CTRL] = { 0x10010000,     0x1000 },
+    [SIFIVE_E_DEV_GPIO0] =    { 0x10012000,     0x1000 },
+    [SIFIVE_E_DEV_UART0] =    { 0x10013000,     0x1000 },
+    [SIFIVE_E_DEV_QSPI0] =    { 0x10014000,     0x1000 },
+    [SIFIVE_E_DEV_PWM0] =     { 0x10015000,     0x1000 },
+    [SIFIVE_E_DEV_UART1] =    { 0x10023000,     0x1000 },
+    [SIFIVE_E_DEV_QSPI1] =    { 0x10024000,     0x1000 },
+    [SIFIVE_E_DEV_PWM1] =     { 0x10025000,     0x1000 },
+    [SIFIVE_E_DEV_QSPI2] =    { 0x10034000,     0x1000 },
+    [SIFIVE_E_DEV_PWM2] =     { 0x10035000,     0x1000 },
+    [SIFIVE_E_DEV_XIP] =      { 0x20000000, 0x20000000 },
+    [SIFIVE_E_DEV_DTIM] =     { 0x80000000,     0x4000 }
 };
 
 static void sifive_e_machine_init(MachineState *machine)

@@ -90,9 +90,9 @@ static void sifive_e_machine_init(MachineState *machine)
 
     /* Data Tightly Integrated Memory */
     memory_region_init_ram(main_mem, NULL, "riscv.sifive.e.ram",
-        memmap[SIFIVE_E_DTIM].size, &error_fatal);
+        memmap[SIFIVE_E_DEV_DTIM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
-        memmap[SIFIVE_E_DTIM].base, main_mem);
+        memmap[SIFIVE_E_DEV_DTIM].base, main_mem);
 
     /* Mask ROM reset vector */
     uint32_t reset_vec[4];

@@ -111,7 +111,7 @@ static void sifive_e_machine_init(MachineState *machine)
         reset_vec[i] = cpu_to_le32(reset_vec[i]);
     }
     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
-                          memmap[SIFIVE_E_MROM].base, &address_space_memory);
+                          memmap[SIFIVE_E_DEV_MROM].base, &address_space_memory);
 
     if (machine->kernel_filename) {
         riscv_load_kernel(machine->kernel_filename, NULL);

@@ -194,12 +194,12 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
 
     /* Mask ROM */
     memory_region_init_rom(&s->mask_rom, OBJECT(dev), "riscv.sifive.e.mrom",
-                           memmap[SIFIVE_E_MROM].size, &error_fatal);
+                           memmap[SIFIVE_E_DEV_MROM].size, &error_fatal);
     memory_region_add_subregion(sys_mem,
-        memmap[SIFIVE_E_MROM].base, &s->mask_rom);
+        memmap[SIFIVE_E_DEV_MROM].base, &s->mask_rom);
 
     /* MMIO */
-    s->plic = sifive_plic_create(memmap[SIFIVE_E_PLIC].base,
+    s->plic = sifive_plic_create(memmap[SIFIVE_E_DEV_PLIC].base,
         (char *)SIFIVE_E_PLIC_HART_CONFIG,
         SIFIVE_E_PLIC_NUM_SOURCES,
         SIFIVE_E_PLIC_NUM_PRIORITIES,

@@ -209,13 +209,13 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_E_PLIC_ENABLE_STRIDE,
         SIFIVE_E_PLIC_CONTEXT_BASE,
         SIFIVE_E_PLIC_CONTEXT_STRIDE,
-        memmap[SIFIVE_E_PLIC].size);
-    sifive_clint_create(memmap[SIFIVE_E_CLINT].base,
-        memmap[SIFIVE_E_CLINT].size, ms->smp.cpus,
+        memmap[SIFIVE_E_DEV_PLIC].size);
+    sifive_clint_create(memmap[SIFIVE_E_DEV_CLINT].base,
+        memmap[SIFIVE_E_DEV_CLINT].size, ms->smp.cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
     create_unimplemented_device("riscv.sifive.e.aon",
-        memmap[SIFIVE_E_AON].base, memmap[SIFIVE_E_AON].size);
-    sifive_e_prci_create(memmap[SIFIVE_E_PRCI].base);
+        memmap[SIFIVE_E_DEV_AON].base, memmap[SIFIVE_E_DEV_AON].size);
+    sifive_e_prci_create(memmap[SIFIVE_E_DEV_PRCI].base);
 
     /* GPIO */
 

@@ -224,7 +224,7 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
     }
 
     /* Map GPIO registers */
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_GPIO0].base);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_E_DEV_GPIO0].base);
 
     /* Pass all GPIOs to the SOC layer so they are available to the board */
     qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);

@@ -236,27 +236,27 @@ static void sifive_e_soc_realize(DeviceState *dev, Error **errp)
                                             SIFIVE_E_GPIO0_IRQ0 + i));
     }
 
-    sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART0].base,
+    sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART0].base,
         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART0_IRQ));
     create_unimplemented_device("riscv.sifive.e.qspi0",
-        memmap[SIFIVE_E_QSPI0].base, memmap[SIFIVE_E_QSPI0].size);
+        memmap[SIFIVE_E_DEV_QSPI0].base, memmap[SIFIVE_E_DEV_QSPI0].size);
     create_unimplemented_device("riscv.sifive.e.pwm0",
-        memmap[SIFIVE_E_PWM0].base, memmap[SIFIVE_E_PWM0].size);
-    sifive_uart_create(sys_mem, memmap[SIFIVE_E_UART1].base,
+        memmap[SIFIVE_E_DEV_PWM0].base, memmap[SIFIVE_E_DEV_PWM0].size);
+    sifive_uart_create(sys_mem, memmap[SIFIVE_E_DEV_UART1].base,
         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_E_UART1_IRQ));
     create_unimplemented_device("riscv.sifive.e.qspi1",
-        memmap[SIFIVE_E_QSPI1].base, memmap[SIFIVE_E_QSPI1].size);
+        memmap[SIFIVE_E_DEV_QSPI1].base, memmap[SIFIVE_E_DEV_QSPI1].size);
     create_unimplemented_device("riscv.sifive.e.pwm1",
-        memmap[SIFIVE_E_PWM1].base, memmap[SIFIVE_E_PWM1].size);
+        memmap[SIFIVE_E_DEV_PWM1].base, memmap[SIFIVE_E_DEV_PWM1].size);
     create_unimplemented_device("riscv.sifive.e.qspi2",
-        memmap[SIFIVE_E_QSPI2].base, memmap[SIFIVE_E_QSPI2].size);
+        memmap[SIFIVE_E_DEV_QSPI2].base, memmap[SIFIVE_E_DEV_QSPI2].size);
     create_unimplemented_device("riscv.sifive.e.pwm2",
-        memmap[SIFIVE_E_PWM2].base, memmap[SIFIVE_E_PWM2].size);
+        memmap[SIFIVE_E_DEV_PWM2].base, memmap[SIFIVE_E_DEV_PWM2].size);
 
     /* Flash memory */
     memory_region_init_rom(&s->xip_mem, OBJECT(dev), "riscv.sifive.e.xip",
-                           memmap[SIFIVE_E_XIP].size, &error_fatal);
-    memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_XIP].base,
+                           memmap[SIFIVE_E_DEV_XIP].size, &error_fatal);
+    memory_region_add_subregion(sys_mem, memmap[SIFIVE_E_DEV_XIP].base,
         &s->xip_mem);
 }
 
--

2.26.2

Some of the enum constant names conflict with the QOM type check macros. This needs to be addressed to allow us to transform the QOM type check macros into functions generated by OBJECT_DECLARE_TYPE().

Rename all the constants to SIFIVE_U_DEV_*, to avoid conflicts.

Signed-off-by Eduardo Habkost <[email protected]>

---
 include/hw/riscv/sifive_u.h |  30 ++++----
 hw/riscv/sifive_u.c         | 136 ++++++++++++++++++------------------
 2 files changed, 83 insertions(+), 83 deletions(-)

include/hw/riscv/sifive_u.h +15 -15

index aba4d0181f..0dab922f3a 100644
@@ -68,21 +68,21 @@ typedef struct SiFiveUState {
 } SiFiveUState;
 
 enum {
-    SIFIVE_U_DEBUG,
-    SIFIVE_U_MROM,
-    SIFIVE_U_CLINT,
-    SIFIVE_U_L2LIM,
-    SIFIVE_U_PLIC,
-    SIFIVE_U_PRCI,
-    SIFIVE_U_UART0,
-    SIFIVE_U_UART1,
-    SIFIVE_U_GPIO,
-    SIFIVE_U_OTP,
-    SIFIVE_U_DMC,
-    SIFIVE_U_FLASH0,
-    SIFIVE_U_DRAM,
-    SIFIVE_U_GEM,
-    SIFIVE_U_GEM_MGMT
+    SIFIVE_U_DEV_DEBUG,
+    SIFIVE_U_DEV_MROM,
+    SIFIVE_U_DEV_CLINT,
+    SIFIVE_U_DEV_L2LIM,
+    SIFIVE_U_DEV_PLIC,
+    SIFIVE_U_DEV_PRCI,
+    SIFIVE_U_DEV_UART0,
+    SIFIVE_U_DEV_UART1,
+    SIFIVE_U_DEV_GPIO,
+    SIFIVE_U_DEV_OTP,
+    SIFIVE_U_DEV_DMC,
+    SIFIVE_U_DEV_FLASH0,
+    SIFIVE_U_DEV_DRAM,
+    SIFIVE_U_DEV_GEM,
+    SIFIVE_U_DEV_GEM_MGMT
 };
 
 enum {

hw/riscv/sifive_u.c +68 -69

index e5682c38a9..0dfbcb5160 100644
@@ -69,21 +69,21 @@ static const struct MemmapEntry {
     hwaddr base;
     hwaddr size;
 } sifive_u_memmap[] = {
-    [SIFIVE_U_DEBUG] =    {        0x0,      0x100 },
-    [SIFIVE_U_MROM] =     {     0x1000,     0xf000 },
-    [SIFIVE_U_CLINT] =    {  0x2000000,    0x10000 },
-    [SIFIVE_U_L2LIM] =    {  0x8000000,  0x2000000 },
-    [SIFIVE_U_PLIC] =     {  0xc000000,  0x4000000 },
-    [SIFIVE_U_PRCI] =     { 0x10000000,     0x1000 },
-    [SIFIVE_U_UART0] =    { 0x10010000,     0x1000 },
-    [SIFIVE_U_UART1] =    { 0x10011000,     0x1000 },
-    [SIFIVE_U_GPIO] =     { 0x10060000,     0x1000 },
-    [SIFIVE_U_OTP] =      { 0x10070000,     0x1000 },
-    [SIFIVE_U_GEM] =      { 0x10090000,     0x2000 },
-    [SIFIVE_U_GEM_MGMT] = { 0x100a0000,     0x1000 },
-    [SIFIVE_U_DMC] =      { 0x100b0000,    0x10000 },
-    [SIFIVE_U_FLASH0] =   { 0x20000000, 0x10000000 },
-    [SIFIVE_U_DRAM] =     { 0x80000000,        0x0 },
+    [SIFIVE_U_DEV_DEBUG] =    {        0x0,      0x100 },
+    [SIFIVE_U_DEV_MROM] =     {     0x1000,     0xf000 },
+    [SIFIVE_U_DEV_CLINT] =    {  0x2000000,    0x10000 },
+    [SIFIVE_U_DEV_L2LIM] =    {  0x8000000,  0x2000000 },
+    [SIFIVE_U_DEV_PLIC] =     {  0xc000000,  0x4000000 },
+    [SIFIVE_U_DEV_PRCI] =     { 0x10000000,     0x1000 },
+    [SIFIVE_U_DEV_UART0] =    { 0x10010000,     0x1000 },
+    [SIFIVE_U_DEV_UART1] =    { 0x10011000,     0x1000 },
+    [SIFIVE_U_DEV_GPIO] =     { 0x10060000,     0x1000 },
+    [SIFIVE_U_DEV_OTP] =      { 0x10070000,     0x1000 },
+    [SIFIVE_U_DEV_GEM] =      { 0x10090000,     0x2000 },
+    [SIFIVE_U_DEV_GEM_MGMT] = { 0x100a0000,     0x1000 },
+    [SIFIVE_U_DEV_DMC] =      { 0x100b0000,    0x10000 },
+    [SIFIVE_U_DEV_FLASH0] =   { 0x20000000, 0x10000000 },
+    [SIFIVE_U_DEV_DRAM] =     { 0x80000000,        0x0 },
 };
 
 #define OTP_SERIAL          1

@@ -142,10 +142,10 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     g_free(nodename);
 
     nodename = g_strdup_printf("/memory@%lx",
-        (long)memmap[SIFIVE_U_DRAM].base);
+        (long)memmap[SIFIVE_U_DEV_DRAM].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        memmap[SIFIVE_U_DRAM].base >> 32, memmap[SIFIVE_U_DRAM].base,
+        memmap[SIFIVE_U_DEV_DRAM].base >> 32, memmap[SIFIVE_U_DEV_DRAM].base,
         mem_size >> 32, mem_size);
     qemu_fdt_setprop_string(fdt, nodename, "device_type", "memory");
     g_free(nodename);

@@ -200,39 +200,39 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
         g_free(nodename);
     }
     nodename = g_strdup_printf("/soc/clint@%lx",
-        (long)memmap[SIFIVE_U_CLINT].base);
+        (long)memmap[SIFIVE_U_DEV_CLINT].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,clint0");
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        0x0, memmap[SIFIVE_U_CLINT].base,
-        0x0, memmap[SIFIVE_U_CLINT].size);
+        0x0, memmap[SIFIVE_U_DEV_CLINT].base,
+        0x0, memmap[SIFIVE_U_DEV_CLINT].size);
     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
         cells, ms->smp.cpus * sizeof(uint32_t) * 4);
     g_free(cells);
     g_free(nodename);
 
     nodename = g_strdup_printf("/soc/otp@%lx",
-        (long)memmap[SIFIVE_U_OTP].base);
+        (long)memmap[SIFIVE_U_DEV_OTP].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_cell(fdt, nodename, "fuse-count", SIFIVE_U_OTP_REG_SIZE);
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        0x0, memmap[SIFIVE_U_OTP].base,
-        0x0, memmap[SIFIVE_U_OTP].size);
+        0x0, memmap[SIFIVE_U_DEV_OTP].base,
+        0x0, memmap[SIFIVE_U_DEV_OTP].size);
     qemu_fdt_setprop_string(fdt, nodename, "compatible",
         "sifive,fu540-c000-otp");
     g_free(nodename);
 
     prci_phandle = phandle++;
     nodename = g_strdup_printf("/soc/clock-controller@%lx",
-        (long)memmap[SIFIVE_U_PRCI].base);
+        (long)memmap[SIFIVE_U_DEV_PRCI].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_cell(fdt, nodename, "phandle", prci_phandle);
     qemu_fdt_setprop_cell(fdt, nodename, "#clock-cells", 0x1);
     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
         hfclk_phandle, rtcclk_phandle);
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        0x0, memmap[SIFIVE_U_PRCI].base,
-        0x0, memmap[SIFIVE_U_PRCI].size);
+        0x0, memmap[SIFIVE_U_DEV_PRCI].base,
+        0x0, memmap[SIFIVE_U_DEV_PRCI].size);
     qemu_fdt_setprop_string(fdt, nodename, "compatible",
         "sifive,fu540-c000-prci");
     g_free(nodename);

@@ -256,7 +256,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
         g_free(nodename);
     }
     nodename = g_strdup_printf("/soc/interrupt-controller@%lx",
-        (long)memmap[SIFIVE_U_PLIC].base);
+        (long)memmap[SIFIVE_U_DEV_PLIC].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_cell(fdt, nodename, "#interrupt-cells", 1);
     qemu_fdt_setprop_string(fdt, nodename, "compatible", "riscv,plic0");

@@ -264,8 +264,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop(fdt, nodename, "interrupts-extended",
         cells, (ms->smp.cpus * 4 - 2) * sizeof(uint32_t));
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        0x0, memmap[SIFIVE_U_PLIC].base,
-        0x0, memmap[SIFIVE_U_PLIC].size);
+        0x0, memmap[SIFIVE_U_DEV_PLIC].base,
+        0x0, memmap[SIFIVE_U_DEV_PLIC].size);
     qemu_fdt_setprop_cell(fdt, nodename, "riscv,ndev", 0x35);
     qemu_fdt_setprop_cell(fdt, nodename, "phandle", plic_phandle);
     plic_phandle = qemu_fdt_get_phandle(fdt, nodename);

@@ -274,7 +274,7 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
 
     gpio_phandle = phandle++;
     nodename = g_strdup_printf("/soc/gpio@%lx",
-        (long)memmap[SIFIVE_U_GPIO].base);
+        (long)memmap[SIFIVE_U_DEV_GPIO].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_cell(fdt, nodename, "phandle", gpio_phandle);
     qemu_fdt_setprop_cells(fdt, nodename, "clocks",

@@ -284,8 +284,8 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     qemu_fdt_setprop_cell(fdt, nodename, "#gpio-cells", 2);
     qemu_fdt_setprop(fdt, nodename, "gpio-controller", NULL, 0);
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        0x0, memmap[SIFIVE_U_GPIO].base,
-        0x0, memmap[SIFIVE_U_GPIO].size);
+        0x0, memmap[SIFIVE_U_DEV_GPIO].base,
+        0x0, memmap[SIFIVE_U_DEV_GPIO].size);
     qemu_fdt_setprop_cells(fdt, nodename, "interrupts", SIFIVE_U_GPIO_IRQ0,
         SIFIVE_U_GPIO_IRQ1, SIFIVE_U_GPIO_IRQ2, SIFIVE_U_GPIO_IRQ3,
         SIFIVE_U_GPIO_IRQ4, SIFIVE_U_GPIO_IRQ5, SIFIVE_U_GPIO_IRQ6,

@@ -304,15 +304,15 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
 
     phy_phandle = phandle++;
     nodename = g_strdup_printf("/soc/ethernet@%lx",
-        (long)memmap[SIFIVE_U_GEM].base);
+        (long)memmap[SIFIVE_U_DEV_GEM].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_string(fdt, nodename, "compatible",
         "sifive,fu540-c000-gem");
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        0x0, memmap[SIFIVE_U_GEM].base,
-        0x0, memmap[SIFIVE_U_GEM].size,
-        0x0, memmap[SIFIVE_U_GEM_MGMT].base,
-        0x0, memmap[SIFIVE_U_GEM_MGMT].size);
+        0x0, memmap[SIFIVE_U_DEV_GEM].base,
+        0x0, memmap[SIFIVE_U_DEV_GEM].size,
+        0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].base,
+        0x0, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
     qemu_fdt_setprop_string(fdt, nodename, "reg-names", "control");
     qemu_fdt_setprop_string(fdt, nodename, "phy-mode", "gmii");
     qemu_fdt_setprop_cell(fdt, nodename, "phy-handle", phy_phandle);

@@ -333,19 +333,19 @@ static void create_fdt(SiFiveUState *s, const struct MemmapEntry *memmap,
     g_free(nodename);
 
     nodename = g_strdup_printf("/soc/ethernet@%lx/ethernet-phy@0",
-        (long)memmap[SIFIVE_U_GEM].base);
+        (long)memmap[SIFIVE_U_DEV_GEM].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_cell(fdt, nodename, "phandle", phy_phandle);
     qemu_fdt_setprop_cell(fdt, nodename, "reg", 0x0);
     g_free(nodename);
 
     nodename = g_strdup_printf("/soc/serial@%lx",
-        (long)memmap[SIFIVE_U_UART0].base);
+        (long)memmap[SIFIVE_U_DEV_UART0].base);
     qemu_fdt_add_subnode(fdt, nodename);
     qemu_fdt_setprop_string(fdt, nodename, "compatible", "sifive,uart0");
     qemu_fdt_setprop_cells(fdt, nodename, "reg",
-        0x0, memmap[SIFIVE_U_UART0].base,
-        0x0, memmap[SIFIVE_U_UART0].size);
+        0x0, memmap[SIFIVE_U_DEV_UART0].base,
+        0x0, memmap[SIFIVE_U_DEV_UART0].size);
     qemu_fdt_setprop_cells(fdt, nodename, "clocks",
         prci_phandle, PRCI_CLK_TLCLK);
     qemu_fdt_setprop_cell(fdt, nodename, "interrupt-parent", plic_phandle);

@@ -377,7 +377,7 @@ static void sifive_u_machine_init(MachineState *machine)
     MemoryRegion *system_memory = get_system_memory();
     MemoryRegion *main_mem = g_new(MemoryRegion, 1);
     MemoryRegion *flash0 = g_new(MemoryRegion, 1);
-    target_ulong start_addr = memmap[SIFIVE_U_DRAM].base;
+    target_ulong start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
     uint32_t start_addr_hi32 = 0x00000000;
     int i;
     uint32_t fdt_load_addr;

@@ -392,13 +392,13 @@ static void sifive_u_machine_init(MachineState *machine)
     /* register RAM */
     memory_region_init_ram(main_mem, NULL, "riscv.sifive.u.ram",
                            machine->ram_size, &error_fatal);
-    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DRAM].base,
+    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_DRAM].base,
                                 main_mem);
 
     /* register QSPI0 Flash */
     memory_region_init_ram(flash0, NULL, "riscv.sifive.u.flash0",
-                           memmap[SIFIVE_U_FLASH0].size, &error_fatal);
-    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_FLASH0].base,
+                           memmap[SIFIVE_U_DEV_FLASH0].size, &error_fatal);
+    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_FLASH0].base,
                                 flash0);
 
     /* register gpio-restart */

@@ -424,14 +424,14 @@ static void sifive_u_machine_init(MachineState *machine)
 
     switch (s->msel) {
     case MSEL_MEMMAP_QSPI0_FLASH:
-        start_addr = memmap[SIFIVE_U_FLASH0].base;
+        start_addr = memmap[SIFIVE_U_DEV_FLASH0].base;
         break;
     case MSEL_L2LIM_QSPI0_FLASH:
     case MSEL_L2LIM_QSPI2_SD:
-        start_addr = memmap[SIFIVE_U_L2LIM].base;
+        start_addr = memmap[SIFIVE_U_DEV_L2LIM].base;
         break;
     default:
-        start_addr = memmap[SIFIVE_U_DRAM].base;
+        start_addr = memmap[SIFIVE_U_DEV_DRAM].base;
         break;
     }
 

@@ -459,7 +459,7 @@ static void sifive_u_machine_init(MachineState *machine)
     }
 
     /* Compute the fdt load address in dram */
-    fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DRAM].base,
+    fdt_load_addr = riscv_load_fdt(memmap[SIFIVE_U_DEV_DRAM].base,
                                    machine->ram_size, s->fdt);
     #if defined(TARGET_RISCV64)
     start_addr_hi32 = start_addr >> 32;

@@ -491,10 +491,10 @@ static void sifive_u_machine_init(MachineState *machine)
         reset_vec[i] = cpu_to_le32(reset_vec[i]);
     }
     rom_add_blob_fixed_as("mrom.reset", reset_vec, sizeof(reset_vec),
-                          memmap[SIFIVE_U_MROM].base, &address_space_memory);
+                          memmap[SIFIVE_U_DEV_MROM].base, &address_space_memory);
 
-    riscv_rom_copy_firmware_info(memmap[SIFIVE_U_MROM].base,
-                                 memmap[SIFIVE_U_MROM].size,
+    riscv_rom_copy_firmware_info(memmap[SIFIVE_U_DEV_MROM].base,
+                                 memmap[SIFIVE_U_DEV_MROM].size,
                                  sizeof(reset_vec), kernel_entry);
 }
 

@@ -634,8 +634,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
 
     /* boot rom */
     memory_region_init_rom(mask_rom, OBJECT(dev), "riscv.sifive.u.mrom",
-                           memmap[SIFIVE_U_MROM].size, &error_fatal);
-    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_MROM].base,
+                           memmap[SIFIVE_U_DEV_MROM].size, &error_fatal);
+    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_MROM].base,
                                 mask_rom);
 
     /*

@@ -648,8 +648,8 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
      * too generous to misbehaving guests.
      */
     memory_region_init_ram(l2lim_mem, NULL, "riscv.sifive.u.l2lim",
-                           memmap[SIFIVE_U_L2LIM].size, &error_fatal);
-    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_L2LIM].base,
+                           memmap[SIFIVE_U_DEV_L2LIM].size, &error_fatal);
+    memory_region_add_subregion(system_memory, memmap[SIFIVE_U_DEV_L2LIM].base,
                                 l2lim_mem);
 
     /* create PLIC hart topology configuration string */

@@ -667,7 +667,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
     }
 
     /* MMIO */
-    s->plic = sifive_plic_create(memmap[SIFIVE_U_PLIC].base,
+    s->plic = sifive_plic_create(memmap[SIFIVE_U_DEV_PLIC].base,
         plic_hart_config,
         SIFIVE_U_PLIC_NUM_SOURCES,
         SIFIVE_U_PLIC_NUM_PRIORITIES,

@@ -677,26 +677,26 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
         SIFIVE_U_PLIC_ENABLE_STRIDE,
         SIFIVE_U_PLIC_CONTEXT_BASE,
         SIFIVE_U_PLIC_CONTEXT_STRIDE,
-        memmap[SIFIVE_U_PLIC].size);
+        memmap[SIFIVE_U_DEV_PLIC].size);
     g_free(plic_hart_config);
-    sifive_uart_create(system_memory, memmap[SIFIVE_U_UART0].base,
+    sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART0].base,
         serial_hd(0), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART0_IRQ));
-    sifive_uart_create(system_memory, memmap[SIFIVE_U_UART1].base,
+    sifive_uart_create(system_memory, memmap[SIFIVE_U_DEV_UART1].base,
         serial_hd(1), qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_UART1_IRQ));
-    sifive_clint_create(memmap[SIFIVE_U_CLINT].base,
-        memmap[SIFIVE_U_CLINT].size, ms->smp.cpus,
+    sifive_clint_create(memmap[SIFIVE_U_DEV_CLINT].base,
+        memmap[SIFIVE_U_DEV_CLINT].size, ms->smp.cpus,
         SIFIVE_SIP_BASE, SIFIVE_TIMECMP_BASE, SIFIVE_TIME_BASE, false);
 
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->prci), errp)) {
         return;
     }
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_PRCI].base);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->prci), 0, memmap[SIFIVE_U_DEV_PRCI].base);
 
     qdev_prop_set_uint32(DEVICE(&s->gpio), "ngpio", 16);
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gpio), errp)) {
         return;
     }
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_GPIO].base);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gpio), 0, memmap[SIFIVE_U_DEV_GPIO].base);
 
     /* Pass all GPIOs to the SOC layer so they are available to the board */
     qdev_pass_gpios(DEVICE(&s->gpio), dev, NULL);

@@ -712,7 +712,7 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->otp), errp)) {
         return;
     }
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_OTP].base);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->otp), 0, memmap[SIFIVE_U_DEV_OTP].base);
 
     /* FIXME use qdev NIC properties instead of nd_table[] */
     if (nd->used) {

@@ -724,15 +724,15 @@ static void sifive_u_soc_realize(DeviceState *dev, Error **errp)
     if (!sysbus_realize(SYS_BUS_DEVICE(&s->gem), errp)) {
         return;
     }
-    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_GEM].base);
+    sysbus_mmio_map(SYS_BUS_DEVICE(&s->gem), 0, memmap[SIFIVE_U_DEV_GEM].base);
     sysbus_connect_irq(SYS_BUS_DEVICE(&s->gem), 0,
                        qdev_get_gpio_in(DEVICE(s->plic), SIFIVE_U_GEM_IRQ));
 
     create_unimplemented_device("riscv.sifive.u.gem-mgmt",
-        memmap[SIFIVE_U_GEM_MGMT].base, memmap[SIFIVE_U_GEM_MGMT].size);
+        memmap[SIFIVE_U_DEV_GEM_MGMT].base, memmap[SIFIVE_U_DEV_GEM_MGMT].size);
 
     create_unimplemented_device("riscv.sifive.u.dmc",
-        memmap[SIFIVE_U_DMC].base, memmap[SIFIVE_U_DMC].size);
+        memmap[SIFIVE_U_DEV_DMC].base, memmap[SIFIVE_U_DEV_DMC].size);
 }
 
 static Property sifive_u_soc_props[] = {
--

2.26.2

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/pci-host/versatile.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

hw/pci-host/versatile.c +0 -0

index 616882a80d..7e4aa467a2 100644

hw/pci-host/versatile.c +0 -0

 typedef enum {
     PCI_IMAP0 = 0x0,
 

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/pci-host/versatile.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

The macro was incorrectly defined using OBJECT_CHECK.

Signed-off-by Eduardo Habkost <[email protected]>

---
 hw/s390x/virtio-ccw.h | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

hw/s390x/virtio-ccw.h +0 -0

index c0e3355248..b281896f7d 100644
@@ -65,9 +65,9 @@ typedef struct VirtioBusClass VirtioCcwBusClass;