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ACPI: Support Generic Initiator proximity domains

PATCH Superseded Jonathan Cameron 2 participants 18 messages Aug 19, 2020 – Aug 21, 2020

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v9 of 12 Superseded Latest is v12 →

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v9 cover ACPI: Support Generic Initiator proximity domains

It would be very nice to finally merge this support during this cycle, so please take a look.

I think we need acks covering x86, ARM and ACPI. Rafael took a look back in November at v5 and was looking for x86 and ARM acks. Whilst there is no ARM specific code left we probably still need an Ack.

Introduces a new type of NUMA node for cases where we want to represent the access characteristics of a non CPU initiator of memory requests, as these differ from all those for existing nodes containing CPUs and/or memory.

These Generic Initiators are presented by the node access0 class in
sysfs in the same way as a CPU. It seems likely that there will be
usecases in which the best 'CPU' is desired and Generic Initiators should be ignored. The final few patches in this series introduced access1 which is a new performance class in the sysfs node description which presents only CPU to memory relationships. Test cases for this are described below.

Changes since v8:
* ifdef protections and stubs to avoid a build error on ia64. I'm assuming no one cares about Generic Initiators on IA64 (0-day)
* Update OSC code to ensure we don't claim to support GIs except on x86 and ARM64

Changes since V7:

* Now independent from
[PATCH v3 0/6] ACPI: Only create NUMA nodes from entries in SRAT or SRAT emulation
* Minor documentation tweak.
* Rebase on v5.9-rc1

Changes since V6:

* Rebase on 5.8-rc4 + Dependency as above.
* Drop the ARM64 specific code. No specific calls are needed on ARM64 as the generic node init is done for all nodes, whether or not they have memory. X86 does memoryless nodes separately from those with memory and hence needs to specifically intialize GI only nodes.
* Fix up an error in the docs reported by Brice Goglin who also did quite a bit of testing of v5. Thanks!

Changes since V5:

3 new patches:
* A fix for a subtlety in how ACPI 6.3 changed part of the HMAT table.
* Introduction of access1 class to represent characteristics between CPU and memory, ingnoring GIs unlike access0 which includes them.
* Docs to describe the new access0 class.

Note that I ran a number of test cases for the new class which are described at the end of this email.

Changes since V4:

At Rafael's suggestion:

Rebase on top of Dan William's Specific Purpose Memory series as that moves srat.c Original patches cherry-picked fine onto mmotm with Dan's patches applied.

Applies to mmotm-2019-09-25 +
https://lore.kernel.org/linux-acpi/156140036490.2951909.1837804994781523185.stgit@dwillia2-desk3.amr.corp.intel.com/
[PATCH v4 00/10] EFI Specific Purpose Memory Support (note there are some trivial conflicts to deal with when applying the SPM series).

Change since V3.
* Rebase.

Changes since RFC V2.
* RFC dropped as now we have x86 support, so the lack of guards in in the ACPI code etc should now be fine.
* Added x86 support. Note this has only been tested on QEMU as I don't have a convenient x86 NUMA machine to play with. Note that this fitted together rather differently from arm64 so I'm particularly interested in feedback on the two solutions.

Since RFC V1.
* Fix incorrect interpretation of the ACPI entry noted by Keith Busch
* Use the acpica headers definitions that are now in mmotm.

It's worth noting that, to safely put a given device in a GI node, may require changes to the existing drivers as it's not unusual to assume you have local memory or processor core. There may be further constraints not yet covered by this patch.

Original cover letter...

ACPI 6.3 introduced a new entity that can be part of a NUMA proximity domain. It may share such a domain with the existing options (memory, CPU etc) but it may also exist on it's own.

The intent is to allow the description of the NUMA properties (particularly via HMAT) of accelerators and other initiators of memory activity that are not the host processor running the operating system.

This patch set introduces 'just enough' to make them work for arm64 and x86. It should be trivial to support other architectures, I just don't suitable NUMA systems readily available to test.

There are a few quirks that need to be considered.

1. Fall back nodes
******************

As pre ACPI 6.3 supporting operating systems do not have Generic Initiator Proximity Domains it is possible to specify, via _PXM in DSDT that another device is part of such a GI only node. This currently blows up spectacularly.

Whilst we can obviously 'now' protect against such a situation (see the related thread on PCI _PXM support and the threadripper board identified there as also falling into the problem of using non existent nodes
https://patchwork.kernel.org/patch/10723311/ ), there is no way to be sure we will never have legacy OSes that are not protected against this. It would also be 'non ideal' to fallback to a default node as there may be a better (non GI) node to pick if GI nodes aren't available.

The work around is that we also have a new system wide OSC bit that allows an operating system to 'announce' that it supports Generic Initiators. This allows, the firmware to us DSDT magic to 'move' devices between the nodes dependent on whether our new nodes are there or not.

2. New ways of assigning a proximity domain for devices
*******************************************************

Until now, the only way firmware could indicate that a particular device (outside the 'special' set of cpus etc) was to be found in a particular Proximity Domain by the use of _PXM in DSDT.

That is equally valid with GI domains, but we have new options. The SRAT affinity structure includes a handle (ACPI or PCI) to identify devices with the system and specify their proximity domain that way. If both _PXM and this are provided, they should give the same answer.

For now this patch set completely ignores that feature as we don't need it to start the discussion. It will form a follow up set at some point (if no one else fancies doing it).

Test cases for the access1 class
********************************

Test cases for Generic Initiator additions to HMAT.

Setup

PXM0 (node 0) - CPU0 CPU1, 2G memory
PXM1 (node 1) - CPU2 CPU3, 2G memory
PXM2 (node 2) - CPU4 CPU5, 2G memory
PXM3 (node 4) - 2G memory (GI in one case below)
PXM4 (node 3) - GI only.

Config 1: GI in PXM4 nearer to memory in PXM 3 than CPUs, not direct attached

[    2.384064] acpi/hmat: HMAT: Locality: Flags:00 Type:Access Latency Initiator Domains:4 Target Domains:4 Base:256
[    2.384913] acpi/hmat:   Initiator-Target[0-0]:1 nsec
[    2.385190] acpi/hmat:   Initiator-Target[0-1]:9 nsec
[    2.385736] acpi/hmat:   Initiator-Target[0-2]:9 nsec
[    2.385984] acpi/hmat:   Initiator-Target[0-3]:9 nsec
[    2.386447] acpi/hmat:   Initiator-Target[1-0]:9 nsec
[    2.386740] acpi/hmat:   Initiator-Target[1-1]:1 nsec
[    2.386964] acpi/hmat:   Initiator-Target[1-2]:9 nsec
[    2.387174] acpi/hmat:   Initiator-Target[1-3]:9 nsec
[    2.387624] acpi/hmat:   Initiator-Target[2-0]:9 nsec
[    2.387953] acpi/hmat:   Initiator-Target[2-1]:9 nsec
[    2.388155] acpi/hmat:   Initiator-Target[2-2]:1 nsec
[    2.388607] acpi/hmat:   Initiator-Target[2-3]:9 nsec
[    2.388861] acpi/hmat:   Initiator-Target[4-0]:13 nsec
[    2.389126] acpi/hmat:   Initiator-Target[4-1]:13 nsec
[    2.389574] acpi/hmat:   Initiator-Target[4-2]:13 nsec
[    2.389805] acpi/hmat:   Initiator-Target[4-3]:5 nsec

# Sysfs reads the same for nodes 0-2 for access0 and access1 as no GI involved.

/sys/bus/node/devices/...

    node0 #1 and 2 similar.
        access0
            initiators
                node0
                read_bandwidth  0 #not specificed in hmat
                read_latency    1
                write_bandwidth 0
                write_latency   1
            power
            targets
                node0
            uevent
        access1
            initiators
                node0
                read_bandwidth  0
                read_latency    1
                write_bandwidth 0
                read_bandwidth  1   
            power
            targets
                node 0
            uevent
        compact
        cpu0
        cpu1
        ...
    node3 # Note PXM 4, contains GI only
        access0
            initiators
                *empty*
            power
            targets
                node4
            uevent
        compact
        ...
    node4
        access0
            initiators
                node3
                read_bandwidth  0
                read_latency    5
                write_bandwidth 0
                write_latency   5
            power
            targets
                *empty*
            uevent
        access1
            initiators
                node0
                node1
                node2
                read_bandwidth  0
                read_latency    9
                write_bandwidth 0
                write_latency   9
            power
            targets
                *empty*
            uevent
        compact
        ...

Config 2: GI in PXM4 further to memory in PXM 3 than CPUs, not direct attached

[    4.073493] acpi/hmat: HMAT: Locality: Flags:00 Type:Access Latency Initiator Domains:4 Target Domains:4 Base:256
[    4.074785] acpi/hmat:   Initiator-Target[0-0]:1 nsec
[    4.075150] acpi/hmat:   Initiator-Target[0-1]:9 nsec
[    4.075423] acpi/hmat:   Initiator-Target[0-2]:9 nsec
[    4.076184] acpi/hmat:   Initiator-Target[0-3]:9 nsec
[    4.077116] acpi/hmat:   Initiator-Target[1-0]:9 nsec
[    4.077366] acpi/hmat:   Initiator-Target[1-1]:1 nsec
[    4.077640] acpi/hmat:   Initiator-Target[1-2]:9 nsec
[    4.078156] acpi/hmat:   Initiator-Target[1-3]:9 nsec
[    4.078471] acpi/hmat:   Initiator-Target[2-0]:9 nsec
[    4.078994] acpi/hmat:   Initiator-Target[2-1]:9 nsec
[    4.079277] acpi/hmat:   Initiator-Target[2-2]:1 nsec
[    4.079505] acpi/hmat:   Initiator-Target[2-3]:9 nsec
[    4.080126] acpi/hmat:   Initiator-Target[4-0]:13 nsec
[    4.080995] acpi/hmat:   Initiator-Target[4-1]:13 nsec
[    4.081351] acpi/hmat:   Initiator-Target[4-2]:13 nsec
[    4.082125] acpi/hmat:   Initiator-Target[4-3]:13 nsec

/sys/bus/node/devices/...

    node0 #1 and 2 similar.
        access0
            initiators
                node0
                read_bandwidth  0 #not specificed in hmat
                read_latency    1
                write_bandwidth 0
                write_latency   1
            power
            targets
                node0
                node4
            uevent
        access1
            initiators
                node0
                read_bandwidth  0
                read_latency    1
                write_bandwidth 0
                read_bandwidth  1   
            power
            targets
                node0
                node4
            uevent
        compact
        cpu0
        cpu1
        ...
    node3 # Note PXM 4, contains GI only
        #No accessX directories.
        compact
        ...
    node4
        access0
            initiators
                node0
                node1
                node2
                read_bandwidth  0
                read_latency    9
                write_bandwidth 0
                write_latency   9
            power
            targets
                *empty*
            uevent
        access1
            initiators
                node0
                node1
                node2
                read_bandwidth  0
                read_latency    9
                write_bandwidth 0
                write_latency   9
            power
            targets
                *empty*
            uevent
        compact
        ...

case 3 - as per case 2 but now the memory in node 3 is direct attached to the GI but nearer the main nodes (not physically sensible :))

/sys/bus/node/devices/...

    node0 #1 and 2 similar.
        access0
            initiators
                node0
                read_bandwidth  0 #not specificed in hmat
                read_latency    1
                write_bandwidth 0
                write_latency   1
            power
            targets
                node0
                node4
            uevent
        access1
            initiators
                node0
                read_bandwidth  0
                read_latency    1
                write_bandwidth 0
                read_bandwidth  1   
            power
            targets
                node0
                node4
            uevent
        compact
        cpu0
        cpu1
        ...
    node3 # Note PXM 4, contains GI only
        access0
            initiators
                *empty*
            power
            targets
                node4
            uevent
        compact
        ...
    node4
        access0
            initiators
                node3
                read_bandwidth  0
                read_latency    13
                write_bandwidth 0
                write_latency   13
            power
            targets
                *empty*
            uevent
        access1
            initiators
                node0
                node1
                node2
                read_bandwidth  0
                read_latency    9
                write_bandwidth 0
                write_latency   9
            power
            targets
                *empty*
            uevent
        compact
        ...

Case 4 - nearer the GI, but direct attached to one of the CPUS. # Another bonkers one.

/sys/bus/node/devices/...
node0 #1 similar.
access0
initiators
node0
read_bandwidth 0 #not specificed in hmat
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node0
node4
uevent
access1
initiators
node0
read_bandwidth 0
read_latency 1
write_bandwidth 0
read_bandwidth 1
power
targets
node0
uevent
compact
cpu0
cpu1
...
node2 # Direct attached to memory in node 3
access0
initiators
node2
read_bandwidth 0 #not specificed in hmat
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node2
node4 #direct attached
uevent
access1
initiators
node2
read_bandwidth 0
read_latency 1
write_bandwidth 0
read_bandwidth 1
power
targets
node2
node4 #direct attached
uevent
compact
cpu0
cpu1
...

node3 # Note PXM 4, contains GI only
#No accessX directories.
compact
...
node4
access0
initiators
node3
read_bandwidth 0
read_latency 13
write_bandwidth 0
write_latency 13
power
targets
*empty*
uevent
access1
initiators
node0
node1
node2
read_bandwidth 0
read_latency 9
write_bandwidth 0
write_latency 9
power
targets
*empty*
uevent
compact
...

case 5 memory and GI together in node 3 (added an extra GI to node 3) Note hmat should also reflect this extra initiator domain.

/sys/bus/node/devices/...
node0 #1 and 2 similar.
access0
initiators
node0
read_bandwidth 0 #not specificed in hmat
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node0
node4
uevent
access1
initiators
node0
read_bandwidth 0
read_latency 1
write_bandwidth 0
read_bandwidth 1
power
targets
node0
uevent
compact
cpu0
cpu1
...
node3 # Note PXM 3, contains GI only
#No accessX directories.
compact
...
node4 # Now memory and GI.
access0
initiators
node4
read_bandwidth 0
read_latency 1
write_bandwidth 0
write_latency 1
power
targets
node4
uevent
access1
initiators
node0
node1
node2
read_bandwidth 0
read_latency 9
write_bandwidth 0
write_latency 9
power
targets
*empty* # as expected GI doesn't paticipate in access 1.
uevent
compact
...

Jonathan Cameron (6):
ACPI: Support Generic Initiator only domains
x86: Support Generic Initiator only proximity domains
ACPI: Let ACPI know we support Generic Initiator Affinity Structures
ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3
node: Add access1 class to represent CPU to memory characteristics
docs: mm: numaperf.rst Add brief description for access class 1.

 Documentation/admin-guide/mm/numaperf.rst |  8 ++
 arch/x86/include/asm/numa.h               |  2 +
 arch/x86/kernel/setup.c                   |  1 +
 arch/x86/mm/numa.c                        | 14 ++++
 drivers/acpi/bus.c                        |  4 +
 drivers/acpi/numa/hmat.c                  | 89 ++++++++++++++++++-----
 drivers/acpi/numa/srat.c                  | 69 +++++++++++++++++-
 drivers/base/node.c                       |  3 +
 include/linux/acpi.h                      |  1 +
 include/linux/nodemask.h                  |  1 +
 10 files changed, 171 insertions(+), 21 deletions(-)
Signature · 1 line
2.19.1
#1 lore raw

PATCH v9 1/6 ACPI: Support Generic Initiator only domains

Generic Initiators are a new ACPI concept that allows for the description of proximity domains that contain a device which performs memory access (such as a network card) but neither host CPU nor Memory.

This patch has the parsing code and provides the infrastructure for an architecture to associate these new domains with their nearest memory processing node.

---
 drivers/acpi/numa/srat.c | 69 +++++++++++++++++++++++++++++++++++++++-
 drivers/base/node.c      |  3 ++
 include/linux/nodemask.h |  1 +
 3 files changed, 72 insertions(+), 1 deletion(-)
drivers/acpi/numa/srat.c +68 -1
index 15bbaab8500b..d27e8585132d 100644
@@ -130,6 +130,36 @@ acpi_table_print_srat_entry(struct acpi_subtable_header *header)
 		}
 		break;
 
+	case ACPI_SRAT_TYPE_GENERIC_AFFINITY:
+	{
+		struct acpi_srat_generic_affinity *p =
+			(struct acpi_srat_generic_affinity *)header;
+
+		if (p->device_handle_type == 0) {
+			/*
+			 * For pci devices this may be the only place they
+			 * are assigned a proximity domain
+			 */
+			pr_debug("SRAT Generic Initiator(Seg:%u BDF:%u) in proximity domain %d %s\n",
+				 *(u16 *)(&p->device_handle[0]),
+				 *(u16 *)(&p->device_handle[2]),
+				 p->proximity_domain,
+				 (p->flags & ACPI_SRAT_GENERIC_AFFINITY_ENABLED) ?
+				"enabled" : "disabled");
+		} else {
+			/*
+			 * In this case we can rely on the device having a
+			 * proximity domain reference
+			 */
+			pr_debug("SRAT Generic Initiator(HID=%.8s UID=%.4s) in proximity domain %d %s\n",
+				(char *)(&p->device_handle[0]),
+				(char *)(&p->device_handle[8]),
+				p->proximity_domain,
+				(p->flags & ACPI_SRAT_GENERIC_AFFINITY_ENABLED) ?
+				"enabled" : "disabled");
+		}
+	}
+	break;
 	default:
 		pr_warn("Found unsupported SRAT entry (type = 0x%x)\n",
 			header->type);
@@ -332,6 +362,41 @@ acpi_parse_gicc_affinity(union acpi_subtable_headers *header,
 	return 0;
 }
 
+#if defined(CONFIG_X86) || defined(CONFIG_ARM64)
+static int __init
+acpi_parse_gi_affinity(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	struct acpi_srat_generic_affinity *gi_affinity;
+	int node;
+
+	gi_affinity = (struct acpi_srat_generic_affinity *)header;
+	if (!gi_affinity)
+		return -EINVAL;
+	acpi_table_print_srat_entry(&header->common);
+
+	if (!(gi_affinity->flags & ACPI_SRAT_GENERIC_AFFINITY_ENABLED))
+		return -EINVAL;
+
+	node = acpi_map_pxm_to_node(gi_affinity->proximity_domain);
+	if (node == NUMA_NO_NODE || node >= MAX_NUMNODES) {
+		pr_err("SRAT: Too many proximity domains.\n");
+		return -EINVAL;
+	}
+	node_set(node, numa_nodes_parsed);
+	node_set_state(node, N_GENERIC_INITIATOR);
+
+	return 0;
+}
+#else
+static int __init
+acpi_parse_gi_affinity(union acpi_subtable_headers *header,
+		       const unsigned long end)
+{
+	return 0;
+}
+#endif /* defined(CONFIG_X86) || defined (CONFIG_ARM64) */
+
 static int __initdata parsed_numa_memblks;
 
 static int __init
@@ -385,7 +450,7 @@ int __init acpi_numa_init(void)
 
 	/* SRAT: System Resource Affinity Table */
 	if (!acpi_table_parse(ACPI_SIG_SRAT, acpi_parse_srat)) {
-		struct acpi_subtable_proc srat_proc[3];
+		struct acpi_subtable_proc srat_proc[4];
 
 		memset(srat_proc, 0, sizeof(srat_proc));
 		srat_proc[0].id = ACPI_SRAT_TYPE_CPU_AFFINITY;
@@ -394,6 +459,8 @@ int __init acpi_numa_init(void)
 		srat_proc[1].handler = acpi_parse_x2apic_affinity;
 		srat_proc[2].id = ACPI_SRAT_TYPE_GICC_AFFINITY;
 		srat_proc[2].handler = acpi_parse_gicc_affinity;
+		srat_proc[3].id = ACPI_SRAT_TYPE_GENERIC_AFFINITY;
+		srat_proc[3].handler = acpi_parse_gi_affinity;
 
 		acpi_table_parse_entries_array(ACPI_SIG_SRAT,
 					sizeof(struct acpi_table_srat),
drivers/base/node.c +3 -0
index 508b80f6329b..53383f1f683c 100644
@@ -980,6 +980,8 @@ static struct node_attr node_state_attr[] = {
 #endif
 	[N_MEMORY] = _NODE_ATTR(has_memory, N_MEMORY),
 	[N_CPU] = _NODE_ATTR(has_cpu, N_CPU),
+	[N_GENERIC_INITIATOR] = _NODE_ATTR(has_generic_initiator,
+					   N_GENERIC_INITIATOR),
 };
 
 static struct attribute *node_state_attrs[] = {
@@ -991,6 +993,7 @@ static struct attribute *node_state_attrs[] = {
 #endif
 	&node_state_attr[N_MEMORY].attr.attr,
 	&node_state_attr[N_CPU].attr.attr,
+	&node_state_attr[N_GENERIC_INITIATOR].attr.attr,
 	NULL
 };
 
include/linux/nodemask.h +1 -0
index 27e7fa36f707..3334ce056335 100644
@@ -399,6 +399,7 @@ enum node_states {
 #endif
 	N_MEMORY,		/* The node has memory(regular, high, movable) */
 	N_CPU,		/* The node has one or more cpus */
+	N_GENERIC_INITIATOR,	/* The node has one or more Generic Initiators */
 	NR_NODE_STATES
 };
 
Signature · 1 line
2.19.1
#2 lore raw

PATCH v9 2/6 x86: Support Generic Initiator only proximity domains

In reply to Jonathan Cameron

In common with memoryless domains we only register GI domains if the proximity node is not online. If a domain is already a memory containing domain, or a memoryless domain there is nothing to do just because it also contains a Generic Initiator.

---
 arch/x86/include/asm/numa.h |  2 ++
 arch/x86/kernel/setup.c     |  1 +
 arch/x86/mm/numa.c          | 14 ++++++++++++++
 3 files changed, 17 insertions(+)
arch/x86/include/asm/numa.h +2 -0
index bbfde3d2662f..f631467272a3 100644
@@ -62,12 +62,14 @@ extern void numa_clear_node(int cpu);
 extern void __init init_cpu_to_node(void);
 extern void numa_add_cpu(int cpu);
 extern void numa_remove_cpu(int cpu);
+extern void init_gi_nodes(void);
 #else	/* CONFIG_NUMA */
 static inline void numa_set_node(int cpu, int node)	{ }
 static inline void numa_clear_node(int cpu)		{ }
 static inline void init_cpu_to_node(void)		{ }
 static inline void numa_add_cpu(int cpu)		{ }
 static inline void numa_remove_cpu(int cpu)		{ }
+static inline void init_gi_nodes(void)			{ }
 #endif	/* CONFIG_NUMA */
 
 #ifdef CONFIG_DEBUG_PER_CPU_MAPS
arch/x86/kernel/setup.c +1 -0
index 3511736fbc74..9062c146f03a 100644
@@ -1218,6 +1218,7 @@ void __init setup_arch(char **cmdline_p)
 	prefill_possible_map();
 
 	init_cpu_to_node();
+	init_gi_nodes();
 
 	io_apic_init_mappings();
 
arch/x86/mm/numa.c +14 -0
index aa76ec2d359b..fc630dc6764e 100644
@@ -747,6 +747,20 @@ static void __init init_memory_less_node(int nid)
 	 */
 }
 
+/*
+ * Generic Initiator Nodes may have neither CPU nor Memory.
+ * At this stage if either of the others were present we would
+ * already be online.
+ */
+void __init init_gi_nodes(void)
+{
+	int nid;
+
+	for_each_node_state(nid, N_GENERIC_INITIATOR)
+		if (!node_online(nid))
+			init_memory_less_node(nid);
+}
+
 /*
  * Setup early cpu_to_node.
  *
Signature · 1 line
2.19.1
#3 lore raw

Re: [PATCH v9 2/6] x86: Support Generic Initiator only proximity domains

Quoted 54 lines · Jonathan Cameron

In common with memoryless domains we only register GI domains if the proximity node is not online. If a domain is already a memory containing domain, or a memoryless domain there is nothing to do just because it also contains a Generic Initiator.

---
 arch/x86/include/asm/numa.h |  2 ++
 arch/x86/kernel/setup.c     |  1 +
 arch/x86/mm/numa.c          | 14 ++++++++++++++
 3 files changed, 17 insertions(+)
arch/x86/include/asm/numa.h +2 -0
index bbfde3d2662f..f631467272a3 100644
@@ -62,12 +62,14 @@ extern void numa_clear_node(int cpu);
 extern void __init init_cpu_to_node(void);
 extern void numa_add_cpu(int cpu);
 extern void numa_remove_cpu(int cpu);
+extern void init_gi_nodes(void);
 #else	/* CONFIG_NUMA */
 static inline void numa_set_node(int cpu, int node)	{ }
 static inline void numa_clear_node(int cpu)		{ }
 static inline void init_cpu_to_node(void)		{ }
 static inline void numa_add_cpu(int cpu)		{ }
 static inline void numa_remove_cpu(int cpu)		{ }
+static inline void init_gi_nodes(void)			{ }
 #endif	/* CONFIG_NUMA */
 
 #ifdef CONFIG_DEBUG_PER_CPU_MAPS
arch/x86/kernel/setup.c +1 -0
index 3511736fbc74..9062c146f03a 100644
@@ -1218,6 +1218,7 @@ void __init setup_arch(char **cmdline_p)
 	prefill_possible_map();
 
 	init_cpu_to_node();
+	init_gi_nodes();
 
 	io_apic_init_mappings();
 
arch/x86/mm/numa.c +3 -0
index aa76ec2d359b..fc630dc6764e 100644
@@ -747,6 +747,20 @@ static void __init init_memory_less_node(int nid)
 	 */
 }
 
+/*
+ * Generic Initiator Nodes may have neither CPU nor Memory.
+ * At this stage if either of the others were present we would

arch/x86/mm/numa.c static void __init init_memory_less_node(int nid) · line 762

Quoted 10 lines
arch/x86/mm/numa.c +10 -0
+ * already be online.
+ */
+void __init init_gi_nodes(void)
+{
+	int nid;
+
+	for_each_node_state(nid, N_GENERIC_INITIATOR)
+		if (!node_online(nid))
+			init_memory_less_node(nid);
+}

This doesn't *look* very x86-specific, and apparently you don't need any arm64-specific changes? Too bad this can't be unified a little bit to remove the arch #ifdefs completely.

I do see that init_memory_less_node() is only implemented on x86, but it just seems like all this might not be inherently be arch-specific.

#4 lore raw

Re: [PATCH v9 2/6] x86: Support Generic Initiator only proximity domains

Quoted 61 lines · On Thu, 20 Aug 2020 17:24:33 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 60 lines · Jonathan Cameron

In common with memoryless domains we only register GI domains if the proximity node is not online. If a domain is already a memory containing domain, or a memoryless domain there is nothing to do just because it also contains a Generic Initiator.

---
 arch/x86/include/asm/numa.h |  2 ++
 arch/x86/kernel/setup.c     |  1 +
 arch/x86/mm/numa.c          | 14 ++++++++++++++
 3 files changed, 17 insertions(+)
arch/x86/include/asm/numa.h +2 -0
index bbfde3d2662f..f631467272a3 100644
@@ -62,12 +62,14 @@ extern void numa_clear_node(int cpu);
 extern void __init init_cpu_to_node(void);
 extern void numa_add_cpu(int cpu);
 extern void numa_remove_cpu(int cpu);
+extern void init_gi_nodes(void);
 #else	/* CONFIG_NUMA */
 static inline void numa_set_node(int cpu, int node)	{ }
 static inline void numa_clear_node(int cpu)		{ }
 static inline void init_cpu_to_node(void)		{ }
 static inline void numa_add_cpu(int cpu)		{ }
 static inline void numa_remove_cpu(int cpu)		{ }
+static inline void init_gi_nodes(void)			{ }
 #endif	/* CONFIG_NUMA */
 
 #ifdef CONFIG_DEBUG_PER_CPU_MAPS
arch/x86/kernel/setup.c +1 -0
index 3511736fbc74..9062c146f03a 100644
@@ -1218,6 +1218,7 @@ void __init setup_arch(char **cmdline_p)
 	prefill_possible_map();
 
 	init_cpu_to_node();
+	init_gi_nodes();
 
 	io_apic_init_mappings();
 
arch/x86/mm/numa.c +9 -0
index aa76ec2d359b..fc630dc6764e 100644
@@ -747,6 +747,20 @@ static void __init init_memory_less_node(int nid)
 	 */
 }
 
+/*
+ * Generic Initiator Nodes may have neither CPU nor Memory.
+ * At this stage if either of the others were present we would
+ * already be online.
+ */
+void __init init_gi_nodes(void)
+{
+	int nid;
+
Quoted 8 lines

arch/x86/mm/numa.c static void __init init_memory_less_node(int nid) · line 762

Quoted 4 lines
arch/x86/mm/numa.c +4 -0
+	for_each_node_state(nid, N_GENERIC_INITIATOR)
+		if (!node_online(nid))
+			init_memory_less_node(nid);
+}  

This doesn't *look* very x86-specific, and apparently you don't need any arm64-specific changes? Too bad this can't be unified a little bit to remove the arch #ifdefs completely.

The only ifdefs in the set aren't actually about this (which is entirely contained in arch code) they are to avoid ia64 issues as has an entirely different implementation that I doubt anyone wants to touch!

Quoted 3 lines

I do see that init_memory_less_node() is only implemented on x86, but it just seems like all this might not be inherently be arch-specific.

I absolutely agree with a long term aim to unify the numa setup code across architectures.

The x86 code is rather more involved than what we have for arm64. On arm64, memoryless nodes are handled in the same pass as those with memory (and we get GI nodes for free).

There are some separate patches under discussion that take a few steps in that direction.

https://lore.kernel.org/linux-arm-kernel/[email protected]/T/
https://patchwork.kernel.org/patch/11651437/ (this one is mostly by coincidence rather than intent!)

Jonathan

#5 lore raw

PATCH v9 3/6 ACPI: Let ACPI know we support Generic Initiator Affinity Structures

In reply to Jonathan Cameron

Until we tell ACPI that we support generic initiators, it will have to operate in fall back domain mode and all _PXM entries should be on existing non GI domains.

This patch sets the relevant OSC bit to make that happen.

---
 drivers/acpi/bus.c   | 4 ++++
 include/linux/acpi.h | 1 +
 2 files changed, 5 insertions(+)
drivers/acpi/bus.c +4 -0
index 54002670cb7a..113c661eb848 100644
@@ -303,7 +303,11 @@ static void acpi_bus_osc_support(void)
 	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_HOTPLUG_OST_SUPPORT;
 	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_PCLPI_SUPPORT;
 
+#ifdef CONFIG_ARM64
+	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_GENERIC_INITIATOR_SUPPORT;
+#endif
 #ifdef CONFIG_X86
+	capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_GENERIC_INITIATOR_SUPPORT;
 	if (boot_cpu_has(X86_FEATURE_HWP)) {
 		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPC_SUPPORT;
 		capbuf[OSC_SUPPORT_DWORD] |= OSC_SB_CPCV2_SUPPORT;
include/linux/acpi.h +1 -0
index 1e4cdc6c7ae2..1321518a53d2 100644
@@ -546,6 +546,7 @@ acpi_status acpi_run_osc(acpi_handle handle, struct acpi_osc_context *context);
 #define OSC_SB_PCLPI_SUPPORT			0x00000080
 #define OSC_SB_OSLPI_SUPPORT			0x00000100
 #define OSC_SB_CPC_DIVERSE_HIGH_SUPPORT		0x00001000
+#define OSC_SB_GENERIC_INITIATOR_SUPPORT	0x00002000
 
 extern bool osc_sb_apei_support_acked;
 extern bool osc_pc_lpi_support_confirmed;
Signature · 1 line
2.19.1
#6 lore raw

PATCH v9 4/6 ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3

In reply to Jonathan Cameron

In ACPI 6.3, the Memory Proximity Domain Attributes Structure changed substantially. One of those changes was that the flag for "Memory Proximity Domain field is valid" was deprecated.

This was because the field "Proximity Domain for the Memory" became a required field and hence having a validity flag makes no sense.

So the correct logic is to always assume the field is there. Current code assumes it never is.

---
 drivers/acpi/numa/hmat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/numa/hmat.c +1 -1
index 2c32cfb72370..07cfe50136e0 100644
@@ -424,7 +424,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) || hmat_revision == 2) {
 		target = find_mem_target(p->memory_PD);
 		if (!target) {
 			pr_debug("HMAT: Memory Domain missing from SRAT\n");
Signature · 1 line
2.19.1
#7 lore raw

Re: [PATCH v9 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3

Quoted 21 lines · Jonathan Cameron

In ACPI 6.3, the Memory Proximity Domain Attributes Structure changed substantially. One of those changes was that the flag for "Memory Proximity Domain field is valid" was deprecated.

This was because the field "Proximity Domain for the Memory" became a required field and hence having a validity flag makes no sense.

So the correct logic is to always assume the field is there. Current code assumes it never is.

---
 drivers/acpi/numa/hmat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/numa/hmat.c +0 -0
index 2c32cfb72370..07cfe50136e0 100644

drivers/acpi/numa/hmat.c static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade · line 427

Quoted 5 lines
drivers/acpi/numa/hmat.c +1 -1
@@ -424,7 +424,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) || hmat_revision == 2) {

I hope/assume the spec is written in such a way that p->memory_PD is required for any revision > 1? So maybe this should be:

  if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) ||
      hmat_revision > 1) {
Quoted 6 lines
drivers/acpi/numa/hmat.c +0 -0
 		target = find_mem_target(p->memory_PD);
 		if (!target) {
 			pr_debug("HMAT: Memory Domain missing from SRAT\n");
Signature · 1 line
2.19.1
#8 lore raw

Re: [PATCH v9 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3

Quoted 25 lines · On Thu, 20 Aug 2020 17:21:29 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 24 lines · Jonathan Cameron

In ACPI 6.3, the Memory Proximity Domain Attributes Structure changed substantially. One of those changes was that the flag for "Memory Proximity Domain field is valid" was deprecated.

This was because the field "Proximity Domain for the Memory" became a required field and hence having a validity flag makes no sense.

So the correct logic is to always assume the field is there. Current code assumes it never is.

---
 drivers/acpi/numa/hmat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/numa/hmat.c +0 -0
index 2c32cfb72370..07cfe50136e0 100644
@@ -424,7 +424,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
Quoted 3 lines

drivers/acpi/numa/hmat.c static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade · line 427

Quoted 2 lines
drivers/acpi/numa/hmat.c +1 -1
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) || hmat_revision == 2) {  

Hi Bjorn,

Quoted 5 lines

I hope/assume the spec is written in such a way that p->memory_PD is required for any revision > 1? So maybe this should be:

  if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) ||
      hmat_revision > 1) {

Good point. We have existing protections elsewhere against hmat_revision being anything other than 1 or 2, so we should aim to keep that in only one place.

I'll tidy this up for v10.

thanks,

Jonathan

Quoted 7 lines
Quoted 7 lines
drivers/acpi/numa/hmat.c +0 -0
 		target = find_mem_target(p->memory_PD);
 		if (!target) {
 			pr_debug("HMAT: Memory Domain missing from SRAT\n");
Signature · 1 line
2.19.1
#9 lore raw

Re: [PATCH v9 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3

[+cc Keith, author of 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory")]

Quoted 28 lines · Jonathan Cameron
Quoted 25 lines · On Thu, 20 Aug 2020 17:21:29 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 24 lines · Jonathan Cameron

In ACPI 6.3, the Memory Proximity Domain Attributes Structure changed substantially. One of those changes was that the flag for "Memory Proximity Domain field is valid" was deprecated.

This was because the field "Proximity Domain for the Memory" became a required field and hence having a validity flag makes no sense.

So the correct logic is to always assume the field is there. Current code assumes it never is.

---
 drivers/acpi/numa/hmat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/numa/hmat.c +0 -0
index 2c32cfb72370..07cfe50136e0 100644
@@ -424,7 +424,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
Quoted 8 lines
Quoted 8 lines

drivers/acpi/numa/hmat.c static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade · line 427

Quoted 2 lines
drivers/acpi/numa/hmat.c +1 -1
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) || hmat_revision == 2) {  

I hope/assume the spec is written in such a way that p->memory_PD is required for any revision > 1? So maybe this should be:

  if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) ||
      hmat_revision > 1) {

I should have said simply:

  if (hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID)

We shouldn't even test p->flags for ACPI_HMAT_MEMORY_PD_VALID unless we already know it's revision 1.

And unless there was a revision 0 of HMAT, there's no need to look for hmat_revison > 1.

Quoted 3 lines

Good point. We have existing protections elsewhere against hmat_revision being anything other than 1 or 2, so we should aim to keep that in only one place.

I think the "Ignoring HMAT: Unknown revision" test in hmat_init(), added by 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory"), is a mistake.

And I think hmat_normalize() has a similar mistake in that it tests explicitly for hmat_revision == 2 when it should accept 2 AND anything later.

We should assume that future spec revisions will be backwards compatible. Otherwise we're forced to make kernel changes when we otherwise would not have to.

Bjorn

#10 lore raw

Re: [PATCH v9 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3

Quoted 43 lines · On Fri, 21 Aug 2020 07:13:56 -0500 Bjorn Helgaas <[email protected]> wrote:

[+cc Keith, author of 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory")]

Quoted 28 lines · Jonathan Cameron
Quoted 25 lines · On Thu, 20 Aug 2020 17:21:29 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 24 lines · Jonathan Cameron

In ACPI 6.3, the Memory Proximity Domain Attributes Structure changed substantially. One of those changes was that the flag for "Memory Proximity Domain field is valid" was deprecated.

This was because the field "Proximity Domain for the Memory" became a required field and hence having a validity flag makes no sense.

So the correct logic is to always assume the field is there. Current code assumes it never is.

---
 drivers/acpi/numa/hmat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/numa/hmat.c +0 -0
index 2c32cfb72370..07cfe50136e0 100644
@@ -424,7 +424,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
Quoted 8 lines
Quoted 8 lines

drivers/acpi/numa/hmat.c static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade · line 427

Quoted 2 lines
drivers/acpi/numa/hmat.c +1 -1
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) || hmat_revision == 2) {    

I hope/assume the spec is written in such a way that p->memory_PD is required for any revision > 1? So maybe this should be:

  if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) ||
      hmat_revision > 1) {  

I should have said simply:

Quoted 7 lines
  if (hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID)

We shouldn't even test p->flags for ACPI_HMAT_MEMORY_PD_VALID unless we already know it's revision 1.

And unless there was a revision 0 of HMAT, there's no need to look for hmat_revison > 1.

It needs to stay as an or statement as you had the first time. The field is always valid for hmat_revision > 1, and valid for hmat_revision == 1 with the flag set. You could express it as

if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID) || (hmat_revision != 1))

but that seems more confusing to me.

Quoted 9 lines
Quoted 4 lines

Good point. We have existing protections elsewhere against hmat_revision being anything other than 1 or 2, so we should aim to keep that in only one place.

I think the "Ignoring HMAT: Unknown revision" test in hmat_init(), added by 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory"), is a mistake.

Quoted 7 lines

And I think hmat_normalize() has a similar mistake in that it tests explicitly for hmat_revision == 2 when it should accept 2 AND anything later.

We should assume that future spec revisions will be backwards compatible. Otherwise we're forced to make kernel changes when we otherwise would not have to.

I disagree with this. There is no rule in ACPI about maintaining backwards compatibility. The assumption is that the version number will always be checked. The meaning of fields changed between version 1 and version 2 so it would be bold to assume that won't happen in the future!

HMAT is an optional table, so if someone boots up an old kernel they are probably better off failing to use it at all than misinterpreting it.

Having the sanity check in one place makes sense, but removing it entirely is a bad idea.

Jonathan

Quoted 2 lines

Bjorn

#11 lore raw

Re: [PATCH v9 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3

Quoted 54 lines · Jonathan Cameron
Quoted 43 lines · On Fri, 21 Aug 2020 07:13:56 -0500 Bjorn Helgaas <[email protected]> wrote:

[+cc Keith, author of 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory")]

Quoted 28 lines · Jonathan Cameron
Quoted 25 lines · On Thu, 20 Aug 2020 17:21:29 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 24 lines · Jonathan Cameron

In ACPI 6.3, the Memory Proximity Domain Attributes Structure changed substantially. One of those changes was that the flag for "Memory Proximity Domain field is valid" was deprecated.

This was because the field "Proximity Domain for the Memory" became a required field and hence having a validity flag makes no sense.

So the correct logic is to always assume the field is there. Current code assumes it never is.

---
 drivers/acpi/numa/hmat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/numa/hmat.c +0 -0
index 2c32cfb72370..07cfe50136e0 100644
@@ -424,7 +424,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
Quoted 8 lines
Quoted 8 lines

drivers/acpi/numa/hmat.c static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade · line 427

Quoted 2 lines
drivers/acpi/numa/hmat.c +1 -1
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) || hmat_revision == 2) {    

I hope/assume the spec is written in such a way that p->memory_PD is required for any revision > 1? So maybe this should be:

  if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) ||
      hmat_revision > 1) {  

I should have said simply:

Quoted 7 lines
  if (hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID)

We shouldn't even test p->flags for ACPI_HMAT_MEMORY_PD_VALID unless we already know it's revision 1.

And unless there was a revision 0 of HMAT, there's no need to look for hmat_revison > 1.

Quoted 7 lines

It needs to stay as an or statement as you had the first time. The field is always valid for hmat_revision > 1, and valid for hmat_revision == 1 with the flag set. You could express it as

if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID) || (hmat_revision != 1))

but that seems more confusing to me.

Oh, you're right, sorry! There are two questions here:

1) In what order should we test "p->flags & ACPI_HMAT_MEMORY_PD_VALID" and "hmat_revision == 1"? ACPI_HMAT_MEMORY_PD_VALID is defined only when "hmat_revision == 1", so I think we should test the revision first.

When "hmat_revision == 2", ACPI_HMAT_MEMORY_PD_VALID is reserved, so we shouldn't test it, even if we later check the revision and discard the result of the flag test. This is a tiny thing, admittedly, but I think it follows the spec more clearly.

2) Do we need to test hmat_revision for anything other than 1? Yes, you're right, see below.

Quoted 16 lines
Quoted 8 lines
Quoted 3 lines

Good point. We have existing protections elsewhere against hmat_revision being anything other than 1 or 2, so we should aim to keep that in only one place.

I think the "Ignoring HMAT: Unknown revision" test in hmat_init(), added by 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory"), is a mistake.

Quoted 7 lines

And I think hmat_normalize() has a similar mistake in that it tests explicitly for hmat_revision == 2 when it should accept 2 AND anything later.

We should assume that future spec revisions will be backwards compatible. Otherwise we're forced to make kernel changes when we otherwise would not have to.

Quoted 5 lines

I disagree with this. There is no rule in ACPI about maintaining backwards compatibility. The assumption is that the version number will always be checked. The meaning of fields changed between version 1 and version 2 so it would be bold to assume that won't happen in the future!

There *is* a rule about maintaining backwards compatibility. ACPI v6.3, sec 5.2.2, says:

All versions of the ACPI tables must maintain backward compatibility. To accomplish this, modifications of the tables consist of redefinition of previously reserved fields and values plus appending data to the 1.0 tables. Modifications of the ACPI tables require that the version numbers of the modified tables be incremented.

Quoted 3 lines

HMAT is an optional table, so if someone boots up an old kernel they are probably better off failing to use it at all than misinterpreting it.

An old kernel tests:

  if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1)
    target = find_mem_target(p->memory_PD);

which is fine on old firmware. On new firmware (hmat_revision == 2), it will ignore p->memory_PD. That is probably a problem, but I think we should check for that at the place where we need a memory_PD and don't find one. That's more general than sanity checking a revision.

A new kernel that tests:

  if ((hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID) ||
       hmat_revision > 1)
    target = find_mem_target(p->memory_PD);

will do the right thing on both old and new firmware.

Bjorn

#12 lore raw

Re: [PATCH v9 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3

Quoted 124 lines · Bjorn Helgaas
Quoted 54 lines · Jonathan Cameron
Quoted 43 lines · On Fri, 21 Aug 2020 07:13:56 -0500 Bjorn Helgaas <[email protected]> wrote:

[+cc Keith, author of 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory")]

Quoted 28 lines · Jonathan Cameron
Quoted 25 lines · On Thu, 20 Aug 2020 17:21:29 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 24 lines · Jonathan Cameron

In ACPI 6.3, the Memory Proximity Domain Attributes Structure changed substantially. One of those changes was that the flag for "Memory Proximity Domain field is valid" was deprecated.

This was because the field "Proximity Domain for the Memory" became a required field and hence having a validity flag makes no sense.

So the correct logic is to always assume the field is there. Current code assumes it never is.

---
 drivers/acpi/numa/hmat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/numa/hmat.c +0 -0
index 2c32cfb72370..07cfe50136e0 100644
@@ -424,7 +424,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
Quoted 8 lines
Quoted 8 lines

drivers/acpi/numa/hmat.c static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade · line 427

Quoted 2 lines
drivers/acpi/numa/hmat.c +1 -1
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) || hmat_revision == 2) {    

I hope/assume the spec is written in such a way that p->memory_PD is required for any revision > 1? So maybe this should be:

  if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) ||
      hmat_revision > 1) {  

I should have said simply:

Quoted 7 lines
  if (hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID)

We shouldn't even test p->flags for ACPI_HMAT_MEMORY_PD_VALID unless we already know it's revision 1.

And unless there was a revision 0 of HMAT, there's no need to look for hmat_revison > 1.

Quoted 7 lines

It needs to stay as an or statement as you had the first time. The field is always valid for hmat_revision > 1, and valid for hmat_revision == 1 with the flag set. You could express it as

if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID) || (hmat_revision != 1))

but that seems more confusing to me.

Oh, you're right, sorry! There are two questions here:

1) In what order should we test "p->flags & ACPI_HMAT_MEMORY_PD_VALID" and "hmat_revision == 1"? ACPI_HMAT_MEMORY_PD_VALID is defined only when "hmat_revision == 1", so I think we should test the revision first.

When "hmat_revision == 2", ACPI_HMAT_MEMORY_PD_VALID is reserved, so we shouldn't test it, even if we later check the revision and discard the result of the flag test. This is a tiny thing, admittedly, but I think it follows the spec more clearly.

2) Do we need to test hmat_revision for anything other than 1? Yes, you're right, see below.

Quoted 16 lines
Quoted 8 lines
Quoted 3 lines

Good point. We have existing protections elsewhere against hmat_revision being anything other than 1 or 2, so we should aim to keep that in only one place.

I think the "Ignoring HMAT: Unknown revision" test in hmat_init(), added by 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory"), is a mistake.

Quoted 7 lines

And I think hmat_normalize() has a similar mistake in that it tests explicitly for hmat_revision == 2 when it should accept 2 AND anything later.

We should assume that future spec revisions will be backwards compatible. Otherwise we're forced to make kernel changes when we otherwise would not have to.

Quoted 5 lines

I disagree with this. There is no rule in ACPI about maintaining backwards compatibility. The assumption is that the version number will always be checked. The meaning of fields changed between version 1 and version 2 so it would be bold to assume that won't happen in the future!

There *is* a rule about maintaining backwards compatibility. ACPI v6.3, sec 5.2.2, says:

All versions of the ACPI tables must maintain backward compatibility. To accomplish this, modifications of the tables consist of redefinition of previously reserved fields and values plus appending data to the 1.0 tables. Modifications of the ACPI tables require that the version numbers of the modified tables be incremented.

Quoted 3 lines

HMAT is an optional table, so if someone boots up an old kernel they are probably better off failing to use it at all than misinterpreting it.

An old kernel tests:

  if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1)
    target = find_mem_target(p->memory_PD);

which is fine on old firmware. On new firmware (hmat_revision == 2), it will ignore p->memory_PD. That is probably a problem, but I think we should check for that at the place where we need a memory_PD and don't find one. That's more general than sanity checking a revision.

Quoted 7 lines

A new kernel that tests:

  if ((hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID) ||
       hmat_revision > 1)
    target = find_mem_target(p->memory_PD);

will do the right thing on both old and new firmware.

Actually, I think this part of the spec was done incorrectly.

ACPI v6.3 could have made the p->memory_PD field required without changing the definition of ACPI_HMAT_MEMORY_PD_VALID. What value was gained by making ACPI_HMAT_MEMORY_PD_VALID a reserved bit in v6.3?

If they had left ACPI_HMAT_MEMORY_PD_VALID alone, the Linux code could have been simply this, which would work with old firmware and new firmware, and we wouldn't have to touch this at all:

  if (p->flags & ACPI_HMAT_MEMORY_PD_VALID)
    target = find_mem_target(p->memory_PD);

Bjorn

#13 lore raw

Re: [PATCH v9 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3

Quoted 139 lines · On Fri, 21 Aug 2020 09:59:23 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 124 lines · Bjorn Helgaas
Quoted 54 lines · Jonathan Cameron
Quoted 43 lines · On Fri, 21 Aug 2020 07:13:56 -0500 Bjorn Helgaas <[email protected]> wrote:

[+cc Keith, author of 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory")]

Quoted 28 lines · Jonathan Cameron
Quoted 25 lines · On Thu, 20 Aug 2020 17:21:29 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 24 lines · Jonathan Cameron

In ACPI 6.3, the Memory Proximity Domain Attributes Structure changed substantially. One of those changes was that the flag for "Memory Proximity Domain field is valid" was deprecated.

This was because the field "Proximity Domain for the Memory" became a required field and hence having a validity flag makes no sense.

So the correct logic is to always assume the field is there. Current code assumes it never is.

---
 drivers/acpi/numa/hmat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/numa/hmat.c +0 -0
index 2c32cfb72370..07cfe50136e0 100644
@@ -424,7 +424,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
Quoted 8 lines
Quoted 8 lines

drivers/acpi/numa/hmat.c static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade · line 427

Quoted 2 lines
drivers/acpi/numa/hmat.c +1 -1
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) || hmat_revision == 2) {      

I hope/assume the spec is written in such a way that p->memory_PD is required for any revision > 1? So maybe this should be:

  if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) ||
      hmat_revision > 1) {    

I should have said simply:

Quoted 7 lines
  if (hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID)

We shouldn't even test p->flags for ACPI_HMAT_MEMORY_PD_VALID unless we already know it's revision 1.

And unless there was a revision 0 of HMAT, there's no need to look for hmat_revison > 1.

Quoted 7 lines

It needs to stay as an or statement as you had the first time. The field is always valid for hmat_revision > 1, and valid for hmat_revision == 1 with the flag set. You could express it as

if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID) || (hmat_revision != 1))

but that seems more confusing to me.

Oh, you're right, sorry! There are two questions here:

1) In what order should we test "p->flags & ACPI_HMAT_MEMORY_PD_VALID" and "hmat_revision == 1"? ACPI_HMAT_MEMORY_PD_VALID is defined only when "hmat_revision == 1", so I think we should test the revision first.

When "hmat_revision == 2", ACPI_HMAT_MEMORY_PD_VALID is reserved, so we shouldn't test it, even if we later check the revision and discard the result of the flag test. This is a tiny thing, admittedly, but I think it follows the spec more clearly.

2) Do we need to test hmat_revision for anything other than 1? Yes, you're right, see below.

Quoted 16 lines
Quoted 8 lines
Quoted 3 lines

Good point. We have existing protections elsewhere against hmat_revision being anything other than 1 or 2, so we should aim to keep that in only one place.

I think the "Ignoring HMAT: Unknown revision" test in hmat_init(), added by 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory"), is a mistake.

Quoted 7 lines

And I think hmat_normalize() has a similar mistake in that it tests explicitly for hmat_revision == 2 when it should accept 2 AND anything later.

We should assume that future spec revisions will be backwards compatible. Otherwise we're forced to make kernel changes when we otherwise would not have to.

Quoted 5 lines

I disagree with this. There is no rule in ACPI about maintaining backwards compatibility. The assumption is that the version number will always be checked. The meaning of fields changed between version 1 and version 2 so it would be bold to assume that won't happen in the future!

There *is* a rule about maintaining backwards compatibility. ACPI v6.3, sec 5.2.2, says:

All versions of the ACPI tables must maintain backward compatibility. To accomplish this, modifications of the tables consist of redefinition of previously reserved fields and values plus appending data to the 1.0 tables. Modifications of the ACPI tables require that the version numbers of the modified tables be incremented.

Quoted 3 lines

HMAT is an optional table, so if someone boots up an old kernel they are probably better off failing to use it at all than misinterpreting it.

An old kernel tests:

  if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1)
    target = find_mem_target(p->memory_PD);

which is fine on old firmware. On new firmware (hmat_revision == 2), it will ignore p->memory_PD. That is probably a problem, but I think we should check for that at the place where we need a memory_PD and don't find one. That's more general than sanity checking a revision.

Quoted 7 lines

A new kernel that tests:

  if ((hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID) ||
       hmat_revision > 1)
    target = find_mem_target(p->memory_PD);

will do the right thing on both old and new firmware.

Actually, I think this part of the spec was done incorrectly.

ACPI v6.3 could have made the p->memory_PD field required without changing the definition of ACPI_HMAT_MEMORY_PD_VALID. What value was gained by making ACPI_HMAT_MEMORY_PD_VALID a reserved bit in v6.3?

Quoted 6 lines

If they had left ACPI_HMAT_MEMORY_PD_VALID alone, the Linux code could have been simply this, which would work with old firmware and new firmware, and we wouldn't have to touch this at all:

  if (p->flags & ACPI_HMAT_MEMORY_PD_VALID)
    target = find_mem_target(p->memory_PD);

I have a slight recollection that might have been my fault :) Oops.

Jonathan

Quoted 2 lines

Bjorn

#14 lore raw

Re: [PATCH v9 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3

In reply to Bjorn Helgaas
Quoted 70 lines · On Fri, 21 Aug 2020 08:46:22 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 54 lines · Jonathan Cameron
Quoted 43 lines · On Fri, 21 Aug 2020 07:13:56 -0500 Bjorn Helgaas <[email protected]> wrote:

[+cc Keith, author of 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory")]

Quoted 28 lines · Jonathan Cameron
Quoted 25 lines · On Thu, 20 Aug 2020 17:21:29 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 24 lines · Jonathan Cameron

In ACPI 6.3, the Memory Proximity Domain Attributes Structure changed substantially. One of those changes was that the flag for "Memory Proximity Domain field is valid" was deprecated.

This was because the field "Proximity Domain for the Memory" became a required field and hence having a validity flag makes no sense.

So the correct logic is to always assume the field is there. Current code assumes it never is.

---
 drivers/acpi/numa/hmat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/numa/hmat.c +0 -0
index 2c32cfb72370..07cfe50136e0 100644
@@ -424,7 +424,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
Quoted 8 lines
Quoted 8 lines

drivers/acpi/numa/hmat.c static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade · line 427

Quoted 2 lines
drivers/acpi/numa/hmat.c +1 -1
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) || hmat_revision == 2) {      

I hope/assume the spec is written in such a way that p->memory_PD is required for any revision > 1? So maybe this should be:

  if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) ||
      hmat_revision > 1) {    

I should have said simply:

Quoted 7 lines
  if (hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID)

We shouldn't even test p->flags for ACPI_HMAT_MEMORY_PD_VALID unless we already know it's revision 1.

And unless there was a revision 0 of HMAT, there's no need to look for hmat_revison > 1.

Quoted 7 lines

It needs to stay as an or statement as you had the first time. The field is always valid for hmat_revision > 1, and valid for hmat_revision == 1 with the flag set. You could express it as

if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID) || (hmat_revision != 1))

but that seems more confusing to me.

Oh, you're right, sorry! There are two questions here:

1) In what order should we test "p->flags & ACPI_HMAT_MEMORY_PD_VALID" and "hmat_revision == 1"? ACPI_HMAT_MEMORY_PD_VALID is defined only when "hmat_revision == 1", so I think we should test the revision first.

Quoted 4 lines

When "hmat_revision == 2", ACPI_HMAT_MEMORY_PD_VALID is reserved, so we shouldn't test it, even if we later check the revision and discard the result of the flag test. This is a tiny thing, admittedly, but I think it follows the spec more clearly.

Agreed.

Quoted 29 lines

2) Do we need to test hmat_revision for anything other than 1? Yes, you're right, see below.

Quoted 16 lines
Quoted 8 lines
Quoted 3 lines

Good point. We have existing protections elsewhere against hmat_revision being anything other than 1 or 2, so we should aim to keep that in only one place.

I think the "Ignoring HMAT: Unknown revision" test in hmat_init(), added by 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory"), is a mistake.

Quoted 7 lines

And I think hmat_normalize() has a similar mistake in that it tests explicitly for hmat_revision == 2 when it should accept 2 AND anything later.

We should assume that future spec revisions will be backwards compatible. Otherwise we're forced to make kernel changes when we otherwise would not have to.

Quoted 5 lines

I disagree with this. There is no rule in ACPI about maintaining backwards compatibility. The assumption is that the version number will always be checked. The meaning of fields changed between version 1 and version 2 so it would be bold to assume that won't happen in the future!

There *is* a rule about maintaining backwards compatibility. ACPI v6.3, sec 5.2.2, says:

Quoted 6 lines

All versions of the ACPI tables must maintain backward compatibility. To accomplish this, modifications of the tables consist of redefinition of previously reserved fields and values plus appending data to the 1.0 tables. Modifications of the ACPI tables require that the version numbers of the modified tables be incremented.

Fair point. Unfortunately it's not true here... The field we are talking about here is probably fine, but the latency units changed between v1 and v2.

Quoted 15 lines
Quoted 4 lines

HMAT is an optional table, so if someone boots up an old kernel they are probably better off failing to use it at all than misinterpreting it.

An old kernel tests:

  if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1)
    target = find_mem_target(p->memory_PD);

which is fine on old firmware. On new firmware (hmat_revision == 2), it will ignore p->memory_PD. That is probably a problem, but I think we should check for that at the place where we need a memory_PD and don't find one. That's more general than sanity checking a revision.

Quoted 8 lines

A new kernel that tests:

  if ((hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID) ||
       hmat_revision > 1)
    target = find_mem_target(p->memory_PD);

will do the right thing on both old and new firmware.

For the case here we are fine, but as mentioned above, it's not the only version dependent part.

Jonathan

Quoted 1 line

Bjorn

#15 lore raw

Re: [PATCH v9 4/6] ACPI: HMAT: Fix handling of changes from ACPI 6.2 to ACPI 6.3

Quoted 116 lines · Jonathan Cameron
Quoted 70 lines · On Fri, 21 Aug 2020 08:46:22 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 54 lines · Jonathan Cameron
Quoted 43 lines · On Fri, 21 Aug 2020 07:13:56 -0500 Bjorn Helgaas <[email protected]> wrote:

[+cc Keith, author of 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory")]

Quoted 28 lines · Jonathan Cameron
Quoted 25 lines · On Thu, 20 Aug 2020 17:21:29 -0500 Bjorn Helgaas <[email protected]> wrote:
Quoted 24 lines · Jonathan Cameron

In ACPI 6.3, the Memory Proximity Domain Attributes Structure changed substantially. One of those changes was that the flag for "Memory Proximity Domain field is valid" was deprecated.

This was because the field "Proximity Domain for the Memory" became a required field and hence having a validity flag makes no sense.

So the correct logic is to always assume the field is there. Current code assumes it never is.

---
 drivers/acpi/numa/hmat.c | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)
drivers/acpi/numa/hmat.c +0 -0
index 2c32cfb72370..07cfe50136e0 100644
@@ -424,7 +424,7 @@ static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade
 		pr_info("HMAT: Memory Flags:%04x Processor Domain:%u Memory Domain:%u\n",
 			p->flags, p->processor_PD, p->memory_PD);
 
Quoted 8 lines
Quoted 8 lines

drivers/acpi/numa/hmat.c static int __init hmat_parse_proximity_domain(union acpi_subtable_headers *heade · line 427

Quoted 2 lines
drivers/acpi/numa/hmat.c +1 -1
-	if (p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) {
+	if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) || hmat_revision == 2) {      

I hope/assume the spec is written in such a way that p->memory_PD is required for any revision > 1? So maybe this should be:

  if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID && hmat_revision == 1) ||
      hmat_revision > 1) {    

I should have said simply:

Quoted 7 lines
  if (hmat_revision == 1 && p->flags & ACPI_HMAT_MEMORY_PD_VALID)

We shouldn't even test p->flags for ACPI_HMAT_MEMORY_PD_VALID unless we already know it's revision 1.

And unless there was a revision 0 of HMAT, there's no need to look for hmat_revison > 1.

Quoted 7 lines

It needs to stay as an or statement as you had the first time. The field is always valid for hmat_revision > 1, and valid for hmat_revision == 1 with the flag set. You could express it as

if ((p->flags & ACPI_HMAT_MEMORY_PD_VALID) || (hmat_revision != 1))

but that seems more confusing to me.

Oh, you're right, sorry! There are two questions here:

1) In what order should we test "p->flags & ACPI_HMAT_MEMORY_PD_VALID" and "hmat_revision == 1"? ACPI_HMAT_MEMORY_PD_VALID is defined only when "hmat_revision == 1", so I think we should test the revision first.

Quoted 4 lines

When "hmat_revision == 2", ACPI_HMAT_MEMORY_PD_VALID is reserved, so we shouldn't test it, even if we later check the revision and discard the result of the flag test. This is a tiny thing, admittedly, but I think it follows the spec more clearly.

Agreed.

Quoted 29 lines

2) Do we need to test hmat_revision for anything other than 1? Yes, you're right, see below.

Quoted 16 lines
Quoted 8 lines
Quoted 3 lines

Good point. We have existing protections elsewhere against hmat_revision being anything other than 1 or 2, so we should aim to keep that in only one place.

I think the "Ignoring HMAT: Unknown revision" test in hmat_init(), added by 3accf7ae37a9 ("acpi/hmat: Parse and report heterogeneous memory"), is a mistake.

Quoted 7 lines

And I think hmat_normalize() has a similar mistake in that it tests explicitly for hmat_revision == 2 when it should accept 2 AND anything later.

We should assume that future spec revisions will be backwards compatible. Otherwise we're forced to make kernel changes when we otherwise would not have to.

Quoted 5 lines

I disagree with this. There is no rule in ACPI about maintaining backwards compatibility. The assumption is that the version number will always be checked. The meaning of fields changed between version 1 and version 2 so it would be bold to assume that won't happen in the future!

There *is* a rule about maintaining backwards compatibility. ACPI v6.3, sec 5.2.2, says:

Quoted 6 lines

All versions of the ACPI tables must maintain backward compatibility. To accomplish this, modifications of the tables consist of redefinition of previously reserved fields and values plus appending data to the 1.0 tables. Modifications of the ACPI tables require that the version numbers of the modified tables be incremented.

Quoted 3 lines

Fair point. Unfortunately it's not true here... The field we are talking about here is probably fine, but the latency units changed between v1 and v2.

Oops. Sounds like this should have been done in a way that didn't break old kernels reading new tables. It's OK if old kernels can't use new features, but not OK if things that used to work are broken by new tables.

Bjorn

#16 lore raw

PATCH v9 5/6 node: Add access1 class to represent CPU to memory characteristics

In reply to Jonathan Cameron

New access1 class is nearly the same as access0, but always provides
characteristics for CPUs to memory. The existing access0 class
provides characteristics to nearest or direct connnect initiator which may be a Generic Initiator such as a GPU or network adapter.

This new class allows thread placement on CPUs to be performed so as to give optimal access characteristics to memory, even if that memory is for example attached to a GPU or similar and only accessible to the CPU via an appropriate bus.

---
 drivers/acpi/numa/hmat.c | 87 +++++++++++++++++++++++++++++++---------
 1 file changed, 68 insertions(+), 19 deletions(-)
drivers/acpi/numa/hmat.c +68 -19
index 07cfe50136e0..00b4cdbefb5e 100644
@@ -56,7 +56,7 @@ struct memory_target {
 	unsigned int memory_pxm;
 	unsigned int processor_pxm;
 	struct resource memregions;
-	struct node_hmem_attrs hmem_attrs;
+	struct node_hmem_attrs hmem_attrs[2];
 	struct list_head caches;
 	struct node_cache_attrs cache_attrs;
 	bool registered;
@@ -65,6 +65,7 @@ struct memory_target {
 struct memory_initiator {
 	struct list_head node;
 	unsigned int processor_pxm;
+	bool has_cpu;
 };
 
 struct memory_locality {
@@ -108,6 +109,7 @@ static __init void alloc_memory_initiator(unsigned int cpu_pxm)
 		return;
 
 	initiator->processor_pxm = cpu_pxm;
+	initiator->has_cpu = node_state(pxm_to_node(cpu_pxm), N_CPU);
 	list_add_tail(&initiator->node, &initiators);
 }
 
@@ -215,28 +217,28 @@ static u32 hmat_normalize(u16 entry, u64 base, u8 type)
 }
 
 static void hmat_update_target_access(struct memory_target *target,
-					     u8 type, u32 value)
+				      u8 type, u32 value, int access)
 {
 	switch (type) {
 	case ACPI_HMAT_ACCESS_LATENCY:
-		target->hmem_attrs.read_latency = value;
-		target->hmem_attrs.write_latency = value;
+		target->hmem_attrs[access].read_latency = value;
+		target->hmem_attrs[access].write_latency = value;
 		break;
 	case ACPI_HMAT_READ_LATENCY:
-		target->hmem_attrs.read_latency = value;
+		target->hmem_attrs[access].read_latency = value;
 		break;
 	case ACPI_HMAT_WRITE_LATENCY:
-		target->hmem_attrs.write_latency = value;
+		target->hmem_attrs[access].write_latency = value;
 		break;
 	case ACPI_HMAT_ACCESS_BANDWIDTH:
-		target->hmem_attrs.read_bandwidth = value;
-		target->hmem_attrs.write_bandwidth = value;
+		target->hmem_attrs[access].read_bandwidth = value;
+		target->hmem_attrs[access].write_bandwidth = value;
 		break;
 	case ACPI_HMAT_READ_BANDWIDTH:
-		target->hmem_attrs.read_bandwidth = value;
+		target->hmem_attrs[access].read_bandwidth = value;
 		break;
 	case ACPI_HMAT_WRITE_BANDWIDTH:
-		target->hmem_attrs.write_bandwidth = value;
+		target->hmem_attrs[access].write_bandwidth = value;
 		break;
 	default:
 		break;
@@ -329,8 +331,12 @@ static __init int hmat_parse_locality(union acpi_subtable_headers *header,
 
 			if (mem_hier == ACPI_HMAT_MEMORY) {
 				target = find_mem_target(targs[targ]);
-				if (target && target->processor_pxm == inits[init])
-					hmat_update_target_access(target, type, value);
+				if (target && target->processor_pxm == inits[init]) {
+					hmat_update_target_access(target, type, value, 0);
+					/* If the node has a CPU, update access 1*/
+					if (node_state(pxm_to_node(inits[init]), N_CPU))
+						hmat_update_target_access(target, type, value, 1);
+				}
 			}
 		}
 	}
@@ -566,6 +572,7 @@ static void hmat_register_target_initiators(struct memory_target *target)
 	unsigned int mem_nid, cpu_nid;
 	struct memory_locality *loc = NULL;
 	u32 best = 0;
+	bool access0done = false;
 	int i;
 
 	mem_nid = pxm_to_node(target->memory_pxm);
@@ -577,7 +584,11 @@ static void hmat_register_target_initiators(struct memory_target *target)
 	if (target->processor_pxm != PXM_INVAL) {
 		cpu_nid = pxm_to_node(target->processor_pxm);
 		register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
-		return;
+		access0done = true;
+		if (node_state(cpu_nid, N_CPU)) {
+			register_memory_node_under_compute_node(mem_nid, cpu_nid, 1);
+			return;
+		}
 	}
 
 	if (list_empty(&localities))
@@ -591,6 +602,40 @@ static void hmat_register_target_initiators(struct memory_target *target)
 	 */
 	bitmap_zero(p_nodes, MAX_NUMNODES);
 	list_sort(p_nodes, &initiators, initiator_cmp);
+	if (!access0done) {
+		for (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) {
+			loc = localities_types[i];
+			if (!loc)
+				continue;
+
+			best = 0;
+			list_for_each_entry(initiator, &initiators, node) {
+				u32 value;
+
+				if (!test_bit(initiator->processor_pxm, p_nodes))
+					continue;
+
+				value = hmat_initiator_perf(target, initiator,
+							    loc->hmat_loc);
+				if (hmat_update_best(loc->hmat_loc->data_type, value, &best))
+					bitmap_clear(p_nodes, 0, initiator->processor_pxm);
+				if (value != best)
+					clear_bit(initiator->processor_pxm, p_nodes);
+			}
+			if (best)
+				hmat_update_target_access(target, loc->hmat_loc->data_type, best, 0);
+		}
+
+		for_each_set_bit(i, p_nodes, MAX_NUMNODES) {
+			cpu_nid = pxm_to_node(i);
+			register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
+		}
+	}
+
+	/* Access 1 ignores Generic Initiators */
+	bitmap_zero(p_nodes, MAX_NUMNODES);
+	list_sort(p_nodes, &initiators, initiator_cmp);
+	best = 0;
 	for (i = WRITE_LATENCY; i <= READ_BANDWIDTH; i++) {
 		loc = localities_types[i];
 		if (!loc)
@@ -600,6 +645,10 @@ static void hmat_register_target_initiators(struct memory_target *target)
 		list_for_each_entry(initiator, &initiators, node) {
 			u32 value;
 
+			if (!initiator->has_cpu) {
+				clear_bit(initiator->processor_pxm, p_nodes);
+				continue;
+			}
 			if (!test_bit(initiator->processor_pxm, p_nodes))
 				continue;
 
@@ -610,12 +659,11 @@ static void hmat_register_target_initiators(struct memory_target *target)
 				clear_bit(initiator->processor_pxm, p_nodes);
 		}
 		if (best)
-			hmat_update_target_access(target, loc->hmat_loc->data_type, best);
+			hmat_update_target_access(target, loc->hmat_loc->data_type, best, 1);
 	}
-
 	for_each_set_bit(i, p_nodes, MAX_NUMNODES) {
 		cpu_nid = pxm_to_node(i);
-		register_memory_node_under_compute_node(mem_nid, cpu_nid, 0);
+		register_memory_node_under_compute_node(mem_nid, cpu_nid, 1);
 	}
 }
 
@@ -628,10 +676,10 @@ static void hmat_register_target_cache(struct memory_target *target)
 		node_add_cache(mem_nid, &tcache->cache_attrs);
 }
 
-static void hmat_register_target_perf(struct memory_target *target)
+static void hmat_register_target_perf(struct memory_target *target, int access)
 {
 	unsigned mem_nid = pxm_to_node(target->memory_pxm);
-	node_set_perf_attrs(mem_nid, &target->hmem_attrs, 0);
+	node_set_perf_attrs(mem_nid, &target->hmem_attrs[access], access);
 }
 
 static void hmat_register_target_device(struct memory_target *target,
@@ -733,7 +781,8 @@ static void hmat_register_target(struct memory_target *target)
 	if (!target->registered) {
 		hmat_register_target_initiators(target);
 		hmat_register_target_cache(target);
-		hmat_register_target_perf(target);
+		hmat_register_target_perf(target, 0);
+		hmat_register_target_perf(target, 1);
 		target->registered = true;
 	}
 	mutex_unlock(&target_lock);
Signature · 1 line
2.19.1
#17 lore raw

PATCH v9 6/6 docs: mm: numaperf.rst Add brief description for access class 1.

In reply to Jonathan Cameron

Try to make minimal changes to the document which already describes access class 0 in a generic fashion (including IO initiatiors that are not CPUs).

---
 Documentation/admin-guide/mm/numaperf.rst | 8 ++++++++
 1 file changed, 8 insertions(+)
Documentation/admin-guide/mm/numaperf.rst +8 -0
index 4d69ef1de830..b89bb85eac75 100644
@@ -56,6 +56,11 @@ nodes' access characteristics share the same performance relative to other
 linked initiator nodes. Each target within an initiator's access class,
 though, do not necessarily perform the same as each other.
 
+The access class "1" is used to allow differentiation between initiators
+that are CPUs and hence suitable for generic task scheduling, and
+IO initiators such as GPUs and NICs.  Unlike access class 0, only
+nodes containing CPUs are considered.
+
 ================
 NUMA Performance
 ================
@@ -88,6 +93,9 @@ The latency attributes are provided in nanoseconds.
 The values reported here correspond to the rated latency and bandwidth
 for the platform.
 
+Access class 1, takes the same form, but only includes values for CPU to
+memory activity.
+
 ==========
 NUMA Cache
 ==========
Signature · 1 line
2.19.1