ARM: dts: exynos: dtschema cleanups for Exynos5

PATCH Applied Krzysztof Kozlowski 2 participants 22 messages Sep 1, 2020 – Sep 4, 2020

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Device tree bindings Arm Samsung Exynos

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Krzysztof Kozlowski

author maintainer

2020-09-01 07:54 UTC #0 lore raw

cover ARM: dts: exynos: dtschema cleanups for Exynos5

Hi,

This is continuation of my series of dtschema cleanup for Exynos SoCs.

The previous series are here:
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t

TODO - remaining: S3C, S5Pv210.

Best regards,
Krzysztof

Krzysztof Kozlowski (13):
ARM: dts: exynos: Correct compatible for Exynos5 GIC
ARM: dts: exynos: Correct compatible for Exynos5260 GIC
ARM: dts: exynos: Remove unneeded address/size cells in Exynos5260 GIC
ARM: dts: exynos: Correct S3C RTC bindings in SMDK5410
ARM: dts: exynos: Silence i2c-gpio dtschema warning in Exynos5250
Arndale
ARM: dts: exynos: Correct whitespace and indentation issues in Exynos5
ARM: dts: exynos: Override thermal by label in Exynos5250
ARM: dts: exynos: Add max77686 clocks for S3C RTC in SMDK5250
ARM: dts: exynos: Use S5M8767 clock in S3C RTC in Exynos5250 Spring
ARM: dts: exynos: Silence DP HPD pinctrl dtschema warning in
Exynos5250 Spring
ARM: dts: exynos: Silence SATA PHY warning in Exynos5250 Arndale
ARM: dts: exynos: Silence SATA PHY warning in SMDK5250
ARM: dts: exynos: Use S2MPS11 clock in S3C RTC in SMDK5420

 arch/arm/boot/dts/exynos5.dtsi                | 10 ++--
 arch/arm/boot/dts/exynos5250-arndale.dts      | 12 ++---
 arch/arm/boot/dts/exynos5250-smdk5250.dts     |  8 +++-
 arch/arm/boot/dts/exynos5250-spring.dts       | 41 ++++++++++-------
 arch/arm/boot/dts/exynos5250.dtsi             | 46 +++++++++----------
 arch/arm/boot/dts/exynos5260.dtsi             |  4 +-
 arch/arm/boot/dts/exynos5410-odroidxu.dts     |  8 ++--
 arch/arm/boot/dts/exynos5410-smdk5410.dts     | 12 +++++
 arch/arm/boot/dts/exynos5410.dtsi             | 12 ++---
 arch/arm/boot/dts/exynos5420-smdk5420.dts     |  3 ++
 arch/arm/boot/dts/exynos5420.dtsi             | 16 +++----
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi |  4 +-
 12 files changed, 99 insertions(+), 77 deletions(-)

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:54 UTC #1 lore raw

PATCH 1/13 ARM: dts: exynos: Correct compatible for Exynos5 GIC

Exynos5250 and Exynso54xx SoCs have ARM GIC 400. Correct the compatibles to match dtschema and fix the dtbs_check warnings like:

arch/arm/boot/dts/exynos5420-peach-pit.dt.yaml: interrupt-controller@10481000:
compatible: ['arm,gic-400', 'arm,cortex-a15-gic', 'arm,cortex-a9-gic'] is not valid under any of the given schemas

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/boot/dts/exynos5.dtsi +1 -1

index 22eb951c614c..9660104be4c9 100644
@@ -86,7 +86,7 @@
 		};
 
 		gic: interrupt-controller@10481000 {
-			compatible = "arm,gic-400", "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+			compatible = "arm,gic-400", "arm,cortex-a15-gic";
 			#interrupt-cells = <3>;
 			interrupt-controller;
 			reg =	<0x10481000 0x1000>,

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-03 20:49 UTC #2 lore raw

Re: [PATCH 01/13] ARM: dts: exynos: Correct compatible for Exynos5 GIC

Quoted 12 lines · Krzysztof Kozlowski

Exynos5250 and Exynso54xx SoCs have ARM GIC 400. Correct the compatibles to match dtschema and fix the dtbs_check warnings like:
arch/arm/boot/dts/exynos5420-peach-pit.dt.yaml: interrupt-controller@10481000:
compatible: ['arm,gic-400', 'arm,cortex-a15-gic', 'arm,cortex-a9-gic'] is not valid under any of the given schemas
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 arch/arm/boot/dts/exynos5.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

Applied 1-10.

Best regards,
Krzysztof

Krzysztof Kozlowski

author maintainer

2020-09-01 07:55 UTC #3 lore raw

PATCH 2/13 ARM: dts: exynos: Correct compatible for Exynos5260 GIC

In reply to Krzysztof Kozlowski

Exynos5260 SoCs have ARM GIC 400. Correct the compatibles to match dtschema and fix the dtbs_check warnings like:

arch/arm/boot/dts/exynos5260-xyref5260.dt.yaml: interrupt-controller@10481000:
compatible: ['arm,cortex-a15-gic', 'arm,cortex-a9-gic'] is not valid under any of the given schemas

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5260.dtsi | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/boot/dts/exynos5260.dtsi +1 -1

index 154df70128f3..9b45e052cca9 100644
@@ -162,7 +162,7 @@
 		};
 
 		gic: interrupt-controller@10481000 {
-			compatible = "arm,cortex-a15-gic", "arm,cortex-a9-gic";
+			compatible = "arm,gic-400", "arm,cortex-a15-gic";
 			#interrupt-cells = <3>;
 			#address-cells = <0>;
 			#size-cells = <0>;

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:54 UTC #4 lore raw

PATCH 3/13 ARM: dts: exynos: Remove unneeded address/size cells in Exynos5260 GIC

In reply to Krzysztof Kozlowski

The Exynos5260 GIC node does not have any children so remove the address and size cells as they are not needed by DT bindings. The size-cells of '0' were also incorrect. This fixes dtbs_check warning:

arch/arm/boot/dts/exynos5260-xyref5260.dt.yaml: interrupt-controller@10481000: #size-cells:0:0: 1 was expected

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5260.dtsi | 2 --
 1 file changed, 2 deletions(-)

arch/arm/boot/dts/exynos5260.dtsi +0 -2

index 9b45e052cca9..973448c4ad93 100644
@@ -164,8 +164,6 @@
 		gic: interrupt-controller@10481000 {
 			compatible = "arm,gic-400", "arm,cortex-a15-gic";
 			#interrupt-cells = <3>;
-			#address-cells = <0>;
-			#size-cells = <0>;
 			interrupt-controller;
 			reg = <0x10481000 0x1000>,
 				<0x10482000 0x2000>,

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:54 UTC #5 lore raw

PATCH 4/13 ARM: dts: exynos: Correct S3C RTC bindings in SMDK5410

In reply to Krzysztof Kozlowski

The S3C RTC requires 32768 Hz clock as input which is provided by PMIC. However the PMIC is not described in DTS at all so at least add a workaround to model its clock with a fixed-clock. This fixes S3C RTC and silences dtbs_check warnings like:

arch/arm/boot/dts/exynos5410-smdk5410.dt.yaml: rtc@101e0000: clocks: [[5, 317]] is too short arch/arm/boot/dts/exynos5410-smdk5410.dt.yaml: rtc@101e0000: clock-names: ['rtc'] is too short

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5410-smdk5410.dts | 12 ++++++++++++
 1 file changed, 12 insertions(+)

arch/arm/boot/dts/exynos5410-smdk5410.dts +12 -0

index 5282b5deca86..2a3ade77a2de 100644
@@ -29,6 +29,13 @@
 		#clock-cells = <0>;
 	};
 
+	pmic_ap_clk: pmic-ap-clk {
+		/* Workaround for missing PMIC and its clock */
+		compatible = "fixed-clock";
+		#clock-cells = <0>;
+		clock-frequency = <32768>;
+	};
+
 	firmware@2037000 {
 		compatible = "samsung,secure-firmware";
 		reg = <0x02037000 0x1000>;

@@ -79,6 +86,11 @@
 	};
 };
 
+&rtc {
+	clocks = <&clock CLK_RTC>, <&pmic_ap_clk>;
+	clock-names = "rtc", "rtc_src";
+};
+
 &sromc {
 	pinctrl-names = "default";
 	pinctrl-0 = <&srom_ctl>, <&srom_ebi>;

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:54 UTC #6 lore raw

PATCH 5/13 ARM: dts: exynos: Silence i2c-gpio dtschema warning in Exynos5250 Arndale

In reply to Krzysztof Kozlowski

The name of I2C controller over GPIO lines node ends with '-gpio' which confuses dtschema:

arch/arm/boot/dts/exynos5250-arndale.dt.yaml: soc: i2c-gpio:
{'pinctrl-names': ['default'], ... 'phandle': [[65]]} is not of type 'array' From schema: lib/python3.6/site-packages/dtschema/schemas/gpio/gpio-consumer.yaml

Add a '-10' (there are already 0-9 I2C controllers on the SoC) suffix to silence it. This pattern on naming i2c-gpio is already present in many other dts. No functional change.

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5250-arndale.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/boot/dts/exynos5250-arndale.dts +1 -1

index 59872d83da6e..ec94af640cd5 100644
@@ -624,7 +624,7 @@
 	 * For unknown reasons HDMI-DDC does not work with Exynos I2C
 	 * controllers. Lets use software I2C over GPIO pins as a workaround.
 	 */
-	i2c_ddc: i2c-gpio {
+	i2c_ddc: i2c-10 {
 		pinctrl-names = "default";
 		pinctrl-0 = <&i2c2_gpio_bus>;
 		status = "okay";

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:54 UTC #7 lore raw

PATCH 6/13 ARM: dts: exynos: Correct whitespace and indentation issues in Exynos5

In reply to Krzysztof Kozlowski

Remove double space after '=' and fix indentation in Exynos5250, Exynos5410 and Exynos5420 DTS files.

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5.dtsi                |  8 ++---
 arch/arm/boot/dts/exynos5250-arndale.dts      | 10 +++----
 arch/arm/boot/dts/exynos5250-spring.dts       | 30 +++++++++----------
 arch/arm/boot/dts/exynos5250.dtsi             |  8 ++---
 arch/arm/boot/dts/exynos5410-odroidxu.dts     |  8 ++---
 arch/arm/boot/dts/exynos5410.dtsi             | 12 ++++----
 arch/arm/boot/dts/exynos5420.dtsi             | 16 +++++-----
 arch/arm/boot/dts/exynos5422-odroid-core.dtsi |  4 +--
 8 files changed, 48 insertions(+), 48 deletions(-)

arch/arm/boot/dts/exynos5.dtsi +4 -4

index 9660104be4c9..9ce9fb3fc190 100644
@@ -211,13 +211,13 @@
 		};
 
 		prng: rng@10830400 {
-		      compatible = "samsung,exynos5250-prng";
-		      reg = <0x10830400 0x200>;
+			compatible = "samsung,exynos5250-prng";
+			reg = <0x10830400 0x200>;
 		};
 
 		trng: rng@10830600 {
-		      compatible = "samsung,exynos5250-trng";
-		      reg = <0x10830600 0x100>;
+			compatible = "samsung,exynos5250-trng";
+			reg = <0x10830600 0x100>;
 		};
 
 		g2d: g2d@10850000 {

arch/arm/boot/dts/exynos5250-arndale.dts +5 -5

index ec94af640cd5..f2bcce167b2d 100644
@@ -243,11 +243,11 @@
 		s5m8767,pmic-buck3-dvs-voltage = <1100000>;
 		s5m8767,pmic-buck4-dvs-voltage = <1200000>;
 		s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_HIGH>,
-		                              <&gpd1 1 GPIO_ACTIVE_HIGH>,
-		                              <&gpd1 2 GPIO_ACTIVE_HIGH>;
+					      <&gpd1 1 GPIO_ACTIVE_HIGH>,
+					      <&gpd1 2 GPIO_ACTIVE_HIGH>;
 		s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_HIGH>,
-		                             <&gpx2 4 GPIO_ACTIVE_HIGH>,
-		                             <&gpx2 5 GPIO_ACTIVE_HIGH>;
+					     <&gpx2 4 GPIO_ACTIVE_HIGH>,
+					     <&gpx2 5 GPIO_ACTIVE_HIGH>;
 
 		s5m8767_osc: clocks {
 			compatible = "samsung,s5m8767-clk";

@@ -544,7 +544,7 @@
 	samsung,i2c-max-bus-freq = <40000>;
 	samsung,i2c-slave-addr = <0x38>;
 
-	sata_phy_i2c:sata-phy@38 {
+	sata_phy_i2c: sata-phy@38 {
 		compatible = "samsung,exynos-sataphy-i2c";
 		reg = <0x38>;
 	};

arch/arm/boot/dts/exynos5250-spring.dts +15 ~~-15~~

index 3d501926c227..b6fcf847fc2f 100644
@@ -114,12 +114,12 @@
 		wakeup-source;
 
 		s5m8767,pmic-buck-dvs-gpios = <&gpd1 0 GPIO_ACTIVE_LOW>, /* DVS1 */
-		                              <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */
-		                              <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */
+					      <&gpd1 1 GPIO_ACTIVE_LOW>, /* DVS2 */
+					      <&gpd1 2 GPIO_ACTIVE_LOW>; /* DVS3 */
 
 		s5m8767,pmic-buck-ds-gpios = <&gpx2 3 GPIO_ACTIVE_LOW>, /* SET1 */
-		                             <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */
-		                             <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */
+					     <&gpx2 4 GPIO_ACTIVE_LOW>, /* SET2 */
+					     <&gpx2 5 GPIO_ACTIVE_LOW>; /* SET3 */
 
 		/*
 		 * The following arrays of DVS voltages are not used, since we are

@@ -127,26 +127,26 @@
 		 * to please the driver.
 		 */
 		s5m8767,pmic-buck2-dvs-voltage = <1350000>, <1300000>,
-		                                 <1250000>, <1200000>,
-		                                 <1150000>, <1100000>,
-		                                 <1000000>, <950000>;
+						 <1250000>, <1200000>,
+						 <1150000>, <1100000>,
+						 <1000000>, <950000>;
 
 		s5m8767,pmic-buck3-dvs-voltage = <1100000>, <1100000>,
-		                                 <1100000>, <1100000>,
-		                                 <1000000>, <1000000>,
-		                                 <1000000>, <1000000>;
+						 <1100000>, <1100000>,
+						 <1000000>, <1000000>,
+						 <1000000>, <1000000>;
 
 		s5m8767,pmic-buck4-dvs-voltage = <1200000>, <1200000>,
-		                                 <1200000>, <1200000>,
-		                                 <1200000>, <1200000>,
-		                                 <1200000>, <1200000>;
+						 <1200000>, <1200000>,
+						 <1200000>, <1200000>,
+						 <1200000>, <1200000>;
 
 		clocks {
 			compatible = "samsung,s5m8767-clk";
 			#clock-cells = <1>;
 			clock-output-names = "en32khz_ap",
-			                     "en32khz_cp",
-			                     "en32khz_bt";
+					     "en32khz_cp",
+					     "en32khz_bt";
 		};
 
 		regulators {

arch/arm/boot/dts/exynos5250.dtsi +4 -4

index e3dbe4166836..0249d16e187f 100644
@@ -723,7 +723,7 @@
 			#dma-requests = <1>;
 		};
 
-		gsc_0:  gsc@13e00000 {
+		gsc_0: gsc@13e00000 {
 			compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 			reg = <0x13e00000 0x1000>;
 			interrupts = <GIC_SPI 85 IRQ_TYPE_LEVEL_HIGH>;

@@ -733,7 +733,7 @@
 			iommus = <&sysmmu_gsc0>;
 		};
 
-		gsc_1:  gsc@13e10000 {
+		gsc_1: gsc@13e10000 {
 			compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 			reg = <0x13e10000 0x1000>;
 			interrupts = <GIC_SPI 86 IRQ_TYPE_LEVEL_HIGH>;

@@ -743,7 +743,7 @@
 			iommus = <&sysmmu_gsc1>;
 		};
 
-		gsc_2:  gsc@13e20000 {
+		gsc_2: gsc@13e20000 {
 			compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 			reg = <0x13e20000 0x1000>;
 			interrupts = <GIC_SPI 87 IRQ_TYPE_LEVEL_HIGH>;

@@ -753,7 +753,7 @@
 			iommus = <&sysmmu_gsc2>;
 		};
 
-		gsc_3:  gsc@13e30000 {
+		gsc_3: gsc@13e30000 {
 			compatible = "samsung,exynos5250-gsc", "samsung,exynos5-gsc";
 			reg = <0x13e30000 0x1000>;
 			interrupts = <GIC_SPI 88 IRQ_TYPE_LEVEL_HIGH>;

arch/arm/boot/dts/exynos5410-odroidxu.dts +4 -4

index 4f9297ae0763..75b4150c26d7 100644
@@ -109,10 +109,10 @@
 	assigned-clock-parents = <&clock CLK_FOUT_EPLL>,
 			<&clock_audss EXYNOS_MOUT_AUDSS>;
 
-	assigned-clock-rates =  <0>,
-				<0>,
-				<96000000>,
-				<19200000>;
+	assigned-clock-rates = <0>,
+			       <0>,
+			       <96000000>,
+			       <19200000>;
 };
 
 &cpu0_thermal {

arch/arm/boot/dts/exynos5410.dtsi +6 -6

index abe75b9e39f5..60a87684b1af 100644
@@ -238,16 +238,16 @@
 			#include "exynos5420-trip-points.dtsi"
 		};
 		cpu1_thermal: cpu1-thermal {
-		       thermal-sensors = <&tmu_cpu1>;
-		       #include "exynos5420-trip-points.dtsi"
+			thermal-sensors = <&tmu_cpu1>;
+			#include "exynos5420-trip-points.dtsi"
 		};
 		cpu2_thermal: cpu2-thermal {
-		       thermal-sensors = <&tmu_cpu2>;
-		       #include "exynos5420-trip-points.dtsi"
+			thermal-sensors = <&tmu_cpu2>;
+			#include "exynos5420-trip-points.dtsi"
 		};
 		cpu3_thermal: cpu3-thermal {
-		       thermal-sensors = <&tmu_cpu3>;
-		       #include "exynos5420-trip-points.dtsi"
+			thermal-sensors = <&tmu_cpu3>;
+			#include "exynos5420-trip-points.dtsi"
 		};
 	};
 };

arch/arm/boot/dts/exynos5420.dtsi +8 -8

index c76460b70532..83580f076a58 100644
@@ -1199,20 +1199,20 @@
 			#include "exynos5420-trip-points.dtsi"
 		};
 		cpu1_thermal: cpu1-thermal {
-		       thermal-sensors = <&tmu_cpu1>;
-		       #include "exynos5420-trip-points.dtsi"
+			thermal-sensors = <&tmu_cpu1>;
+			#include "exynos5420-trip-points.dtsi"
 		};
 		cpu2_thermal: cpu2-thermal {
-		       thermal-sensors = <&tmu_cpu2>;
-		       #include "exynos5420-trip-points.dtsi"
+			thermal-sensors = <&tmu_cpu2>;
+			#include "exynos5420-trip-points.dtsi"
 		};
 		cpu3_thermal: cpu3-thermal {
-		       thermal-sensors = <&tmu_cpu3>;
-		       #include "exynos5420-trip-points.dtsi"
+			thermal-sensors = <&tmu_cpu3>;
+			#include "exynos5420-trip-points.dtsi"
 		};
 		gpu_thermal: gpu-thermal {
-		       thermal-sensors = <&tmu_gpu>;
-		       #include "exynos5420-trip-points.dtsi"
+			thermal-sensors = <&tmu_gpu>;
+			#include "exynos5420-trip-points.dtsi"
 		};
 	};
 };

arch/arm/boot/dts/exynos5422-odroid-core.dtsi +2 -2

index afe090578e8f..b1cf9414ce17 100644
@@ -333,8 +333,8 @@
 		compatible	= "samsung,K3QF2F20DB", "jedec,lpddr3";
 		density		= <16384>;
 		io-width	= <32>;
-		#address-cells  = <1>;
-		#size-cells     = <0>;
+		#address-cells	= <1>;
+		#size-cells	= <0>;
 
 		tRFC-min-tck		= <17>;
 		tRRD-min-tck		= <2>;

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:54 UTC #8 lore raw

PATCH 7/13 ARM: dts: exynos: Override thermal by label in Exynos5250

In reply to Krzysztof Kozlowski

Using full paths to extend or override a device tree node is error prone since if there was a typo error, a new node will be created instead of extending the node as it was desired. This will lead to run-time errors that could be hard to detect.

A mistyped label on the other hand, will cause a dtc compile error (during build time).

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5250.dtsi | 38 +++++++++++++++----------------
 1 file changed, 18 insertions(+), 20 deletions(-)

arch/arm/boot/dts/exynos5250.dtsi +18 ~~-20~~

index 0249d16e187f..488d3f9fab59 100644
@@ -1085,26 +1085,6 @@
 		};
 	};
 
-	thermal-zones {
-		cpu_thermal: cpu-thermal {
-			polling-delay-passive = <0>;
-			polling-delay = <0>;
-			thermal-sensors = <&tmu 0>;
-
-			cooling-maps {
-				map0 {
-				     /* Corresponds to 800MHz at freq_table */
-				     cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
-				};
-				map1 {
-				     /* Corresponds to 200MHz at freq_table */
-				     cooling-device = <&cpu0 15 15>,
-						      <&cpu1 15 15>;
-			       };
-		       };
-		};
-	};
-
 	timer {
 		compatible = "arm,armv7-timer";
 		interrupts = <GIC_PPI 13 (GIC_CPU_MASK_SIMPLE(4) | IRQ_TYPE_LEVEL_LOW)>,

@@ -1120,6 +1100,24 @@
 	};
 };
 
+&cpu_thermal {
+	polling-delay-passive = <0>;
+	polling-delay = <0>;
+	thermal-sensors = <&tmu 0>;
+
+	cooling-maps {
+		map0 {
+			/* Corresponds to 800MHz at freq_table */
+			cooling-device = <&cpu0 9 9>, <&cpu1 9 9>;
+		};
+		map1 {
+			/* Corresponds to 200MHz at freq_table */
+			cooling-device = <&cpu0 15 15>,
+					 <&cpu1 15 15>;
+		};
+	};
+};
+
 &dp {
 	power-domains = <&pd_disp1>;
 	clocks = <&clock CLK_DP>;

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:55 UTC #9 lore raw

PATCH 8/13 ARM: dts: exynos: Add max77686 clocks for S3C RTC in SMDK5250

In reply to Krzysztof Kozlowski

Add clock-cells to max77686 PMIC node so its 32 kHz clocks could be used later in the S3C RTC node. Except making the S3C RTC working, this also fixes dtbs_check warnings:

arch/arm/boot/dts/exynos5250-smdk5250.dt.yaml: rtc@101e0000: clocks: [[2, 337]] is too short arch/arm/boot/dts/exynos5250-smdk5250.dt.yaml: rtc@101e0000: clock-names: ['rtc'] is too short

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5250-smdk5250.dts | 6 +++++-
 1 file changed, 5 insertions(+), 1 deletion(-)

arch/arm/boot/dts/exynos5250-smdk5250.dts +5 -1

index 5c42df024adf..00af7fb65080 100644
@@ -7,6 +7,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/clock/maxim,max77686.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include "exynos5250.dtsi"

@@ -129,13 +130,14 @@
 		reg = <0x50>;
 	};
 
-	max77686@9 {
+	max77686: pmic@9 {
 		compatible = "maxim,max77686";
 		reg = <0x09>;
 		interrupt-parent = <&gpx3>;
 		interrupts = <2 IRQ_TYPE_NONE>;
 		pinctrl-names = "default";
 		pinctrl-0 = <&max77686_irq>;
+		#clock-cells = <1>;
 		wakeup-source;
 
 		voltage-regulators {

@@ -368,6 +370,8 @@
 
 &rtc {
 	status = "okay";
+	clocks = <&clock CLK_RTC>, <&max77686 MAX77686_CLK_AP>;
+	clock-names = "rtc", "rtc_src";
 };
 
 &sata {

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:55 UTC #10 lore raw

PATCH 9/13 ARM: dts: exynos: Use S5M8767 clock in S3C RTC in Exynos5250 Spring

In reply to Krzysztof Kozlowski

Use the 32 kHz clock from S5M8767 PMIC in the S3C RTC node. Except making the S3C RTC working, this also fixes dtbs_check warnings:

arch/arm/boot/dts/exynos5250-spring.dt.yaml: rtc@101e0000: clocks: [[2, 337]] is too short arch/arm/boot/dts/exynos5250-spring.dt.yaml: rtc@101e0000: clock-names: ['rtc'] is too short

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5250-spring.dts | 9 ++++++++-
 1 file changed, 8 insertions(+), 1 deletion(-)

arch/arm/boot/dts/exynos5250-spring.dts +8 -1

index b6fcf847fc2f..166a0d287633 100644
@@ -7,6 +7,7 @@
  */
 
 /dts-v1/;
+#include <dt-bindings/clock/samsung,s2mps11.h>
 #include <dt-bindings/gpio/gpio.h>
 #include <dt-bindings/interrupt-controller/irq.h>
 #include <dt-bindings/input/input.h>

@@ -141,7 +142,7 @@
 						 <1200000>, <1200000>,
 						 <1200000>, <1200000>;
 
-		clocks {
+		s5m8767_osc: clocks {
 			compatible = "samsung,s5m8767-clk";
 			#clock-cells = <1>;
 			clock-output-names = "en32khz_ap",

@@ -522,6 +523,12 @@
 	};
 };
 
+&rtc {
+	status = "okay";
+	clocks = <&clock CLK_RTC>, <&s5m8767_osc S2MPS11_CLK_AP>;
+	clock-names = "rtc", "rtc_src";
+};
+
 &sd1_bus4 {
 	samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
 };

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:55 UTC #11 lore raw

PATCH 10/13 ARM: dts: exynos: Silence DP HPD pinctrl dtschema warning in Exynos5250 Spring

In reply to Krzysztof Kozlowski

The pin configuration of Display Port HPD GPIO emds with '-gpio' which confuses dtschema:

arch/arm/boot/dts/exynos5250-spring.dt.yaml: pinctrl@11400000: dp-hpd-gpio:
{'samsung,pins': ['gpc3-0'], ... 'samsung,pin-drv': [[0]], 'phandle': [[23]]} is not of type 'array' From schema: lib/python3.6/site-packages/dtschema/schemas/gpio/gpio-consumer.yaml

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5250-spring.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/boot/dts/exynos5250-spring.dts +1 -1

index 166a0d287633..a92ade33779c 100644
@@ -457,7 +457,7 @@
 		samsung,pin-drv = <EXYNOS4_PIN_DRV_LV1>;
 	};
 
-	dp_hpd_gpio: dp-hpd-gpio {
+	dp_hpd_gpio: dp-hpd {
 		samsung,pins = "gpc3-0";
 		samsung,pin-function = <EXYNOS_PIN_FUNC_INPUT>;
 		samsung,pin-pud = <EXYNOS_PIN_PULL_UP>;

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:55 UTC #12 lore raw

PATCH 11/13 ARM: dts: exynos: Silence SATA PHY warning in Exynos5250 Arndale

In reply to Krzysztof Kozlowski

The SATA PHY in Exynos5250 SoCs has two interfaces and two device nodes:
1. sata-phy@12170000
2. i2c-9/i2c@38

The first node represents the actual SATA PHY device with phy-cells. The second represents additional I2C interface, needed by the driver to communicate with the SATA PHY device. It is not a PHY-provider in the terms of dtschema so rename it to silence dtbs_check warning:

arch/arm/boot/dts/exynos5250-arndale.dt.yaml: sata-phy@38: '#phy-cells' is a required property
From schema: lib/python3.6/site-packages/dtschema/schemas/phy/phy-provider.yaml

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5250-arndale.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/boot/dts/exynos5250-arndale.dts +1 -1

index f2bcce167b2d..3c401c82905c 100644
@@ -544,7 +544,7 @@
 	samsung,i2c-max-bus-freq = <40000>;
 	samsung,i2c-slave-addr = <0x38>;
 
-	sata_phy_i2c: sata-phy@38 {
+	sata_phy_i2c: sata-phy-i2c@38 {
 		compatible = "samsung,exynos-sataphy-i2c";
 		reg = <0x38>;
 	};

Signature · 1 line

2.17.1

Marek Szyprowski

2020-09-01 08:13 UTC #13 lore raw

Re: [PATCH 11/13] ARM: dts: exynos: Silence SATA PHY warning in Exynos5250 Arndale

Hi Krzysztof,

Quoted 22 lines · Krzysztof Kozlowski

The SATA PHY in Exynos5250 SoCs has two interfaces and two device nodes:
1. sata-phy@12170000
2. i2c-9/i2c@38
The first node represents the actual SATA PHY device with phy-cells. The second represents additional I2C interface, needed by the driver to communicate with the SATA PHY device. It is not a PHY-provider in the terms of dtschema so rename it to silence dtbs_check warning:
arch/arm/boot/dts/exynos5250-arndale.dt.yaml: sata-phy@38: '#phy-cells' is a required property
From schema: lib/python3.6/site-packages/dtschema/schemas/phy/phy-provider.yaml
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
  arch/arm/boot/dts/exynos5250-arndale.dts | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/exynos5250-arndale.dts +0 -0
index f2bcce167b2d..3c401c82905c 100644

arch/arm/boot/dts/exynos5250-arndale.dts line 550

Quoted 8 lines

arch/arm/boot/dts/exynos5250-arndale.dts +1 -1

@@ -544,7 +544,7 @@
  	samsung,i2c-max-bus-freq = <40000>;
  	samsung,i2c-slave-addr = <0x38>;
 
-	sata_phy_i2c: sata-phy@38 {
+	sata_phy_i2c: sata-phy-i2c@38 {
  		compatible = "samsung,exynos-sataphy-i2c";
  		reg = <0x38>;
  	};

I'm not against the rename, but frankly, the above node and all i2c parameters should be moved to exynos5250.dtsi. This is a SoC internal things (the same way as hdmiphy in exynos4.dtsi), so the board dts should only contain information like status = "enabled" for i2c_8 and hdmi_i2c_phy nodes. No need to duplicate it here and in smdk5250.dts.

Best regards

Signature · 2 lines

Marek Szyprowski, PhD
Samsung R&D Institute Poland

Krzysztof Kozlowski

author maintainer

2020-09-01 08:17 UTC #14 lore raw

Re: [PATCH 11/13] ARM: dts: exynos: Silence SATA PHY warning in Exynos5250 Arndale

Quoted 29 lines · Marek Szyprowski

Hi Krzysztof,
Quoted 25 lines · Krzysztof Kozlowski
The SATA PHY in Exynos5250 SoCs has two interfaces and two device nodes:
1. sata-phy@12170000
2. i2c-9/i2c@38
The first node represents the actual SATA PHY device with phy-cells. The second represents additional I2C interface, needed by the driver to communicate with the SATA PHY device. It is not a PHY-provider in the terms of dtschema so rename it to silence dtbs_check warning:
arch/arm/boot/dts/exynos5250-arndale.dt.yaml: sata-phy@38: '#phy-cells' is a required property
From schema: lib/python3.6/site-packages/dtschema/schemas/phy/phy-provider.yaml
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
  arch/arm/boot/dts/exynos5250-arndale.dts | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/exynos5250-arndale.dts +0 -0
index f2bcce167b2d..3c401c82905c 100644
@@ -544,7 +544,7 @@
      samsung,i2c-max-bus-freq = <40000>;
      samsung,i2c-slave-addr = <0x38>;
 

Quoted 11 lines

arch/arm/boot/dts/exynos5250-arndale.dts line 550
Quoted 5 lines
arch/arm/boot/dts/exynos5250-arndale.dts +1 -1
-     sata_phy_i2c: sata-phy@38 {
+     sata_phy_i2c: sata-phy-i2c@38 {
              compatible = "samsung,exynos-sataphy-i2c";
              reg = <0x38>;
      };
I'm not against the rename, but frankly, the above node and all i2c parameters should be moved to exynos5250.dtsi. This is a SoC internal things (the same way as hdmiphy in exynos4.dtsi), so the board dts should only contain information like status = "enabled" for i2c_8 and hdmi_i2c_phy nodes. No need to duplicate it here and in smdk5250.dts.

Good point, the I2C bus used here is an internal part of SoC.

I will squash these two changes into a new one. Thanks for the review!

Best regards,
Krzysztof

Krzysztof Kozlowski

author maintainer

2020-09-01 08:19 UTC #15 lore raw

Re: [PATCH 11/13] ARM: dts: exynos: Silence SATA PHY warning in Exynos5250 Arndale

Quoted 43 lines · Krzysztof Kozlowski

Quoted 29 lines · Marek Szyprowski
Hi Krzysztof,
Quoted 25 lines · Krzysztof Kozlowski
The SATA PHY in Exynos5250 SoCs has two interfaces and two device nodes:
1. sata-phy@12170000
2. i2c-9/i2c@38
The first node represents the actual SATA PHY device with phy-cells. The second represents additional I2C interface, needed by the driver to communicate with the SATA PHY device. It is not a PHY-provider in the terms of dtschema so rename it to silence dtbs_check warning:
arch/arm/boot/dts/exynos5250-arndale.dt.yaml: sata-phy@38: '#phy-cells' is a required property
From schema: lib/python3.6/site-packages/dtschema/schemas/phy/phy-provider.yaml
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
  arch/arm/boot/dts/exynos5250-arndale.dts | 2 +-
  1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/exynos5250-arndale.dts +0 -0
index f2bcce167b2d..3c401c82905c 100644
@@ -544,7 +544,7 @@
      samsung,i2c-max-bus-freq = <40000>;
      samsung,i2c-slave-addr = <0x38>;
 
Quoted 11 lines
arch/arm/boot/dts/exynos5250-arndale.dts line 550
Quoted 5 lines
arch/arm/boot/dts/exynos5250-arndale.dts +1 -1
-     sata_phy_i2c: sata-phy@38 {
+     sata_phy_i2c: sata-phy-i2c@38 {
              compatible = "samsung,exynos-sataphy-i2c";
              reg = <0x38>;
      };
I'm not against the rename, but frankly, the above node and all i2c parameters should be moved to exynos5250.dtsi. This is a SoC internal things (the same way as hdmiphy in exynos4.dtsi), so the board dts should only contain information like status = "enabled" for i2c_8 and hdmi_i2c_phy nodes. No need to duplicate it here and in smdk5250.dts.

Quoted 3 lines

Good point, the I2C bus used here is an internal part of SoC.
I will squash these two changes into a new one. Thanks for the review!

While at it, I wonder about the samsung,i2c-slave-addr property. Is it really needed? Are there multiple masters on this bus?

Best regards,
Krzysztof

Marek Szyprowski

2020-09-01 08:36 UTC #16 lore raw

Re: [PATCH 11/13] ARM: dts: exynos: Silence SATA PHY warning in Exynos5250 Arndale

Quoted 38 lines · Krzysztof Kozlowski

Quoted 37 lines · Krzysztof Kozlowski
Quoted 36 lines · Marek Szyprowski
Quoted 22 lines · Krzysztof Kozlowski
The SATA PHY in Exynos5250 SoCs has two interfaces and two device nodes:
1. sata-phy@12170000
2. i2c-9/i2c@38
The first node represents the actual SATA PHY device with phy-cells. The second represents additional I2C interface, needed by the driver to communicate with the SATA PHY device. It is not a PHY-provider in the terms of dtschema so rename it to silence dtbs_check warning:
arch/arm/boot/dts/exynos5250-arndale.dt.yaml: sata-phy@38: '#phy-cells' is a required property
From schema: lib/python3.6/site-packages/dtschema/schemas/phy/phy-provider.yaml
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
   arch/arm/boot/dts/exynos5250-arndale.dts | 2 +-
   1 file changed, 1 insertion(+), 1 deletion(-)
arch/arm/boot/dts/exynos5250-arndale.dts +0 -0
index f2bcce167b2d..3c401c82905c 100644
arch/arm/boot/dts/exynos5250-arndale.dts line 550
Quoted 8 lines
arch/arm/boot/dts/exynos5250-arndale.dts +1 -1
@@ -544,7 +544,7 @@
       samsung,i2c-max-bus-freq = <40000>;
       samsung,i2c-slave-addr = <0x38>;
 
-     sata_phy_i2c: sata-phy@38 {
+     sata_phy_i2c: sata-phy-i2c@38 {
               compatible = "samsung,exynos-sataphy-i2c";
               reg = <0x38>;
       };
I'm not against the rename, but frankly, the above node and all i2c parameters should be moved to exynos5250.dtsi. This is a SoC internal things (the same way as hdmiphy in exynos4.dtsi), so the board dts should only contain information like status = "enabled" for i2c_8 and hdmi_i2c_phy nodes. No need to duplicate it here and in smdk5250.dts.

Quoted 5 lines

Quoted 3 lines
Good point, the I2C bus used here is an internal part of SoC.
I will squash these two changes into a new one. Thanks for the review!
While at it, I wonder about the samsung,i2c-slave-addr property. Is it really needed? Are there multiple masters on this bus?

This might be some cargo-cult, probably copied from HDMI DDC (I'm not sure if it is needed there). I've removed it and SATA still works fine on Exynos5250 Arndale board.

Best regards

Signature · 2 lines

Marek Szyprowski, PhD
Samsung R&D Institute Poland

Krzysztof Kozlowski

author maintainer

2020-09-01 08:42 UTC #17 lore raw

Re: [PATCH 11/13] ARM: dts: exynos: Silence SATA PHY warning in Exynos5250 Arndale

Quoted 7 lines · Marek Szyprowski

Quoted 7 lines
Quoted 7 lines
Quoted 5 lines
I'm not against the rename, but frankly, the above node and all i2c parameters should be moved to exynos5250.dtsi. This is a SoC internal things (the same way as hdmiphy in exynos4.dtsi), so the board dts should only contain information like status = "enabled" for i2c_8 and hdmi_i2c_phy nodes. No need to duplicate it here and in smdk5250.dts.
Good point, the I2C bus used here is an internal part of SoC.

Quoted 7 lines

Quoted 3 lines
Quoted 1 line
I will squash these two changes into a new one. Thanks for the review!
While at it, I wonder about the samsung,i2c-slave-addr property. Is it really needed? Are there multiple masters on this bus?
This might be some cargo-cult, probably copied from HDMI DDC (I'm not sure if it is needed there). I've removed it and SATA still works fine on Exynos5250 Arndale board.

Cool, thanks!

Best regards,
Krzysztof

Krzysztof Kozlowski

author maintainer

2020-09-01 07:55 UTC #18 lore raw

PATCH 12/13 ARM: dts: exynos: Silence SATA PHY warning in SMDK5250

In reply to Krzysztof Kozlowski

The SATA PHY in Exynos5250 SoCs has two interfaces and two device nodes:
1. sata-phy@12170000
2. i2c-9/i2c@38

arch/arm/boot/dts/exynos5250-smdk5250.dt.yaml: sata-phy@38: '#phy-cells' is a required property
From schema: lib/python3.6/site-packages/dtschema/schemas/phy/phy-provider.yaml

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5250-smdk5250.dts | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

arch/arm/boot/dts/exynos5250-smdk5250.dts +1 -1

index 00af7fb65080..e613814da386 100644
@@ -328,7 +328,7 @@
 	samsung,i2c-max-bus-freq = <40000>;
 	samsung,i2c-slave-addr = <0x38>;
 
-	sata_phy_i2c: sata-phy@38 {
+	sata_phy_i2c: sata-phy-i2c@38 {
 		compatible = "samsung,exynos-sataphy-i2c";
 		reg = <0x38>;
 	};

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer

2020-09-01 07:55 UTC #19 lore raw

PATCH 13/13 ARM: dts: exynos: Use S2MPS11 clock in S3C RTC in SMDK5420

In reply to Krzysztof Kozlowski

Use the 32 kHz clock from S2MPS11 PMIC in the S3C RTC node. Except making the S3C RTC working, this also fixes dtbs_check warnings:

arch/arm/boot/dts/exynos5420-smdk5420.dt.yaml: rtc@101e0000: clocks: [[2, 317]] is too short arch/arm/boot/dts/exynos5420-smdk5420.dt.yaml: rtc@101e0000: clock-names: ['rtc'] is too short

Signed-off-by Krzysztof Kozlowski <[email protected]>

---
 arch/arm/boot/dts/exynos5420-smdk5420.dts | 3 +++
 1 file changed, 3 insertions(+)

arch/arm/boot/dts/exynos5420-smdk5420.dts +3 -0

index 83fa800fa1eb..4e49d8095b29 100644
@@ -9,6 +9,7 @@
 /dts-v1/;
 #include "exynos5420.dtsi"
 #include "exynos5420-cpus.dtsi"
+#include <dt-bindings/clock/samsung,s2mps11.h>
 #include <dt-bindings/gpio/gpio.h>
 
 / {

@@ -401,6 +402,8 @@
 
 &rtc {
 	status = "okay";
+	clocks = <&clock CLK_RTC>, <&s2mps11_osc S2MPS11_CLK_AP>;
+	clock-names = "rtc", "rtc_src";
 };
 
 &usbdrd_phy0 {

Signature · 1 line

2.17.1

Krzysztof Kozlowski

author maintainer Applied

2020-09-04 08:59 UTC #20 lore raw

Re: [PATCH 13/13] ARM: dts: exynos: Use S2MPS11 clock in S3C RTC in SMDK5420

Quoted 9 lines · Krzysztof Kozlowski

Use the 32 kHz clock from S2MPS11 PMIC in the S3C RTC node. Except making the S3C RTC working, this also fixes dtbs_check warnings:
arch/arm/boot/dts/exynos5420-smdk5420.dt.yaml: rtc@101e0000: clocks: [[2, 317]] is too short arch/arm/boot/dts/exynos5420-smdk5420.dt.yaml: rtc@101e0000: clock-names: ['rtc'] is too short
Signed-off-by Krzysztof Kozlowski <[email protected]>
---
 arch/arm/boot/dts/exynos5420-smdk5420.dts | 3 +++

Applied.

Best regards,
Krzysztof

Krzysztof Kozlowski

author maintainer

2020-09-01 08:02 UTC #21 lore raw

In reply to Krzysztof Kozlowski

Quoted 7 lines · Krzysztof Kozlowski

Hi,
This is continuation of my series of dtschema cleanup for Exynos SoCs.
The previous series are here:
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t

Except the first one, other links are wrong. Here are correct:
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t
https://lore.kernel.org/linux-samsung-soc/[email protected]/T/#t

Best regards,
Krzysztof