SM8150 and SM8250 dispcc drivers

PATCH Superseded Jonathan Marek 2 participants 10 messages Sep 3, 2020 – Sep 14, 2020 1 message not in the archive

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Device tree bindings Arm Qualcomm mailing list Common clk Arm Qualcomm support +1 more subsystems

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Jonathan Marek

author

2020-09-03 22:27 UTC #0 lore raw

v2 cover SM8150 and SM8250 dispcc drivers

Add display clock drivers required to get DSI and DP displays working on SM8150 and SM8250 SoCs.

Derived from downstream drivers. Notable changes compared to downstream:
- EDP clks removed (nothing uses these even in downstream it seems)
- freq_tbl values for dp_link clk is in Hz and not kHz

v2:
- updated dts example to reflect the change (first patch)
- updated config_ctl_hi1_val in sm8250 dispcc to latest downstream

Jonathan Marek (7):
dt-bindings: clock: sdm845-dispcc: same name for dp_phy clocks as

    sc7180

arm64: dts: qcom: sdm845-dispcc: same name for dp_phy clocks as sc7180
dt-bindings: clock: combine qcom,sdm845-dispcc and qcom,sc7180-dispcc
dt-bindings: clock: Introduce QCOM SM8150 display clock bindings
dt-bindings: clock: Introduce QCOM SM8250 display clock bindings
clk: qcom: Add display clock controller driver for SM8150
clk: qcom: Add display clock controller driver for SM8250

 ...om,sdm845-dispcc.yaml => qcom,dispcc.yaml} |   30 +-
 .../bindings/clock/qcom,sc7180-dispcc.yaml    |   86 --
 arch/arm64/boot/dts/qcom/sdm845.dtsi          |    4 +-
 drivers/clk/qcom/Kconfig                      |   18 +
 drivers/clk/qcom/Makefile                     |    2 +
 drivers/clk/qcom/dispcc-sm8150.c              | 1152 +++++++++++++++++
 drivers/clk/qcom/dispcc-sm8250.c              | 1100 ++++++++++++++++
 .../dt-bindings/clock/qcom,dispcc-sm8150.h    |   69 +
 .../dt-bindings/clock/qcom,dispcc-sm8250.h    |   66 +
 9 files changed, 2428 insertions(+), 99 deletions(-)
 rename Documentation/devicetree/bindings/clock/{qcom,sdm845-dispcc.yaml => qcom,dispcc.yaml} (75%)
 delete mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml
 create mode 100644 drivers/clk/qcom/dispcc-sm8150.c
 create mode 100644 drivers/clk/qcom/dispcc-sm8250.c
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8150.h
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h

Signature · 1 line

2.26.1

Jonathan Marek

author

2020-09-03 22:27 UTC #1 lore raw

PATCH v2 1/7 dt-bindings: clock: sdm845-dispcc: same name for dp_phy clocks as sc7180

This makes it easier to combine dt bindings for sdm845/sc7180 dispcc.

Note: nothing upstream provides these clocks and the sdm845 dispcc driver hasn't switched to using .fw_name for these clocks (these properties are ignored), so changing this shouldn't be a problem.

Signed-off-by Jonathan Marek <[email protected]>

---
 .../devicetree/bindings/clock/qcom,sdm845-dispcc.yaml     | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml +4 -4

index 4a3be733d042..ead44705333b 100644
@@ -43,8 +43,8 @@ properties:
       - const: dsi0_phy_pll_out_dsiclk
       - const: dsi1_phy_pll_out_byteclk
       - const: dsi1_phy_pll_out_dsiclk
-      - const: dp_link_clk_divsel_ten
-      - const: dp_vco_divided_clk_src_mux
+      - const: dp_phy_pll_link_clk
+      - const: dp_phy_pll_vco_div_clk
 
   '#clock-cells':
     const: 1

@@ -92,8 +92,8 @@ examples:
                     "dsi0_phy_pll_out_dsiclk",
                     "dsi1_phy_pll_out_byteclk",
                     "dsi1_phy_pll_out_dsiclk",
-                    "dp_link_clk_divsel_ten",
-                    "dp_vco_divided_clk_src_mux";
+                    "dp_phy_pll_link_clk",
+                    "dp_phy_pll_vco_div_clk";
       #clock-cells = <1>;
       #reset-cells = <1>;
       #power-domain-cells = <1>;

Signature · 1 line

2.26.1

Jonathan Marek

author

2020-09-03 22:27 UTC #2 lore raw

PATCH v2 2/7 arm64: dts: qcom: sdm845-dispcc: same name for dp_phy clocks as sc7180

In reply to Jonathan Marek

This makes it easier to combine dt bindings for sdm845/sc7180 dispcc.

Note: nothing upstream provides these clocks and the sdm845 dispcc driver hasn't switched to using .fw_name for these clocks (these properties are ignored), so changing this shouldn't be a problem.

Signed-off-by Jonathan Marek <[email protected]>

---
 arch/arm64/boot/dts/qcom/sdm845.dtsi | 4 ++--
 1 file changed, 2 insertions(+), 2 deletions(-)

arch/arm64/boot/dts/qcom/sdm845.dtsi +2 -2

index 2884577dcb77..8184d6204b33 100644
@@ -4139,8 +4139,8 @@ dispcc: clock-controller@af00000 {
 				      "dsi0_phy_pll_out_dsiclk",
 				      "dsi1_phy_pll_out_byteclk",
 				      "dsi1_phy_pll_out_dsiclk",
-				      "dp_link_clk_divsel_ten",
-				      "dp_vco_divided_clk_src_mux";
+				      "dp_phy_pll_link_clk",
+				      "dp_phy_pll_vco_div_clk";
 			#clock-cells = <1>;
 			#reset-cells = <1>;
 			#power-domain-cells = <1>;

Signature · 1 line

2.26.1

Jonathan Marek

author

2020-09-03 22:28 UTC #3 lore raw

PATCH v2 3/7 dt-bindings: clock: combine qcom,sdm845-dispcc and qcom,sc7180-dispcc

In reply to Jonathan Marek

These two bindings are almost identical, so combine them into one. This will make it easier to add the sm8150 and sm8250 dispcc bindings.

Signed-off-by Jonathan Marek <[email protected]>

---
 ...om,sdm845-dispcc.yaml => qcom,dispcc.yaml} | 18 ++--
 .../bindings/clock/qcom,sc7180-dispcc.yaml    | 86 -------------------
 2 files changed, 11 insertions(+), 93 deletions(-)
 rename Documentation/devicetree/bindings/clock/{qcom,sdm845-dispcc.yaml => qcom,dispcc.yaml} (85%)
 delete mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml

Documentation/devicetree/bindings/clock/qcom,dispcc.yaml renamed from Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml +11 -7

similarity index 85%
rename from Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
rename to Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
index ead44705333b..ef0321ace786 100644
@@ -1,23 +1,27 @@
 # SPDX-License-Identifier: GPL-2.0-only
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
+$id: http://devicetree.org/schemas/clock/qcom,dispcc.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Display Clock & Reset Controller Binding for SDM845
+title: Qualcomm Display Clock & Reset Controller Binding
 
 maintainers:
   - Taniya Das <[email protected]>
 
 description: |
   Qualcomm display clock control module which supports the clocks, resets and
-  power domains on SDM845.
+  power domains on SDM845/SC7180.
 
-  See also dt-bindings/clock/qcom,dispcc-sdm845.h.
+  See also:
+    dt-bindings/clock/qcom,dispcc-sdm845.h
+    dt-bindings/clock/qcom,dispcc-sc7180.h
 
 properties:
   compatible:
-    const: qcom,sdm845-dispcc
+    enum:
+      - qcom,sdm845-dispcc
+      - qcom,sc7180-dispcc
 
   # NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
   # The code had to use hardcoded mechanisms to find the input clocks.

@@ -25,8 +29,8 @@ properties:
   clocks:
     items:
       - description: Board XO source
-      - description: GPLL0 source from GCC
-      - description: GPLL0 div source from GCC
+      - description: GPLL0 source from GCC (sdm845 only)
+      - description: GPLL0 div source from GCC (sdm845 only)
       - description: Byte clock from DSI PHY0
       - description: Pixel clock from DSI PHY0
       - description: Byte clock from DSI PHY1

Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml deleted +0 ~~-86~~

86 lines not on this page · raw message

Signature · 1 line

2.26.1

Jonathan Marek

author

2020-09-03 22:28 UTC #4 lore raw

PATCH v2 4/7 dt-bindings: clock: Introduce QCOM SM8150 display clock bindings

In reply to Jonathan Marek

Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM8150 SoCs.

Signed-off-by Jonathan Marek <[email protected]>

---
 .../bindings/clock/qcom,dispcc.yaml           |  4 +-
 .../dt-bindings/clock/qcom,dispcc-sm8150.h    | 69 +++++++++++++++++++
 2 files changed, 72 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8150.h

Documentation/devicetree/bindings/clock/qcom,dispcc.yaml +3 -1

index ef0321ace786..5b5c7fa6375e 100644
@@ -11,17 +11,19 @@ maintainers:
 
 description: |
   Qualcomm display clock control module which supports the clocks, resets and
-  power domains on SDM845/SC7180.
+  power domains on SDM845/SC7180/SM8150.
 
   See also:
     dt-bindings/clock/qcom,dispcc-sdm845.h
     dt-bindings/clock/qcom,dispcc-sc7180.h
+    dt-bindings/clock/qcom,dispcc-sm8150.h
 
 properties:
   compatible:
     enum:
       - qcom,sdm845-dispcc
       - qcom,sc7180-dispcc
+      - qcom,sm8150-dispcc
 
   # NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
   # The code had to use hardcoded mechanisms to find the input clocks.

include/dt-bindings/clock/qcom,dispcc-sm8150.h new file +69 -0

69 lines not on this page · raw message

Signature · 1 line

2.26.1

Jonathan Marek

author

2020-09-03 22:27 UTC #5 lore raw

PATCH v2 5/7 dt-bindings: clock: Introduce QCOM SM8250 display clock bindings

In reply to Jonathan Marek

Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM8250 SoCs.

Signed-off-by Jonathan Marek <[email protected]>

---
 .../bindings/clock/qcom,dispcc.yaml           |  4 +-
 .../dt-bindings/clock/qcom,dispcc-sm8250.h    | 66 +++++++++++++++++++
 2 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h

Documentation/devicetree/bindings/clock/qcom,dispcc.yaml +3 -1

index 5b5c7fa6375e..0b905a4e9ada 100644
@@ -11,12 +11,13 @@ maintainers:
 
 description: |
   Qualcomm display clock control module which supports the clocks, resets and
-  power domains on SDM845/SC7180/SM8150.
+  power domains on SDM845/SC7180/SM8150/SM8250.
 
   See also:
     dt-bindings/clock/qcom,dispcc-sdm845.h
     dt-bindings/clock/qcom,dispcc-sc7180.h
     dt-bindings/clock/qcom,dispcc-sm8150.h
+    dt-bindings/clock/qcom,dispcc-sm8250.h
 
 properties:
   compatible:

@@ -24,6 +25,7 @@ properties:
       - qcom,sdm845-dispcc
       - qcom,sc7180-dispcc
       - qcom,sm8150-dispcc
+      - qcom,sm8250-dispcc
 
   # NOTE: sdm845.dtsi existed for quite some time and specified no clocks.
   # The code had to use hardcoded mechanisms to find the input clocks.

include/dt-bindings/clock/qcom,dispcc-sm8250.h new file +66 -0

66 lines not on this page · raw message

Signature · 1 line

2.26.1

Jonathan Marek

author

2020-09-03 22:27 UTC #6 lore raw

PATCH v2 6/7 clk: qcom: Add display clock controller driver for SM8150

In reply to Jonathan Marek

Add support for the display clock controller found on SM8150 based devices. This would allow display drivers to probe and control their clocks.

Signed-off-by Jonathan Marek <[email protected]>

---
 drivers/clk/qcom/Kconfig         |    9 +
 drivers/clk/qcom/Makefile        |    1 +
 drivers/clk/qcom/dispcc-sm8150.c | 1152 ++++++++++++++++++++++++++++++
 3 files changed, 1162 insertions(+)
 create mode 100644 drivers/clk/qcom/dispcc-sm8150.c

drivers/clk/qcom/Kconfig +9 -0

index 058327310c25..b8f82e7495ba 100644
@@ -444,6 +444,15 @@ config SM_GPUCC_8250
 	  Say Y if you want to support graphics controller devices and
 	  functionality such as 3D graphics.
 
+config SM_DISPCC_8150
+	tristate "SM8150 Display Clock Controller"
+	select SM_GCC_8150
+	help
+	  Support for the display clock controller on Qualcomm Technologies, Inc
+	  SM8150 devices.
+	  Say Y if you want to support display devices and functionality such as
+	  splash screen.
+
 config SPMI_PMIC_CLKDIV
 	tristate "SPMI PMIC clkdiv Support"
 	depends on SPMI || COMPILE_TEST

drivers/clk/qcom/Makefile +1 -0

index 9677e769e7e9..edea87f1c7e6 100644
@@ -64,6 +64,7 @@ obj-$(CONFIG_SDM_GCC_845) += gcc-sdm845.o
 obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
 obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
+obj-$(CONFIG_SM_DISPCC_8150) += dispcc-sm8150.o
 obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
 obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
 obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o

drivers/clk/qcom/dispcc-sm8150.c new file +1152 -0

1,152 lines not on this page · raw message

Signature · 1 line

2.26.1

Jonathan Marek

author

2020-09-03 22:27 UTC #7 lore raw

PATCH v2 7/7 clk: qcom: Add display clock controller driver for SM8250

In reply to Jonathan Marek

Add support for the display clock controller found on SM8250 based devices. This would allow display drivers to probe and control their clocks.

Signed-off-by Jonathan Marek <[email protected]>

---
 drivers/clk/qcom/Kconfig         |    9 +
 drivers/clk/qcom/Makefile        |    1 +
 drivers/clk/qcom/dispcc-sm8250.c | 1100 ++++++++++++++++++++++++++++++
 3 files changed, 1110 insertions(+)
 create mode 100644 drivers/clk/qcom/dispcc-sm8250.c

drivers/clk/qcom/Kconfig +9 -0

index b8f82e7495ba..6aee0b8ca897 100644
@@ -453,6 +453,15 @@ config SM_DISPCC_8150
 	  Say Y if you want to support display devices and functionality such as
 	  splash screen.
 
+config SM_DISPCC_8250
+	tristate "SM8250 Display Clock Controller"
+	select SM_GCC_8250
+	help
+	  Support for the display clock controller on Qualcomm Technologies, Inc
+	  SM8250 devices.
+	  Say Y if you want to support display devices and functionality such as
+	  splash screen.
+
 config SPMI_PMIC_CLKDIV
 	tristate "SPMI PMIC clkdiv Support"
 	depends on SPMI || COMPILE_TEST

drivers/clk/qcom/Makefile +1 -0

index edea87f1c7e6..8eb395d02a32 100644
@@ -65,6 +65,7 @@ obj-$(CONFIG_SDM_GPUCC_845) += gpucc-sdm845.o
 obj-$(CONFIG_SDM_LPASSCC_845) += lpasscc-sdm845.o
 obj-$(CONFIG_SDM_VIDEOCC_845) += videocc-sdm845.o
 obj-$(CONFIG_SM_DISPCC_8150) += dispcc-sm8150.o
+obj-$(CONFIG_SM_DISPCC_8250) += dispcc-sm8250.o
 obj-$(CONFIG_SM_GCC_8150) += gcc-sm8150.o
 obj-$(CONFIG_SM_GCC_8250) += gcc-sm8250.o
 obj-$(CONFIG_SM_GPUCC_8150) += gpucc-sm8150.o

drivers/clk/qcom/dispcc-sm8250.c new file +1100 -0

1,100 lines not on this page · raw message

Signature · 1 line

2.26.1

Dmitry Baryshkov

Tested-by on the v2 series

2020-09-07 16:30 UTC #8 lore raw

In reply to Jonathan Marek

Quoted 6 lines · Jonathan Marek

Add display clock drivers required to get DSI and DP displays working on SM8150 and SM8250 SoCs.
Derived from downstream drivers. Notable changes compared to downstream:
- EDP clks removed (nothing uses these even in downstream it seems)
- freq_tbl values for dp_link clk is in Hz and not kHz

On SM8250:

Tested-by Dmitry Baryshkov <[email protected]>

Quoted 32 lines

v2:
- updated dts example to reflect the change (first patch)
- updated config_ctl_hi1_val in sm8250 dispcc to latest downstream
Jonathan Marek (7):
dt-bindings: clock: sdm845-dispcc: same name for dp_phy clocks as
     sc7180
arm64: dts: qcom: sdm845-dispcc: same name for dp_phy clocks as sc7180
dt-bindings: clock: combine qcom,sdm845-dispcc and qcom,sc7180-dispcc
dt-bindings: clock: Introduce QCOM SM8150 display clock bindings
dt-bindings: clock: Introduce QCOM SM8250 display clock bindings
clk: qcom: Add display clock controller driver for SM8150
clk: qcom: Add display clock controller driver for SM8250
  ...om,sdm845-dispcc.yaml => qcom,dispcc.yaml} |   30 +-
  .../bindings/clock/qcom,sc7180-dispcc.yaml    |   86 --
  arch/arm64/boot/dts/qcom/sdm845.dtsi          |    4 +-
  drivers/clk/qcom/Kconfig                      |   18 +
  drivers/clk/qcom/Makefile                     |    2 +
  drivers/clk/qcom/dispcc-sm8150.c              | 1152 +++++++++++++++++
  drivers/clk/qcom/dispcc-sm8250.c              | 1100 ++++++++++++++++
  .../dt-bindings/clock/qcom,dispcc-sm8150.h    |   69 +
  .../dt-bindings/clock/qcom,dispcc-sm8250.h    |   66 +
  9 files changed, 2428 insertions(+), 99 deletions(-)
rename Documentation/devicetree/bindings/clock/{qcom,sdm845-dispcc.yaml => qcom,dispcc.yaml} (75%) delete mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml create mode 100644 drivers/clk/qcom/dispcc-sm8150.c
create mode 100644 drivers/clk/qcom/dispcc-sm8250.c
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8150.h
create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h

Signature · 2 lines

With best wishes
Dmitry

A message that is not in the archive (sent off-list or not yet received): 160012787871.4188128.16710718496771467444@swboyd.mtv.corp.google.com

Jonathan Marek

author

2020-09-14 23:59 UTC #10 lore raw

Quoted 10 lines · Stephen Boyd

Quoting Dmitry Baryshkov (2020-09-07 07:25:45)
Quoted 9 lines · Jonathan Marek
Quoted 6 lines
Add display clock drivers required to get DSI and DP displays working on SM8150 and SM8250 SoCs.
Derived from downstream drivers. Notable changes compared to downstream:
- EDP clks removed (nothing uses these even in downstream it seems)
- freq_tbl values for dp_link clk is in Hz and not kHz

Quoted 5 lines

Quoted 2 lines
On SM8250:
Tested-by Dmitry Baryshkov <[email protected]>
Can this be carried to v3?

I already included the tag in the last commit which adds the SM8250 dispcc driver (probably should've included it in the SM8250 dt-bindings patch too though).