SM8150 and SM8250 dispcc drivers

This makes it easier to combine dt bindings for sdm845/sc7180 dispcc.

Note: nothing upstream provides these clocks and the sdm845 dispcc driver hasn't switched to using .fw_name for these clocks (these properties are ignored), so changing this shouldn't be a problem.

Signed-off-by Jonathan Marek <[email protected]>

---
 .../devicetree/bindings/clock/qcom,sdm845-dispcc.yaml     | 8 ++++----
 1 file changed, 4 insertions(+), 4 deletions(-)

These two bindings are almost identical, so combine them into one. This will make it easier to add the sm8150 and sm8250 dispcc bindings.

Signed-off-by Jonathan Marek <[email protected]>

---
 ...om,sdm845-dispcc.yaml => qcom,dispcc.yaml} | 18 ++--
 .../bindings/clock/qcom,sc7180-dispcc.yaml    | 86 -------------------
 2 files changed, 12 insertions(+), 92 deletions(-)
 rename Documentation/devicetree/bindings/clock/{qcom,sdm845-dispcc.yaml => qcom,dispcc.yaml} (86%)
 delete mode 100644 Documentation/devicetree/bindings/clock/qcom,sc7180-dispcc.yaml

Documentation/devicetree/bindings/clock/qcom,dispcc.yaml renamed from Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml +2 -2

similarity index 86%
rename from Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml
rename to Documentation/devicetree/bindings/clock/qcom,dispcc.yaml
index ead44705333b..7d5b25dfe0b1 100644
@@ -1,32 +1,37 @@
 # SPDX-License-Identifier: GPL-2.0-only
 %YAML 1.2
 ---
-$id: http://devicetree.org/schemas/clock/qcom,sdm845-dispcc.yaml#
+$id: http://devicetree.org/schemas/clock/qcom,dispcc.yaml#
 $schema: http://devicetree.org/meta-schemas/core.yaml#
 
-title: Qualcomm Display Clock & Reset Controller Binding for SDM845
+title: Qualcomm Display Clock & Reset Controller Binding
 
 maintainers:
   - Taniya Das <[email protected]>

Documentation/devicetree/bindings/clock/qcom,dispcc.yaml renamed from Documentation/devicetree/bindings/clock/qcom,sdm845-dispcc.yaml +1 -0

       - description: Byte clock from DSI PHY0
       - description: Pixel clock from DSI PHY0
       - description: Byte clock from DSI PHY1

@@ -35,6 +40,7 @@ properties:
       - description: VCO DIV clock from DP PHY
 
   clock-names:
+    minItems: 8
     items:
       - const: bi_tcxo
       - const: gcc_disp_gpll0_clk_src

Add device tree bindings for display clock controller for Qualcomm Technology Inc's SM8250 SoCs.

Signed-off-by Jonathan Marek <[email protected]>

---

 .../bindings/clock/qcom,dispcc.yaml           |  4 +-
 .../dt-bindings/clock/qcom,dispcc-sm8250.h    | 66 +++++++++++++++++++
 2 files changed, 69 insertions(+), 1 deletion(-)
 create mode 100644 include/dt-bindings/clock/qcom,dispcc-sm8250.h

Add support for the display clock controller found on SM8150 based devices. This would allow display drivers to probe and control their clocks.

Signed-off-by Jonathan Marek <[email protected]>

---
 drivers/clk/qcom/Kconfig         |    9 +
 drivers/clk/qcom/Makefile        |    1 +
 drivers/clk/qcom/dispcc-sm8150.c | 1152 ++++++++++++++++++++++++++++++
 3 files changed, 1162 insertions(+)
 create mode 100644 drivers/clk/qcom/dispcc-sm8150.c

Quoting Jonathan Marek (2020-09-11 08:34:06)

Quoted 11 lines

Add support for the display clock controller found on SM8150 based devices. This would allow display drivers to probe and control their clocks.

Signed-off-by Jonathan Marek <[email protected]>

---
  drivers/clk/qcom/Kconfig         |    9 +
  drivers/clk/qcom/Makefile        |    1 +
  drivers/clk/qcom/dispcc-sm8150.c | 1152 ++++++++++++++++++++++++++++++
  3 files changed, 1162 insertions(+)

create mode 100644 drivers/clk/qcom/dispcc-sm8150.c

If the bindings are the same for these two drivers I wonder if there is anything different between the two. Maybe the two drivers can be one driver?

Quoted 13 lines

Quoting Jonathan Marek (2020-09-11 08:34:06)

Quoted 11 lines

Add support for the display clock controller found on SM8150 based devices. This would allow display drivers to probe and control their clocks.

Signed-off-by Jonathan Marek <[email protected]>

---
  drivers/clk/qcom/Kconfig         |    9 +
  drivers/clk/qcom/Makefile        |    1 +
  drivers/clk/qcom/dispcc-sm8150.c | 1152 ++++++++++++++++++++++++++++++
  3 files changed, 1162 insertions(+)

create mode 100644 drivers/clk/qcom/dispcc-sm8150.c

Quoted 4 lines

If the bindings are the same for these two drivers I wonder if there is anything different between the two. Maybe the two drivers can be one driver?

Possibly, the biggest difference seems to be the plls (trion vs lucid, different config), which could be resolved in the probe() function. If you think combining the drivers is the right thing to do then I can do that.

drivers/clk/qcom/dispcc-sm8250.c new file +5 -0

new file mode 100644
index 000000000000..7c0f384a3a42
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+

drivers/clk/qcom/dispcc-sm8250.c new file +29 -0

+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
+       F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
+       .cmd_rcgr = 0x22bc,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_3,
+       .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_ahb_clk_src",
+               .parent_data = disp_cc_parent_data_3,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_shared_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       { }
+};
+

drivers/clk/qcom/dispcc-sm8250.c new file +87 -0

+               .ops = &clk_byte2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
+       .cmd_rcgr = 0x212c,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_2,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_byte1_clk_src",
+               .parent_data = disp_cc_parent_data_2,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_byte2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
+       .cmd_rcgr = 0x2240,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_1,
+       .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_aux1_clk_src",
+               .parent_data = disp_cc_parent_data_1,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
+       .cmd_rcgr = 0x21dc,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_1,
+       .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_aux_clk_src",
+               .parent_data = disp_cc_parent_data_1,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = {
+       F(162000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+       F(270000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+       F(540000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+       F(810000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
+       .cmd_rcgr = 0x220c,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_link1_clk_src",
+               .parent_data = disp_cc_parent_data_0,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
+       .cmd_rcgr = 0x2178,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_link_clk_src",
+               .parent_data = disp_cc_parent_data_0,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {

drivers/clk/qcom/dispcc-sm8250.c new file +17 -0

+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
+       .cmd_rcgr = 0x21f4,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_pixel2_clk_src",
+               .parent_data = disp_cc_parent_data_0,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_dp_ops,
+       },
+};
+

Quoting Jonathan Marek (2020-09-11 08:34:07)

Quoted 11 lines

drivers/clk/qcom/dispcc-sm8250.c new file +5 -0

new file mode 100644
index 000000000000..7c0f384a3a42
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+

[...]

drivers/clk/qcom/dispcc-sm8250.c line 166

Quoted 5 lines

drivers/clk/qcom/dispcc-sm8250.c new file +5 -0

+
+static const struct clk_parent_data disp_cc_parent_data_6[] = {
+       { .fw_name = "bi_tcxo" },
+       { .fw_name = "dsi0_phy_pll_out_dsiclk" },
+       { .fw_name = "dsi1_phy_pll_out_dsiclk" },

Can we remove clk postfix on these clk names?

Quoted 29 lines

drivers/clk/qcom/dispcc-sm8250.c new file +29 -0

+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_ahb_clk_src[] = {
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       F(37500000, P_DISP_CC_PLL1_OUT_MAIN, 16, 0, 0),
+       F(75000000, P_DISP_CC_PLL1_OUT_MAIN, 8, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_ahb_clk_src = {
+       .cmd_rcgr = 0x22bc,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_3,
+       .freq_tbl = ftbl_disp_cc_mdss_ahb_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_ahb_clk_src",
+               .parent_data = disp_cc_parent_data_3,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_3),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_shared_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_byte0_clk_src[] = {
+       F(19200000, P_BI_TCXO, 1, 0, 0),
+       { }
+};
+

drivers/clk/qcom/dispcc-sm8250.c line 205

Quoted 10 lines

drivers/clk/qcom/dispcc-sm8250.c new file +10 -0

+static struct clk_rcg2 disp_cc_mdss_byte0_clk_src = {
+       .cmd_rcgr = 0x2110,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_2,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_byte0_clk_src",
+               .parent_data = disp_cc_parent_data_2,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,

Why do we need CLK_GET_RATE_NOCACHE? Please remove it.

Quoted 87 lines

drivers/clk/qcom/dispcc-sm8250.c new file +87 -0

+               .ops = &clk_byte2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_byte1_clk_src = {
+       .cmd_rcgr = 0x212c,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_2,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_byte1_clk_src",
+               .parent_data = disp_cc_parent_data_2,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_2),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_byte2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_aux1_clk_src = {
+       .cmd_rcgr = 0x2240,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_1,
+       .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_aux1_clk_src",
+               .parent_data = disp_cc_parent_data_1,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_aux_clk_src = {
+       .cmd_rcgr = 0x21dc,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_1,
+       .freq_tbl = ftbl_disp_cc_mdss_byte0_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_aux_clk_src",
+               .parent_data = disp_cc_parent_data_1,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_1),
+               .flags = CLK_SET_RATE_PARENT,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static const struct freq_tbl ftbl_disp_cc_mdss_dp_link1_clk_src[] = {
+       F(162000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+       F(270000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+       F(540000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+       F(810000000, P_DP_PHY_PLL_LINK_CLK, 1, 0, 0),
+       { }
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_link1_clk_src = {
+       .cmd_rcgr = 0x220c,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_link1_clk_src",
+               .parent_data = disp_cc_parent_data_0,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_link_clk_src = {
+       .cmd_rcgr = 0x2178,
+       .mnd_width = 0,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .freq_tbl = ftbl_disp_cc_mdss_dp_link1_clk_src,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_link_clk_src",
+               .parent_data = disp_cc_parent_data_0,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_rcg2_ops,
+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_pixel1_clk_src = {

drivers/clk/qcom/dispcc-sm8250.c line 302

Quoted 10 lines

drivers/clk/qcom/dispcc-sm8250.c new file +10 -0

+       .cmd_rcgr = 0x21c4,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_pixel1_clk_src",
+               .parent_data = disp_cc_parent_data_0,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_dp_ops,

This is affected by the patch I just applied 355a7d754b92 ("clk: qcom:
dispcc: Update DP clk ops for phy design"). Please resend.

Quoted 17 lines

drivers/clk/qcom/dispcc-sm8250.c new file +17 -0

+       },
+};
+
+static struct clk_rcg2 disp_cc_mdss_dp_pixel2_clk_src = {
+       .cmd_rcgr = 0x21f4,
+       .mnd_width = 16,
+       .hid_width = 5,
+       .parent_map = disp_cc_parent_map_0,
+       .clkr.hw.init = &(struct clk_init_data){
+               .name = "disp_cc_mdss_dp_pixel2_clk_src",
+               .parent_data = disp_cc_parent_data_0,
+               .num_parents = ARRAY_SIZE(disp_cc_parent_data_0),
+               .flags = CLK_SET_RATE_PARENT | CLK_GET_RATE_NOCACHE,
+               .ops = &clk_dp_ops,
+       },
+};
+

Quoted 13 lines

Quoting Jonathan Marek (2020-09-11 08:34:07)

Quoted 11 lines

drivers/clk/qcom/dispcc-sm8250.c new file +5 -0

new file mode 100644
index 000000000000..7c0f384a3a42
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+

[...]

Quoted 8 lines

drivers/clk/qcom/dispcc-sm8250.c line 166

Quoted 5 lines

drivers/clk/qcom/dispcc-sm8250.c new file +5 -0

+
+static const struct clk_parent_data disp_cc_parent_data_6[] = {
+       { .fw_name = "bi_tcxo" },
+       { .fw_name = "dsi0_phy_pll_out_dsiclk" },
+       { .fw_name = "dsi1_phy_pll_out_dsiclk" },

Can we remove clk postfix on these clk names?

This is consistent with the names used in both sdm845 and sc7180 drivers. If this should change then those should be changed too?

Quoting Jonathan Marek (2020-09-23 09:10:04)

Quoted 23 lines · Stephen Boyd

Quoted 21 lines

Quoting Jonathan Marek (2020-09-11 08:34:07)

Quoted 11 lines

drivers/clk/qcom/dispcc-sm8250.c new file +5 -0

new file mode 100644
index 000000000000..7c0f384a3a42
@@ -0,0 +1,1100 @@
+// SPDX-License-Identifier: GPL-2.0
+/*
+ * Copyright (c) 2018-2020, The Linux Foundation. All rights reserved.
+ */
+

[...]

drivers/clk/qcom/dispcc-sm8250.c line 166

Quoted 5 lines

drivers/clk/qcom/dispcc-sm8250.c new file +5 -0

+
+static const struct clk_parent_data disp_cc_parent_data_6[] = {
+       { .fw_name = "bi_tcxo" },
+       { .fw_name = "dsi0_phy_pll_out_dsiclk" },
+       { .fw_name = "dsi1_phy_pll_out_dsiclk" },

Can we remove clk postfix on these clk names?

Quoted 2 lines

This is consistent with the names used in both sdm845 and sc7180 drivers. If this should change then those should be changed too?

If DT isn't using it already then it sounds OK to change the other SoCs. Otherwise fix it just for this one.